Current implementation always sets odd/even bit for ISO transactions.
This is a good strategy only if interval is 1.
For ISO endpoint interval in (micro)frames is computed as
2^(interval-1), which means that odd/frame number should stay
same for interval values > 1.
With this change only when interval is 1 odd/even bit is modified.
dcd_edpt_close() no longer modifies FIFO distribution.
Code that that was commented out is removed along with
variables that are no longer used.
FIFO distribution among endpoints is handled upfront
and does not need to be modified in open and close endpoint
functions.
Recommended FIFO allocation schema includes 2 maximum endpoint sizes.
Comment suggested that this is the case while it would work according
to this description only in checked endpoints were ascending sizes.
Also two same size endpoints would be counted as one.
That is fixed by way sz is filled.
Calculation used too much modulo operation while single division was enough
to account for odd FIFO sizes.
Extra space that is evenly distributed between Bulk and control endpoints
was incorrectly calculated it could prevent allocation of ISO endpoint FIFO
when bulk endpoints existed with smaller endpoint numbers.
Minimum endpoint FIFO size is 16 32bit words, FIFO space requirement is
now observed.
Endpoint close was implemented only in one driver so far.
This function is needed for interfaces with several alternate settings.
The way FIFO is allocated in dcd_edpt_open() allows to correctly close
only one IN endpoint (the one that was opened last).
Wrong FIFO was flushed in dcd_edpt_stall().
(epnum - 1) should only be used when accessing DIEPTXF registers.
For DIEPCTL and GRSTCTL epnum is correct index.
For ISO endpoint driver has to specify when data
is to be transmitted (odd or even frame).
Currently code was not updating this bit resulting in
data being sent every other frame.
If interval was 1ms full data packed was sent every 2ms, and
ZLP was sent in between.
While the ST code has a 2 ms stabilization delay for the USBC PHY PLL,
running without this delay showed no problem for at leat 10 USB un/replug
cycles. Observe for problems!
FIXME: Allow run-time selection to allow to handle both HS and FS with
one file
F746 HS port enumerates with error
config 1 interface 2 altsetting 0 bulk endpoint 0x3 has invalid maxpacket 64
- Use register based XFRSIZ to determine transfer complete
(xfer->queued_len and xfer->short_packet were deleted)
- Pop out as many RxFIFO data entries as available within a IRQ call
- less application interruption due to XFRC calls
Changes:
- checking if tx buffer empty interrupt is masked
- process more than one packet in isr
- mask tx buffer empty just after all bytes were written
- use of transmit_fifo_packet instead of transmit_packet
For IN endpoints output FIFO is filled in interrupt, therefor before
endpoint is enabled, DIEPTSIZ is set with correct size of packet.
Then endpoint is enabled and FIFO empty interrupt is enabled.
This works fine except for the ZLP. Enabling FIFO empty interrupt
results in interrupt handler being called all the time because
there is nothing to put in the FIFO.
Eventually it ends when IN token is received and empty
packed is transmitted out.
This change does not enable FIFO empty interrupt for ZLP reducing
CPU load.
Reinhard Panhuber