suporting multiple port (OTG FS + HS) for stm32
This commit is contained in:
hathach
parent
fad088719e
commit
b7ab60aa44
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@ -82,6 +82,33 @@
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#include "device/dcd.h"
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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typedef struct
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{
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uint32_t regs; // registers
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const IRQn_Type irqnum; // IRQ number
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// const uint8_t ep_count; // Max bi-directional Endpoints
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}dcd_rhport_t;
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// To be consistent across stm32 port. We will number OTG_FS as Rhport0, and OTG_HS as Rhport1
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static const dcd_rhport_t _dcd_rhport[] =
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{
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{ .regs = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn }
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#ifdef USB_OTG_HS
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,{ .regs = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn }
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#endif
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};
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#define DEVICE_BASE(_port) (USB_OTG_DeviceTypeDef *) (_dcd_rhport[_port].regs + USB_OTG_DEVICE_BASE)
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#define OUT_EP_BASE(_port) (USB_OTG_OUTEndpointTypeDef *) (_dcd_rhport[_port].regs + USB_OTG_OUT_ENDPOINT_BASE)
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#define IN_EP_BASE(_port) (USB_OTG_INEndpointTypeDef *) (_dcd_rhport[_port].regs + USB_OTG_IN_ENDPOINT_BASE)
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#define FIFO_BASE(_port, _x) ((volatile uint32_t *) (_dcd_rhport[_port].regs + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
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/*------------------------------------------------------------------*/
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/* MACRO TYPEDEF CONSTANT ENUM
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*------------------------------------------------------------------*/
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@ -90,11 +117,6 @@
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// We disable SOF for now until needed later on
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#define USE_SOF 0
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#define DEVICE_BASE (USB_OTG_DeviceTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE)
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#define OUT_EP_BASE (USB_OTG_OUTEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE)
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#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
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#define FIFO_BASE(_x) ((volatile uint32_t *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
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static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
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static uint8_t _setup_offs; // We store up to 3 setup packets.
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@ -113,9 +135,10 @@ xfer_ctl_t xfer_status[EP_MAX][2];
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// Setup the control endpoint 0.
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static void bus_reset(void) {
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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static void bus_reset(uint8_t rhport)
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{
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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for(uint8_t n = 0; n < EP_MAX; n++) {
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out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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@ -163,9 +186,11 @@ static void bus_reset(void) {
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USB_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
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}
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static void end_of_reset(void) {
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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static void end_of_reset(uint8_t rhport)
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{
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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// On current silicon on the Full Speed core, speed is fixed to Full Speed.
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// However, keep for debugging and in case Low Speed is ever supported.
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uint32_t enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
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@ -191,8 +216,6 @@ static void end_of_reset(void) {
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*------------------------------------------------------------------*/
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void dcd_init (uint8_t rhport)
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{
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(void) rhport;
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// Programming model begins in the last section of the chapter on the USB
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// peripheral in each Reference Manual.
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USB_OTG_FS->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
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@ -210,7 +233,7 @@ void dcd_init (uint8_t rhport)
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// the core to stop working/require reset.
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USB_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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// If USB host misbehaves during status portion of control xfer
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// (non zero-length packet), send STALL back and discard. Full speed.
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@ -226,21 +249,17 @@ void dcd_init (uint8_t rhport)
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void dcd_int_enable (uint8_t rhport)
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{
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(void) rhport;
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NVIC_EnableIRQ(OTG_FS_IRQn);
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NVIC_EnableIRQ(_dcd_rhport[rhport].irqnum);
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}
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void dcd_int_disable (uint8_t rhport)
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{
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(void) rhport;
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NVIC_DisableIRQ(OTG_FS_IRQn);
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NVIC_EnableIRQ(_dcd_rhport[rhport].irqnum);
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}
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void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
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{
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(void) rhport;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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dev->DCFG |= (dev_addr << USB_OTG_DCFG_DAD_Pos) & USB_OTG_DCFG_DAD_Msk;
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// Response with status after changing device address
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@ -254,16 +273,14 @@ void dcd_remote_wakeup(uint8_t rhport)
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void dcd_connect(uint8_t rhport)
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{
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(void) rhport;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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dev->DCTL &= ~USB_OTG_DCTL_SDIS;
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}
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void dcd_disconnect(uint8_t rhport)
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{
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(void) rhport;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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dev->DCTL |= USB_OTG_DCTL_SDIS;
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}
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@ -275,10 +292,9 @@ void dcd_disconnect(uint8_t rhport)
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bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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{
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(void) rhport;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
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uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
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@ -345,10 +361,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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(void) rhport;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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@ -393,10 +408,9 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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// (send STALL versus NAK handshakes back). Refactor into resuable function.
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void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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@ -445,9 +459,8 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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@ -480,8 +493,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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// TODO: Split into "receive on endpoint 0" and "receive generic"; endpoint 0's
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// DOEPTSIZ register is smaller than the others, and so is insufficient for
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// determining how much of an OUT transfer is actually remaining.
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static void receive_packet(xfer_ctl_t * xfer, /* USB_OTG_OUTEndpointTypeDef * out_ep, */ uint16_t xfer_size) {
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usb_fifo_t rx_fifo = FIFO_BASE(0);
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static void receive_packet(uint8_t rhport, xfer_ctl_t * xfer, /* USB_OTG_OUTEndpointTypeDef * out_ep, */ uint16_t xfer_size) {
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usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
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// See above TODO
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// uint16_t remaining = (out_ep->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
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@ -539,8 +552,8 @@ static void receive_packet(xfer_ctl_t * xfer, /* USB_OTG_OUTEndpointTypeDef * ou
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}
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// Write a single data packet to EPIN FIFO
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static void write_fifo_packet(uint8_t fifo_num, uint8_t * src, uint16_t len){
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usb_fifo_t tx_fifo = FIFO_BASE(fifo_num);
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static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len){
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usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num);
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// Pushing full available 32 bit words to fifo
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uint16_t full_words = len >> 2;
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@ -564,8 +577,8 @@ static void write_fifo_packet(uint8_t fifo_num, uint8_t * src, uint16_t len){
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}
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}
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static void read_rx_fifo(USB_OTG_OUTEndpointTypeDef * out_ep) {
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usb_fifo_t rx_fifo = FIFO_BASE(0);
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static void read_rx_fifo(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_ep) {
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usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
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// Pop control word off FIFO (completed xfers will have 2 control words,
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// we only pop one ctl word each interrupt).
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@ -580,7 +593,7 @@ static void read_rx_fifo(USB_OTG_OUTEndpointTypeDef * out_ep) {
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case 0x02: // Out packet recvd
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{
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xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
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receive_packet(xfer, bcnt);
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receive_packet(rhport, xfer, bcnt);
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}
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break;
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case 0x03: // Out packet done (Interrupt)
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@ -605,7 +618,7 @@ static void read_rx_fifo(USB_OTG_OUTEndpointTypeDef * out_ep) {
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}
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}
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static void handle_epout_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
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static void handle_epout_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
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// DAINT for a given EP clears when DOEPINTx is cleared.
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// OEPINT will be cleared when DAINT's out bits are cleared.
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for(uint8_t n = 0; n < EP_MAX; n++) {
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@ -615,7 +628,7 @@ static void handle_epout_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTy
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// SETUP packet Setup Phase done.
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if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
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out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP;
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dcd_event_setup_received(0, (uint8_t*) &_setup_packet[2*_setup_offs], true);
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dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[2*_setup_offs], true);
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_setup_offs = 0;
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}
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@ -631,7 +644,7 @@ static void handle_epout_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTy
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// Transfer complete if short packet or total len is transferred
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if(xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
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xfer->short_packet = false;
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dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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dcd_event_xfer_complete(rhport, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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} else {
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// Schedule another packet to be received.
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out_ep[n].DOEPTSIZ |= (1 << USB_OTG_DOEPTSIZ_PKTCNT_Pos) | \
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@ -643,7 +656,7 @@ static void handle_epout_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTy
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}
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}
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static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) {
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static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) {
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// DAINT for a given EP clears when DIEPINTx is cleared.
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// IEPINT will be cleared when DAINT's out bits are cleared.
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for ( uint8_t n = 0; n < EP_MAX; n++ )
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@ -657,7 +670,7 @@ static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointType
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if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC )
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{
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in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC;
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dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
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dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
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}
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// XFER FIFO empty
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@ -686,7 +699,7 @@ static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointType
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xfer->queued_len = xfer->total_len - remaining_bytes;
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// Push packet to Tx-FIFO
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write_fifo_packet(n, (xfer->buffer + xfer->queued_len), packet_size);
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write_fifo_packet(rhport, n, (xfer->buffer + xfer->queued_len), packet_size);
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}
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// Turn off TXFE if all bytes are written.
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@ -699,20 +712,18 @@ static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointType
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}
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}
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void dcd_int_handler(uint8_t rhport) {
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(void) rhport;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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void dcd_int_handler(uint8_t rhport)
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{
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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uint32_t int_status = USB_OTG_FS->GINTSTS;
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if(int_status & USB_OTG_GINTSTS_USBRST) {
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// USBRST is start of reset.
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBRST;
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bus_reset();
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bus_reset(rhport);
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}
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if(int_status & USB_OTG_GINTSTS_ENUMDNE) {
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@ -720,20 +731,20 @@ void dcd_int_handler(uint8_t rhport) {
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// always expect the same value. This interrupt is considered
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// the end of reset.
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
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end_of_reset();
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dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
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end_of_reset(rhport);
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dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
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}
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if(int_status & USB_OTG_GINTSTS_USBSUSP)
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{
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBSUSP;
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dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
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dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
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}
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if(int_status & USB_OTG_GINTSTS_WKUINT)
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{
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_WKUINT;
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dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
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dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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}
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if(int_status & USB_OTG_GINTSTS_OTGINT)
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@ -743,7 +754,7 @@ void dcd_int_handler(uint8_t rhport) {
|
|||
|
||||
if (otg_int & USB_OTG_GOTGINT_SEDET)
|
||||
{
|
||||
dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
|
||||
}
|
||||
|
||||
USB_OTG_FS->GOTGINT = otg_int;
|
||||
|
|
@ -761,20 +772,20 @@ void dcd_int_handler(uint8_t rhport) {
|
|||
|
||||
// Mask out RXFLVL while reading data from FIFO
|
||||
USB_OTG_FS->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
|
||||
read_rx_fifo(out_ep);
|
||||
read_rx_fifo(rhport, out_ep);
|
||||
USB_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
||||
}
|
||||
|
||||
// OUT endpoint interrupt handling.
|
||||
if(int_status & USB_OTG_GINTSTS_OEPINT) {
|
||||
// OEPINT is read-only
|
||||
handle_epout_ints(dev, out_ep);
|
||||
handle_epout_ints(rhport, dev, out_ep);
|
||||
}
|
||||
|
||||
// IN endpoint interrupt handling.
|
||||
if(int_status & USB_OTG_GINTSTS_IEPINT) {
|
||||
// IEPINT bit read-only
|
||||
handle_epin_ints(dev, in_ep);
|
||||
handle_epin_ints(rhport, dev, in_ep);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue