correct HSE_VALUE in hal_conf
- although it is define in CFLAGS, it is worth to correct to be consistent with other build - extract set_speed()
This commit is contained in:
hathach
parent
9a290febcd
commit
4cec866994
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@ -39,7 +39,7 @@ The stack supports the following MCUs:
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- LPC Series: 11Uxx, 13xx, 175x_6x, 177x_8x, 18xx, 40xx, 43xx, 51Uxx, 54xxx, 55xx
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- iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
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- **Sony:** CXD56
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- **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 (device only)
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- **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
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- **TI:** MSP430
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- **[ValentyUSB](https://github.com/im-tomu/valentyusb)** eptri
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@ -85,6 +85,7 @@ This code base already had supported for a handful of following boards (sorted a
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- [Adafruit Feather STM32F405](https://www.adafruit.com/product/4382)
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- [Micro Python PyBoard v1.1](https://store.micropython.org/product/PYBv1.1)
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- [STLink-V3 Mini](https://www.st.com/en/development-tools/stlink-v3mini.html)
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- [STM32 L035c8 Discovery](https://www.st.com/en/evaluation-tools/32l0538discovery.html)
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- [STM32 F070rb Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f070rb.html)
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- [STM32 F072rb Discovery](https://www.st.com/en/evaluation-tools/32f072bdiscovery.html)
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@ -96,9 +97,13 @@ This code base already had supported for a handful of following boards (sorted a
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- STM32 F411ce Black Pill
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- [STM32 F411ve Discovery](https://www.st.com/en/evaluation-tools/32f411ediscovery.html)
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- [STM32 F412zg Discovery](https://www.st.com/en/evaluation-tools/32f412gdiscovery.html)
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- [STM32 F723e Discovery](https://www.st.com/en/evaluation-tools/32f723ediscovery.html)
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- [STM32 F746zg Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f746zg.html)
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- [STM32 F746g Discovery](https://www.st.com/en/evaluation-tools/32f746gdiscovery.html)
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- [STM32 F767zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f767zi.html)
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- [STM32 F769i Discovery](https://www.st.com/en/evaluation-tools/32f769idiscovery.html)
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- [STM32 H743zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html)
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- [STM32 H743i Evaluation](https://www.st.com/en/evaluation-tools/stm32h743i-eval.html)
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### TI
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@ -87,7 +87,7 @@
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* (when HSE is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
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#define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSE_STARTUP_TIMEOUT)
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@ -87,7 +87,7 @@
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* (when HSE is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
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#define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSE_STARTUP_TIMEOUT)
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@ -87,7 +87,7 @@
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* (when HSE is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
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#define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSE_STARTUP_TIMEOUT)
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@ -285,12 +285,74 @@ static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed)
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}
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}
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static tusb_speed_t get_speed(USB_OTG_DeviceTypeDef* dev)
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static tusb_speed_t get_speed(uint8_t rhport)
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{
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
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return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
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}
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static void set_speed(uint8_t rhport, tusb_speed_t speed)
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{
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uint32_t bitvalue;
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if ( rhport == 1 )
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{
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bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
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}
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else
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{
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bitvalue = DCD_FULL_SPEED;
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}
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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// Clear and set speed bits
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dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
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dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
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}
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#if defined(USB_HS_PHYC) && TUD_OPT_HIGH_SPEED
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static bool USB_HS_PHYCInit(void)
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{
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USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
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// Enable LDO
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usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
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// Wait until LDO ready
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while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
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uint32_t phyc_pll = 0;
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// TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
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switch ( HSE_VALUE )
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{
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case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break;
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case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
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case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break;
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case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break;
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case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break;
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case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header
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default:
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TU_ASSERT(0);
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}
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usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
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// Control the tuning interface of the High Speed PHY
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// Use magic value from ST driver
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usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
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// Enable PLL internal PHY
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usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
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// Original ST code has 2 ms delay for PLL stabilization.
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// Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
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return true;
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}
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#endif
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static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes) {
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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@ -325,46 +387,6 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
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}
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}
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#if defined(USB_HS_PHYC) && TUD_OPT_HIGH_SPEED
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static bool USB_HS_PHYCInit(void)
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{
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USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
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// Enable LDO
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usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
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// Wait until LDO ready
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while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
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uint32_t phyc_pll = 0;
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switch ( HSE_VALUE )
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{
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case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break;
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case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
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case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break;
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case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break;
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case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break;
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case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header
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default:
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TU_ASSERT(0);
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}
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usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
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// Control the tuning interface of the High Speed PHY
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// Use magic value from ST driver
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usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
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// Enable PLL internal PHY
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usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
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// Original ST code has 2 ms delay for PLL stabilization.
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// Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
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return true;
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}
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#endif
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/*------------------------------------------------------------------*/
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/* Controller API
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*------------------------------------------------------------------*/
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@ -431,21 +453,10 @@ void dcd_init (uint8_t rhport)
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// (non zero-length packet), send STALL back and discard.
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dev->DCFG |= USB_OTG_DCFG_NZLSOHSK;
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// Clear speed bits
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dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
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set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
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if ( rhport == 1 )
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{
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dev->DCFG |= ((TUD_OPT_HIGH_SPEED ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS) << USB_OTG_DCFG_DSPD_Pos);
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}
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else
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{
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// full speed = 0x03
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dev->DCFG |= (DCD_FULL_SPEED << USB_OTG_DCFG_DSPD_Pos);
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// Enable internal USB transceiver.
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usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
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}
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// Enable internal USB transceiver.
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if ( rhport == 0 ) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
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usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM |
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USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM |
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@ -511,7 +522,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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TU_ASSERT(epnum < EP_MAX);
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// TODO ISO endpoint can be up to 1024 bytes
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TU_ASSERT(desc_edpt->wMaxPacketSize.size <= (get_speed(dev) == TUSB_SPEED_HIGH ? 512 : 64));
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TU_ASSERT(desc_edpt->wMaxPacketSize.size <= (get_speed(rhport) == TUSB_SPEED_HIGH ? 512 : 64));
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xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
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xfer->max_size = desc_edpt->wMaxPacketSize.size;
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@ -575,9 +586,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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_allocated_fifo_words += fifo_size;
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//TU_LOG2_INT(fifo_size);
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//TU_LOG2_INT(_allocated_fifo_words);
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in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
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(epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
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(desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
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@ -925,7 +933,7 @@ void dcd_int_handler(uint8_t rhport)
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usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
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tusb_speed_t const speed = get_speed(dev);
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tusb_speed_t const speed = get_speed(rhport);
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set_turnaround(usb_otg, speed);
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dcd_event_bus_reset(rhport, speed, true);
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