Commit Graph

29 Commits

Author SHA1 Message Date
hathach acde49ccc9
enable pull-up in dcd_init() instead of usbd 2020-08-01 20:14:58 +07:00
hathach 5af08e2ffc
fix strict prototype 2020-07-29 16:59:07 +07:00
Ha Thach 8dda0a0dd1
Merge pull request #454 from me-no-dev/esp32-s2-fifos
ESP32-S2: Handle the fact that available EP IN FIFOs are less than the number of available EP INs
2020-07-28 15:16:15 +07:00
me-no-dev a1a390a788 Update dcd_esp32s2.c 2020-07-28 10:54:23 +03:00
me-no-dev d493724a7b ESP32-S2: Detect EP IN Xfer Timeout
In some rare ocasions (bad cable, noise, etc.) data transfer might timeout and hang the endpoint, unless the interrupt flag is cleared.
This pull request targets to solve that case.
2020-07-02 13:05:17 +03:00
me-no-dev 6178f8de2f ESP32-S2: Handle the fact that available EP IN FIFOs are less than the number of available EP INs
ESP32-S2 has only 5 available endpoint-in FIFOs (including EP0) but 7 available EP IN numbers. This change decouples the fifo number from the endpoint number, providing FIFO numbers until they reach the limit, at which point it will return false and assert an error that too many endpoints were allocated.
2020-07-01 13:38:59 +03:00
hathach 00fcf829a1 sync synopsis fix for esp32s2 2020-04-26 22:41:04 +07:00
hathach c3fc5f1595 session end interrupt doesn't trigger on esp32 saola board
it is possibly due to the board design without vbus sense. Revisit
later.
2020-04-18 23:42:51 +07:00
hathach 6f9c256ad0
complete remove dcd_set_config(), fix unit test 2020-04-17 13:52:34 +07:00
hathach 50be9d7c3a
mass rename tud/dcd_irq_handler to tud/dcd_init_handler 2020-04-17 12:27:53 +07:00
hathach 63655ac9d7
cleanup for esp32 2020-04-16 20:43:26 +07:00
hathach ae1314f1c7 fix incorrect setup packet
also increase usbd stack in example when debug is enabled
2020-04-11 12:55:45 +07:00
hathach a37a56acd3 remove CONFIG_IDF_TARGET_ESP32S2BETA per review 2020-04-10 23:38:36 +07:00
hathach 8953bc9255 added comment note for beta chip walkaround 2020-04-10 20:25:53 +07:00
hathach c545cfc0bc Correct dedicated FIFO SRAM size to 1024
add note for up to 5 active IN endpoints (including EP0 IN)
2020-04-10 15:42:50 +07:00
hathach 978eec73b3 remove 100us delay at the end of dcd_init() 2020-04-10 15:39:59 +07:00
hathach 30945ab9f3 revert name to dcd_int_handler due to function prototype warning 2020-04-10 15:27:23 +07:00
hathach c0695b4b55 clear USB_RXFLVI_M before read_rx_fifo()
more format clean up
2020-04-10 15:13:12 +07:00
hathach 933e3cdfc7 change indent from 4 -> 2 spaces 2020-04-10 15:01:12 +07:00
hathach cec747776d rename dcd_init_handler to dcd_irq_handler to consistent with other ports 2020-04-10 14:47:02 +07:00
hathach d122d7de88 remove commented code 2020-04-10 14:45:55 +07:00
hathach a40d1e800d try to fix racing condition with setup 2020-04-10 14:04:18 +07:00
hathach 880595433c use macro for easy enable/disable SOF 2020-04-08 15:41:16 +07:00
hathach 7b7a78ab2e disable SOF interrupt since it is not used for now 2020-04-08 15:33:07 +07:00
hathach 06e87b47a2 revert name to dcd_init_handler()
since the function signature is different
2020-04-06 21:28:02 +07:00
hathach 22a9b05834 rename dcd_int_handler to dcd_irq_handler for consistency with other port 2020-04-06 19:49:25 +07:00
hathach 050de0ec33 fix issue and typo with In token when Fifo empty
fix transmit packet endpoint's fifo
2020-04-06 16:32:55 +07:00
hathach 1e7c3cf95e update dcd esp32s2 fifo allocation to match current dcd synopsys 2020-04-03 17:09:38 +07:00
hathach a3e50242b9 add dcd_esp32s2
skip esp32s2_saola for make build since idf use cmake
2020-04-01 17:07:28 +07:00