Correct dedicated FIFO SRAM size to 1024

add note for up to 5 active IN endpoints (including EP0 IN)
This commit is contained in:
hathach 2020-04-10 15:42:50 +07:00
parent 978eec73b3
commit c545cfc0bc
1 changed files with 6 additions and 2 deletions

View File

@ -46,9 +46,13 @@
// We disable SOF for now until needed later on
#define USE_SOF 0
// FIFO size in bytes TODO need confirmation from Espressif
// Max number of bi-directional endpoints including EP0
// Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0
// We should probably prohibit enabling Endpoint IN > 4 (not done yet)
#define EP_MAX USB_OUT_EP_NUM
#define EP_FIFO_SIZE 1280
// FIFO size in bytes
#define EP_FIFO_SIZE 1024
typedef struct {
uint8_t *buffer;