2013-11-01 06:11:26 +01:00
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/**************************************************************************/
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/*!
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@file msc_device.c
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@author hathach (tinyusb.org)
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@section LICENSE
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Software License Agreement (BSD License)
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Copyright (c) 2013, hathach (tinyusb.org)
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holders nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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#include "tusb_option.h"
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2018-04-12 08:23:52 +02:00
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#if (MODE_DEVICE_SUPPORTED && CFG_TUD_MSC)
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2013-11-01 06:11:26 +01:00
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#define _TINY_USB_SOURCE_FILE_
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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2018-03-22 08:15:16 +01:00
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#include "common/tusb_common.h"
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2013-11-01 06:11:26 +01:00
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#include "msc_device.h"
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2018-03-22 08:15:16 +01:00
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#include "device/usbd_pvt.h"
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2013-11-01 06:11:26 +01:00
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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2018-03-22 11:43:13 +01:00
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enum
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{
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MSC_STAGE_CMD = 0,
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MSC_STAGE_DATA,
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MSC_STAGE_STATUS
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};
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2013-11-01 06:11:26 +01:00
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typedef struct {
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2018-03-23 05:53:49 +01:00
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// buffer for scsi's response other than read10 & write10.
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// NOTE should be multiple of 64 to be compatible with lpc11/13u
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uint8_t scsi_data[64];
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2018-04-10 14:44:08 +02:00
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CFG_TUSB_MEM_ALIGN msc_cbw_t cbw;
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2014-03-12 08:28:43 +01:00
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2018-04-12 08:04:48 +02:00
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#if defined (__ICCARM__) && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13UXX)
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2018-03-22 10:46:14 +01:00
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uint8_t padding1[64-sizeof(msc_cbw_t)]; // IAR cannot align struct's member
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2014-03-12 08:28:43 +01:00
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#endif
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2018-04-10 14:44:08 +02:00
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CFG_TUSB_MEM_ALIGN msc_csw_t csw;
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2014-03-12 08:28:43 +01:00
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2014-03-22 16:50:08 +01:00
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uint8_t max_lun;
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2018-03-22 10:46:14 +01:00
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uint8_t interface_num;
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uint8_t ep_in, ep_out;
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2018-03-22 11:43:13 +01:00
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uint8_t stage;
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2018-03-23 05:53:49 +01:00
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uint16_t data_len;
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uint16_t xferred_len; // numbered of bytes transferred so far in the Data Stage
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2013-11-01 06:11:26 +01:00
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}mscd_interface_t;
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2018-04-10 14:44:08 +02:00
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CFG_TUSB_ATTR_USBRAM CFG_TUSB_MEM_ALIGN STATIC_VAR mscd_interface_t mscd_data;
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2013-11-01 06:11:26 +01:00
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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2018-03-23 06:17:47 +01:00
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static bool read10_write10_data_xfer(uint8_t rhport, mscd_interface_t* p_msc);
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2013-11-01 06:11:26 +01:00
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//--------------------------------------------------------------------+
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// USBD-CLASS API
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//--------------------------------------------------------------------+
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2013-11-13 06:40:11 +01:00
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void mscd_init(void)
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{
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2013-12-01 16:34:59 +01:00
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memclr_(&mscd_data, sizeof(mscd_interface_t));
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2013-11-13 06:40:11 +01:00
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}
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2018-03-23 06:17:47 +01:00
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void mscd_close(uint8_t rhport)
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2013-11-13 06:40:11 +01:00
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{
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2013-12-01 16:34:59 +01:00
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memclr_(&mscd_data, sizeof(mscd_interface_t));
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2013-11-13 06:40:11 +01:00
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}
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2018-03-23 06:32:40 +01:00
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tusb_error_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface_desc, uint16_t *p_length)
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2013-11-01 06:11:26 +01:00
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{
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2018-03-11 09:31:46 +01:00
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VERIFY( ( MSC_SUBCLASS_SCSI == p_interface_desc->bInterfaceSubClass &&
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2013-11-01 06:11:26 +01:00
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MSC_PROTOCOL_BOT == p_interface_desc->bInterfaceProtocol ), TUSB_ERROR_MSC_UNSUPPORTED_PROTOCOL );
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mscd_interface_t * p_msc = &mscd_data;
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//------------- Open Data Pipe -------------//
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2018-03-23 06:32:40 +01:00
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tusb_desc_endpoint_t const *p_endpoint = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) p_interface_desc );
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2018-03-22 10:46:14 +01:00
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for(int i=0; i<2; i++)
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2013-11-01 06:11:26 +01:00
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{
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2018-03-11 15:16:51 +01:00
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TU_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint->bDescriptorType &&
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2018-03-22 10:46:14 +01:00
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TUSB_XFER_BULK == p_endpoint->bmAttributes.xfer, TUSB_ERROR_DESCRIPTOR_CORRUPTED);
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2013-11-01 06:11:26 +01:00
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2018-03-28 08:47:58 +02:00
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TU_ASSERT( dcd_edpt_open(rhport, p_endpoint), TUSB_ERROR_DCD_FAILED );
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2018-03-11 09:31:46 +01:00
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2018-03-11 14:20:59 +01:00
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if ( p_endpoint->bEndpointAddress & TUSB_DIR_IN_MASK )
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2018-03-11 09:31:46 +01:00
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{
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2018-03-22 10:46:14 +01:00
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p_msc->ep_in = p_endpoint->bEndpointAddress;
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2018-03-11 09:31:46 +01:00
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}else
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{
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2018-03-22 10:46:14 +01:00
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p_msc->ep_out = p_endpoint->bEndpointAddress;
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2018-03-11 09:31:46 +01:00
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}
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2013-11-01 06:11:26 +01:00
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2018-03-23 06:32:40 +01:00
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p_endpoint = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) p_endpoint );
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2013-11-01 06:11:26 +01:00
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}
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2018-03-22 10:46:14 +01:00
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p_msc->interface_num = p_interface_desc->bInterfaceNumber;
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2013-11-01 06:11:26 +01:00
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2018-03-23 06:32:40 +01:00
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(*p_length) += sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
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2013-11-01 06:11:26 +01:00
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//------------- Queue Endpoint OUT for Command Block Wrapper -------------//
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2018-03-28 08:47:58 +02:00
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TU_ASSERT( dcd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)), TUSB_ERROR_DCD_EDPT_XFER );
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2013-11-01 06:11:26 +01:00
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return TUSB_ERROR_NONE;
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}
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2018-03-23 06:17:47 +01:00
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tusb_error_t mscd_control_request_st(uint8_t rhport, tusb_control_request_t const * p_request)
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2013-11-01 06:11:26 +01:00
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{
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2018-03-21 14:08:57 +01:00
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OSAL_SUBTASK_BEGIN
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2013-11-01 06:11:26 +01:00
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2018-03-21 14:08:57 +01:00
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tusb_error_t err;
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2013-11-01 06:11:26 +01:00
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2018-03-21 14:08:57 +01:00
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TU_ASSERT(p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS, TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT);
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2013-11-01 06:11:26 +01:00
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2018-03-21 14:08:57 +01:00
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mscd_interface_t * p_msc = &mscd_data;
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2013-11-01 06:11:26 +01:00
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2018-03-21 14:08:57 +01:00
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if(MSC_REQUEST_RESET == p_request->bRequest)
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{
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2018-03-28 08:54:28 +02:00
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dcd_control_status(rhport, p_request->bmRequestType_bit.direction);
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2018-03-21 14:08:57 +01:00
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}
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else if (MSC_REQUEST_GET_MAX_LUN == p_request->bRequest)
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{
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// Note: lpc11/13u need xfer data's address to be aligned 64 -> make use of scsi_data instead of using max_lun directly
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p_msc->scsi_data[0] = p_msc->max_lun;
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2018-03-31 09:09:48 +02:00
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usbd_control_xfer_st(rhport, p_request->bmRequestType_bit.direction, p_msc->scsi_data, 1);
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2018-03-21 14:08:57 +01:00
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}else
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{
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2018-03-28 08:54:28 +02:00
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dcd_control_stall(rhport); // stall unsupported request
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2013-11-01 06:11:26 +01:00
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}
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2018-03-21 14:08:57 +01:00
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OSAL_SUBTASK_END
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2013-11-01 06:11:26 +01:00
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}
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2013-12-01 16:34:59 +01:00
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//--------------------------------------------------------------------+
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// MSCD APPLICATION CALLBACK
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//--------------------------------------------------------------------+
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2018-03-23 06:17:47 +01:00
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tusb_error_t mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, uint32_t xferred_bytes)
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2018-03-22 11:43:13 +01:00
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{
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mscd_interface_t* const p_msc = &mscd_data;
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msc_cbw_t* const p_cbw = &p_msc->cbw;
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msc_csw_t* const p_csw = &p_msc->csw;
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2013-11-26 07:15:40 +01:00
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2018-03-22 10:46:14 +01:00
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VERIFY( (ep_addr == p_msc->ep_out) || (ep_addr == p_msc->ep_in), TUSB_ERROR_INVALID_PARA);
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2018-03-06 10:50:50 +01:00
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2018-03-22 11:43:13 +01:00
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switch (p_msc->stage)
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2013-12-01 16:34:59 +01:00
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{
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2018-03-22 11:43:13 +01:00
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//------------- new CBW received -------------//
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case MSC_STAGE_CMD:
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2018-03-22 11:48:10 +01:00
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// Complete IN while waiting for CMD is usually Status of previous SCSI op, ignore it
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if(ep_addr != p_msc->ep_out) return TUSB_ERROR_NONE;
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TU_ASSERT( event == TUSB_EVENT_XFER_COMPLETE &&
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xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE, TUSB_ERROR_INVALID_PARA );
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2018-03-22 11:43:13 +01:00
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p_csw->signature = MSC_CSW_SIGNATURE;
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p_csw->tag = p_cbw->tag;
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p_csw->data_residue = 0;
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// Valid command -> move to Data Stage
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2018-03-23 05:53:49 +01:00
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p_msc->stage = MSC_STAGE_DATA;
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p_msc->data_len = p_cbw->xfer_bytes;
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p_msc->xferred_len = 0;
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2018-03-22 11:43:13 +01:00
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if ( (SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0]) )
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{
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2018-03-23 05:53:49 +01:00
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// Read10 & Write10 data len is same as CBW's xfer bytes
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2018-03-23 06:17:47 +01:00
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read10_write10_data_xfer(rhport, p_msc);
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2018-03-22 11:43:13 +01:00
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}
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else
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{
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2018-03-23 05:53:49 +01:00
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// If not read10 & write10, invoke application callback
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2018-03-22 11:43:13 +01:00
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void const *p_buffer = NULL;
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2013-11-26 07:15:40 +01:00
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2018-03-22 11:43:13 +01:00
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// TODO SCSI data out transfer is not yet supported
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2018-03-28 08:38:17 +02:00
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TU_ASSERT( !(p_cbw->xfer_bytes > 0 && !BIT_TEST_(p_cbw->dir, 7)), TUSB_ERROR_NOT_SUPPORTED_YET);
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2013-11-26 08:17:58 +01:00
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2018-03-23 06:17:47 +01:00
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p_csw->status = tud_msc_scsi_cb(rhport, p_cbw->lun, p_cbw->command, &p_buffer, &p_msc->data_len);
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2013-11-26 07:15:40 +01:00
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2018-03-23 05:53:49 +01:00
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if ( p_cbw->xfer_bytes == 0)
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2018-03-22 11:43:13 +01:00
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{
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2018-03-23 05:53:49 +01:00
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// There is no DATA, move to Status Stage
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p_msc->stage = MSC_STAGE_STATUS;
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}
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else
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{
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// Data Phase (non READ10, WRITE10)
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2018-03-28 09:49:00 +02:00
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TU_ASSERT( p_cbw->xfer_bytes >= p_msc->data_len, TUSB_ERROR_INVALID_PARA );
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TU_ASSERT( sizeof(p_msc->scsi_data) >= p_msc->data_len, TUSB_ERROR_NOT_ENOUGH_MEMORY); // needs to increase size for scsi_data
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2018-03-22 11:43:13 +01:00
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2018-03-23 05:53:49 +01:00
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uint8_t const ep_data = BIT_TEST_(p_cbw->dir, 7) ? p_msc->ep_in : p_msc->ep_out;
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2018-03-22 11:43:13 +01:00
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2018-03-23 05:53:49 +01:00
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if ( p_buffer == NULL || p_msc->data_len == 0 )
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2018-03-22 11:43:13 +01:00
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{
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// application does not provide data to response --> possibly unsupported SCSI command
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2018-03-28 08:47:58 +02:00
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dcd_edpt_stall(rhport, ep_data);
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2018-03-22 11:43:13 +01:00
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p_csw->status = MSC_CSW_STATUS_FAILED;
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2018-03-23 05:53:49 +01:00
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p_msc->stage = MSC_STAGE_STATUS;
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2018-03-22 11:43:13 +01:00
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}else
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{
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2018-03-23 05:53:49 +01:00
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memcpy(p_msc->scsi_data, p_buffer, p_msc->data_len);
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2018-03-28 08:47:58 +02:00
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TU_ASSERT( dcd_edpt_xfer(rhport, ep_data, p_msc->scsi_data, p_msc->data_len), TUSB_ERROR_DCD_EDPT_XFER );
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2018-03-22 11:43:13 +01:00
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}
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}
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}
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break;
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2013-11-26 07:15:40 +01:00
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2018-03-22 11:43:13 +01:00
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case MSC_STAGE_DATA:
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2018-03-23 05:53:49 +01:00
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p_msc->xferred_len += xferred_bytes;
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// Data Stage is complete
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if ( p_msc->xferred_len == p_msc->data_len )
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2013-11-25 10:42:04 +01:00
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{
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2018-03-23 05:53:49 +01:00
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p_msc->stage = MSC_STAGE_STATUS;
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}
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else if ( (SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0]) )
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{
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// Can be executed several times e.g write 8K bytes (several flash write)
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2018-03-23 06:17:47 +01:00
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read10_write10_data_xfer(rhport, p_msc);
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2018-03-23 05:53:49 +01:00
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}else
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|
|
|
{
|
|
|
|
// unlikely error
|
2018-03-28 10:23:33 +02:00
|
|
|
verify_breakpoint();
|
2013-11-25 10:42:04 +01:00
|
|
|
}
|
2018-03-22 11:43:13 +01:00
|
|
|
break;
|
2013-11-01 06:11:26 +01:00
|
|
|
|
2018-03-23 05:53:49 +01:00
|
|
|
case MSC_STAGE_STATUS: break; // is processed immediately
|
2018-03-22 11:43:13 +01:00
|
|
|
default : break;
|
2013-11-01 06:11:26 +01:00
|
|
|
}
|
|
|
|
|
2018-03-22 11:43:13 +01:00
|
|
|
if ( p_msc->stage == MSC_STAGE_STATUS )
|
2013-11-26 07:15:40 +01:00
|
|
|
{
|
2018-03-22 11:43:13 +01:00
|
|
|
// Move to default CMD stage after sending status
|
2018-03-23 05:53:49 +01:00
|
|
|
p_msc->stage = MSC_STAGE_CMD;
|
2018-03-22 11:43:13 +01:00
|
|
|
|
2018-03-28 08:47:58 +02:00
|
|
|
TU_ASSERT( dcd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)) );
|
2013-11-01 06:11:26 +01:00
|
|
|
|
2013-11-26 07:15:40 +01:00
|
|
|
//------------- Queue the next CBW -------------//
|
2018-03-28 08:47:58 +02:00
|
|
|
TU_ASSERT( dcd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) );
|
2013-11-26 07:15:40 +01:00
|
|
|
}
|
2013-11-01 06:11:26 +01:00
|
|
|
|
2013-11-26 07:15:40 +01:00
|
|
|
return TUSB_ERROR_NONE;
|
2013-11-01 06:11:26 +01:00
|
|
|
}
|
|
|
|
|
2014-03-09 09:30:57 +01:00
|
|
|
// return true if data phase is complete, false if not yet complete
|
2018-03-23 06:17:47 +01:00
|
|
|
static bool read10_write10_data_xfer(uint8_t rhport, mscd_interface_t* p_msc)
|
2014-03-09 09:30:57 +01:00
|
|
|
{
|
2018-03-22 11:43:13 +01:00
|
|
|
msc_cbw_t* const p_cbw = &p_msc->cbw;
|
2018-03-22 10:46:14 +01:00
|
|
|
msc_csw_t* const p_csw = &p_msc->csw;
|
2014-03-09 09:30:57 +01:00
|
|
|
|
2018-03-22 11:43:13 +01:00
|
|
|
// read10 & write10 has the same format
|
|
|
|
scsi_read10_t* p_readwrite = (scsi_read10_t*) &p_cbw->command;
|
2014-03-09 09:30:57 +01:00
|
|
|
|
2018-03-23 05:53:49 +01:00
|
|
|
uint8_t const ep_data = BIT_TEST_(p_cbw->dir, 7) ? p_msc->ep_in : p_msc->ep_out;
|
2014-03-09 09:30:57 +01:00
|
|
|
|
2018-03-23 05:53:49 +01:00
|
|
|
uint32_t lba = __be2n(p_readwrite->lba);
|
|
|
|
uint16_t block_count = __be2n_16(p_readwrite->block_count);
|
|
|
|
uint16_t const block_size = p_cbw->xfer_bytes / block_count;
|
|
|
|
|
|
|
|
// Adjust lba and block count according to byte transferred so far
|
|
|
|
lba += (p_msc->xferred_len / block_size);
|
|
|
|
block_count -= (p_msc->xferred_len / block_size);
|
2014-03-09 09:30:57 +01:00
|
|
|
|
2018-03-23 05:53:49 +01:00
|
|
|
void *p_buffer = NULL;
|
2018-03-22 11:43:13 +01:00
|
|
|
uint16_t xfer_block;
|
|
|
|
|
|
|
|
if (SCSI_CMD_READ_10 == p_cbw->command[0])
|
|
|
|
{
|
2018-03-23 06:17:47 +01:00
|
|
|
xfer_block = tud_msc_read10_cb (rhport, p_cbw->lun, &p_buffer, lba, block_count);
|
2018-03-22 11:43:13 +01:00
|
|
|
}else
|
|
|
|
{
|
2018-03-23 06:17:47 +01:00
|
|
|
xfer_block = tud_msc_write10_cb(rhport, p_cbw->lun, &p_buffer, lba, block_count);
|
2018-03-22 11:43:13 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
xfer_block = min16_of(xfer_block, block_count);
|
2014-03-09 09:30:57 +01:00
|
|
|
|
2018-03-22 11:43:13 +01:00
|
|
|
if ( 0 == xfer_block )
|
|
|
|
{
|
|
|
|
// xferred_block is zero will cause pipe is stalled & status in CSW set to failed
|
2014-03-09 09:30:57 +01:00
|
|
|
p_csw->data_residue = p_cbw->xfer_bytes;
|
|
|
|
p_csw->status = MSC_CSW_STATUS_FAILED;
|
|
|
|
|
2018-03-28 08:47:58 +02:00
|
|
|
dcd_edpt_stall(rhport, ep_data);
|
2014-03-09 09:30:57 +01:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}else
|
|
|
|
{
|
2018-03-28 08:47:58 +02:00
|
|
|
TU_ASSERT( dcd_edpt_xfer(rhport, ep_data, p_buffer, xfer_block * block_size) );
|
2014-03-09 09:30:57 +01:00
|
|
|
}
|
2018-03-23 05:53:49 +01:00
|
|
|
|
|
|
|
return true;
|
2014-03-09 09:30:57 +01:00
|
|
|
}
|
|
|
|
|
2013-11-01 06:11:26 +01:00
|
|
|
#endif
|