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espressif_tinyusb
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rename dcd_11u_13u_qhd_t::total_bytes to nbytes to prevent confusion 

introduce scsi_data to mscd_interface_t to make tusbd_msc_scsi_cb buffer's address no longer to be required in USB ram section --> save usb ram for lpc11/13u
This commit is contained in:
hathach 2014-03-22 22:50:08 +07:00
parent 7c5b386130
commit 1cdca167cd
8 changed files with 82 additions and 223 deletions
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106
demos/device/device_os_none/.cproject
View File

@ -1,25 +1,23 @@
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@ -92,25 +90,24 @@
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@ -183,25 +180,24 @@
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@ -278,25 +274,24 @@
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@ -369,25 +364,24 @@
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@ -464,25 +458,24 @@
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@ -559,7 +552,6 @@
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</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
@ -568,8 +560,11 @@
<storageModule moduleId="com.crt.config">
<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
&lt;TargetConfig&gt;&#13;
&lt;Properties property_0="" property_3="NXP" property_4="LPC1347" property_count="5" version="1"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC1347" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC1347&lt;/name&gt;&#13;
&lt;Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC1347" property_count="5" version="60100"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&#13;
&lt;info chip="LPC1347" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
&lt;chip&gt;&#13;
&lt;name&gt;LPC1347&lt;/name&gt;&#13;
&lt;family&gt;LPC13xx (12bit ADC)&lt;/family&gt;&#13;
&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
@ -581,33 +576,34 @@
&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/&gt;&#13;
&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C" id="I2C" location="0x40000000"/&gt;&#13;
&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40004000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART" id="USART" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B0" id="CT16B0" location="0x4000c000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B1" id="CT16B1" location="0x40010000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B0" id="CT32B0" location="0x40014000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B1" id="CT32B1" location="0x40018000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x4001c000"/&gt;&#13;
&lt;peripheralInstance derived_from="PMU" id="PMU" location="0x40038000"/&gt;&#13;
&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x40044000"/&gt;&#13;
&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40048000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x40058000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
&lt;peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x40064000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB" id="USB" location="0x40080000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_ITM" determined="infoFile" id="ITM" location="0xe0000000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
&lt;peripheralInstance derived_from="RITIMER" determined="infoFile" id="RITIMER" location="0x40064000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
&lt;processor&gt;&#13;
&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
&lt;/processor&gt;&#13;
&lt;link href="nxp_lpc13Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;

15
demos/device/src/mscd_app.c
View File

@ -46,8 +46,7 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
TUSB_CFG_ATTR_USBRAM
static scsi_inquiry_data_t mscd_inquiry_data =
static scsi_inquiry_data_t const mscd_inquiry_data =
{
.is_removable = 1,
.version = 2,
@ -57,14 +56,12 @@ static scsi_inquiry_data_t mscd_inquiry_data =
.product_revision = "0.01"
};
TUSB_CFG_ATTR_USBRAM
static scsi_read_capacity10_data_t mscd_read_capacity10_data =
static scsi_read_capacity10_data_t const mscd_read_capacity10_data =
{
.last_lba = ENDIAN_BE(DISK_BLOCK_NUM-1), // read capacity
.block_size = ENDIAN_BE(DISK_BLOCK_SIZE)
};
TUSB_CFG_ATTR_USBRAM
scsi_sense_fixed_data_t mscd_sense_data =
{
.response_code = 0x70,
@ -72,8 +69,7 @@ scsi_sense_fixed_data_t mscd_sense_data =
.additional_sense_len = sizeof(scsi_sense_fixed_data_t) - 8
};
TUSB_CFG_ATTR_USBRAM
static scsi_read_format_capacity_data_t mscd_format_capacity_data =
static scsi_read_format_capacity_data_t const mscd_format_capacity_data =
{
.list_length = 8,
.block_num = ENDIAN_BE(DISK_BLOCK_NUM), // write capacity
@ -81,8 +77,7 @@ static scsi_read_format_capacity_data_t mscd_format_capacity_data =
.block_size_u16 = ENDIAN_BE16(DISK_BLOCK_SIZE)
};
TUSB_CFG_ATTR_USBRAM
static scsi_mode_parameters_t msc_dev_mode_para =
static scsi_mode_parameters_t const msc_dev_mode_para =
{
.mode_data_length = 3,
.medium_type = 0,
@ -97,7 +92,7 @@ static scsi_mode_parameters_t msc_dev_mode_para =
//--------------------------------------------------------------------+
// tinyusb callback (ISR context)
//--------------------------------------------------------------------+
msc_csw_status_t tusbd_msc_scsi_cb (uint8_t coreid, uint8_t lun, uint8_t scsi_cmd[16], void ** pp_buffer, uint16_t* p_length)
msc_csw_status_t tusbd_msc_scsi_cb (uint8_t coreid, uint8_t lun, uint8_t scsi_cmd[16], void const ** pp_buffer, uint16_t* p_length)
{
// read10 & write10 has their own callback and MUST not be handled here
switch (scsi_cmd[0])

4
demos/device/src/tusb_config.h
View File

@ -59,11 +59,11 @@
#define TUSB_CFG_DEVICE_FULLSPEED 1 // TODO refractor, remove
//------------- CLASS -------------//
#define TUSB_CFG_DEVICE_HID_KEYBOARD 0
#define TUSB_CFG_DEVICE_HID_KEYBOARD 1
#define TUSB_CFG_DEVICE_HID_MOUSE 1
#define TUSB_CFG_DEVICE_HID_GENERIC 0 // not supported yet
#define TUSB_CFG_DEVICE_MSC 1
#define TUSB_CFG_DEVICE_CDC 0
#define TUSB_CFG_DEVICE_CDC 1
//--------------------------------------------------------------------+
// COMMON CONFIGURATION

131
tinyusb/class/hid_device.c
View File

@ -321,135 +321,4 @@ tusb_error_t hidd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32
return TUSB_ERROR_NONE;
}
#if defined(CAP_DEVICE_ROMDRIVER)
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
#if TUSB_CFG_DEVICE_HID_KEYBOARD
TUSB_CFG_ATTR_USBRAM uint8_t hidd_keyboard_buffer[1024]; // TODO memory reduce
TUSB_CFG_ATTR_USBRAM hid_keyboard_report_t hid_keyboard_report;
static volatile bool bKeyChanged = false;
#endif
#if TUSB_CFG_DEVICE_HID_MOUSE
TUSB_CFG_ATTR_USBRAM uint8_t hidd_mouse_buffer[1024]; // TODO memory reduce
TUSB_CFG_ATTR_USBRAM hid_mouse_report_t hid_mouse_report;
static volatile bool bMouseChanged = false;
#endif
//--------------------------------------------------------------------+
// APPLICATION API
//--------------------------------------------------------------------+
//--------------------------------------------------------------------+
// IMPLEMENTATION
//--------------------------------------------------------------------+
ErrorCode_t HID_GetReport( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* plength)
{
USB_HID_CTRL_T* pHidCtrl = (USB_HID_CTRL_T*) hHid;
/* ReportID = SetupPacket.wValue.WB.L; */
if (pSetup->wValue.WB.H == HID_REQUEST_REPORT_INPUT)
return (ERR_USBD_STALL); /* Not Supported */
switch (pHidCtrl->protocol)
{
#if TUSB_CFG_DEVICE_HID_KEYBOARD
case HID_PROTOCOL_KEYBOARD:
*pBuffer = (uint8_t*) &hid_keyboard_report;
*plength = sizeof(hid_keyboard_report_t);
if (!bKeyChanged)
{
memset(pBuffer, 0, *plength);
}
bKeyChanged = false;
break;
#endif
#if TUSB_CFG_DEVICE_HID_MOUSE
case HID_PROTOCOL_MOUSE:
*pBuffer = (uint8_t*) &hid_mouse_report;
*plength = sizeof(hid_mouse_report_t);
if (!bMouseChanged)
{
memset(pBuffer, 0, *plength);
}
bMouseChanged = false;
break;
#endif
default:
break;
}
return (LPC_OK);
}
ErrorCode_t HID_SetReport( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length)
{
/* we will reuse standard EP0Buf */
if (length == 0)
return LPC_OK;
/* ReportID = SetupPacket.wValue.WB.L; */
if (pSetup->wValue.WB.H != HID_REQUEST_REPORT_OUTPUT)
return (ERR_USBD_STALL); /* Not Supported */
return (LPC_OK);
}
ErrorCode_t HID_EpIn_Hdlr (USBD_HANDLE_T hUsb, void* data, uint32_t event)
{
if (USB_EVT_IN == event)
{
USB_HID_CTRL_T* pHidCtrl = (USB_HID_CTRL_T*)data;
switch(pHidCtrl->protocol)
{
#if TUSB_CFG_DEVICE_HID_KEYBOARD
case HID_PROTOCOL_KEYBOARD:
if (!bKeyChanged)
{
memset(&hid_keyboard_report, 0, sizeof(hid_keyboard_report_t));
}
ROM_API->hw->WriteEP(hUsb, pHidCtrl->epin_adr, (uint8_t*) &hid_keyboard_report, sizeof(hid_keyboard_report_t));
bKeyChanged = false;
break;
#endif
#if TUSB_CFG_DEVICE_HID_MOUSE
case HID_PROTOCOL_MOUSE:
if (!bMouseChanged)
{
memset(&hid_mouse_report, 0, sizeof(hid_mouse_report_t));
}
ROM_API->hw->WriteEP(hUsb, pHidCtrl->epin_adr, (uint8_t*) &hid_mouse_report, sizeof(hid_mouse_report_t));
bMouseChanged = false;
break;
#endif
default:
break;
}
}
return LPC_OK;
}
ErrorCode_t HID_EpOut_Hdlr (USBD_HANDLE_T hUsb, void* data, uint32_t event)
{
if (USB_EVT_OUT == event)
{
// not used yet
// uint8_t outreport[8];
// USB_HID_CTRL_T* pHidCtrl = (USB_HID_CTRL_T*)data;
// ROM_API->hw->ReadEP(hUsb, pHidCtrl->epout_adr, outreport);
}
return LPC_OK;
}
#endif
#endif

26
tinyusb/class/msc_device.c
View File

@ -51,6 +51,7 @@
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
typedef struct {
uint8_t scsi_data[64]; // buffer for scsi's response other than read10 & write10. NOTE should be multiple of 64 to be compatible with lpc11/13u
ATTR_USB_MIN_ALIGNMENT msc_cmd_block_wrapper_t cbw;
#if defined (__ICCARM__) && (TUSB_CFG_MCU == MCU_LPC11UXX || TUSB_CFG_MCU == MCU_LPC13UXX)
@ -59,12 +60,7 @@ typedef struct {
ATTR_USB_MIN_ALIGNMENT msc_cmd_status_wrapper_t csw;
#if defined (__ICCARM__) && (TUSB_CFG_MCU == MCU_LPC11UXX || TUSB_CFG_MCU == MCU_LPC13UXX)
uint8_t padding2[64-sizeof(msc_cmd_status_wrapper_t)]; // IAR cannot align struct's member
#endif
ATTR_USB_MIN_ALIGNMENT uint8_t max_lun; // can STALL for one LUN
uint8_t max_lun;
uint8_t interface_number;
endpoint_handle_t edpt_in, edpt_out;
}mscd_interface_t;
@ -134,7 +130,8 @@ tusb_error_t mscd_control_request_subtask(uint8_t coreid, tusb_control_request_t
break;
case MSC_REQUEST_GET_MAX_LUN:
dcd_pipe_control_xfer(coreid, TUSB_DIR_DEV_TO_HOST, &p_msc->max_lun, 1, false);
p_msc->scsi_data[0] = p_msc->max_lun; // Note: lpc11/13u need xfer data's address to be aligned 64 -> make use of scsi_data instead of using max_lun directly
dcd_pipe_control_xfer(coreid, TUSB_DIR_DEV_TO_HOST, p_msc->scsi_data, 1, false);
break;
default:
@ -149,7 +146,6 @@ tusb_error_t mscd_control_request_subtask(uint8_t coreid, tusb_control_request_t
//--------------------------------------------------------------------+
tusb_error_t mscd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32_t xferred_bytes)
{
// TODO failed --> STALL pipe, on clear STALL --> queue endpoint OUT
static bool is_waiting_read10_write10 = false; // indicate we are transferring data in READ10, WRITE10 command
mscd_interface_t * const p_msc = &mscd_data;
@ -172,15 +168,20 @@ tusb_error_t mscd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32
if ( (SCSI_CMD_READ_10 != p_cbw->command[0]) && (SCSI_CMD_WRITE_10 != p_cbw->command[0]) )
{
void *p_buffer = NULL;
void const *p_buffer = NULL;
uint16_t actual_length = (uint16_t) p_cbw->xfer_bytes;
// TODO SCSI data out transfer is not yet supported
ASSERT_FALSE( p_cbw->xfer_bytes > 0 && !BIT_TEST_(p_cbw->dir, 7), TUSB_ERROR_NOT_SUPPORTED_YET);
p_csw->status = tusbd_msc_scsi_cb(edpt_hdl.coreid, p_cbw->lun, p_cbw->command, &p_buffer, &actual_length);
//------------- Data Phase (non READ10, WRITE10) -------------//
if ( p_cbw->xfer_bytes )
{
ASSERT( p_cbw->xfer_bytes >= actual_length, TUSB_ERROR_INVALID_PARA );
ASSERT( sizeof(p_msc->scsi_data) >= actual_length, TUSB_ERROR_NOT_ENOUGH_MEMORY); // needs to increase size for scsi_data
endpoint_handle_t const edpt_data = BIT_TEST_(p_cbw->dir, 7) ? p_msc->edpt_in : p_msc->edpt_out;
if ( p_buffer == NULL || actual_length == 0 )
@ -189,7 +190,8 @@ tusb_error_t mscd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32
p_csw->status = MSC_CSW_STATUS_FAILED;
}else
{
ASSERT_STATUS( dcd_pipe_queue_xfer( edpt_data, p_buffer, min16_of(actual_length, (uint16_t) p_cbw->xfer_bytes)) );
memcpy(p_msc->scsi_data, p_buffer, actual_length);
ASSERT_STATUS( dcd_pipe_queue_xfer( edpt_data, p_msc->scsi_data, actual_length ) );
}
}
}
@ -198,10 +200,6 @@ tusb_error_t mscd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32
//------------- Data Phase For READ10 & WRITE10 (can be executed several times) -------------//
if ( (SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0]) )
{
// if (is_waiting_read10_write10)
// { // continue with read10, write10 data transfer, interrupt must come from endpoint IN
// ASSERT( endpointhandle_is_equal(p_msc->edpt_in, edpt_hdl) && event == TUSB_EVENT_XFER_COMPLETE, TUSB_ERROR_INVALID_PARA);
// }
is_waiting_read10_write10 = !read10_write10_data_xfer(p_msc);
}

6
tinyusb/class/msc_device.h
View File

@ -105,8 +105,8 @@ uint16_t tusbd_msc_write10_cb(uint8_t coreid, uint8_t lun, void** pp_buffer, uin
* \param[in] coreid USB Controller ID
* \param[in] lun Targeted Logical Unit
* \param[in] scsi_cmd SCSI command contents, application should examine this command block to know which command host requested
* \param[out] pp_buffer Pointer to buffer which application need to update with the address to transceive data with host
* Must be accessible by USB controller (see \ref TUSB_CFG_ATTR_USBRAM)
* \param[out] pp_buffer Pointer to buffer which application need to update with the address to transfer data with host.
* The buffer address can be anywhere since the stack will copy its contents to a internal USB-accessible buffer.
* \param[in] p_length length
* \retval non-zero Actual number of block that application can receive and must be less than or equal to \a \b block_count.
* \retval zero Indicate error in retrieving data from application. Tinyusb device stack will \b STALL the corresponding
@ -114,7 +114,7 @@ uint16_t tusbd_msc_write10_cb(uint8_t coreid, uint8_t lun, void** pp_buffer, uin
* \note Although this callback is called by tinyusb device task (non-isr context), however as all the classes share
* the same task (to save resource), any delay in this callback will cause delay in reponse on other classes.
*/
msc_csw_status_t tusbd_msc_scsi_cb (uint8_t coreid, uint8_t lun, uint8_t scsi_cmd[16], void ** pp_buffer, uint16_t* p_length);
msc_csw_status_t tusbd_msc_scsi_cb (uint8_t coreid, uint8_t lun, uint8_t scsi_cmd[16], void const ** pp_buffer, uint16_t* p_length);
/** @} */
/** @} */

1
tinyusb/common/tusb_errors.h
View File

@ -96,6 +96,7 @@
ENTRY(TUSB_ERROR_DCD_OPEN_PIPE_FAILED )\
ENTRY(TUSB_ERROR_NOT_SUPPORTED_YET )\
ENTRY(TUSB_ERROR_USBD_DEVICE_NOT_CONFIGURED )\
ENTRY(TUSB_ERROR_NOT_ENOUGH_MEMORY )\
ENTRY(TUSB_ERROR_FAILED )\

16
tinyusb/device/dcd_lpc_11uxx_13uxx.c
View File

@ -92,10 +92,10 @@ enum {
};
// buffer input must be 64 byte alignment
typedef struct {
typedef ATTR_PACKED_STRUCT(struct) {
volatile uint16_t buff_addr_offset ; ///< The address offset is updated by hardware after each successful reception/transmission of a packet. Hardware increments the original value with the integer value when the packet size is divided by 64.
volatile uint16_t total_bytes : 10 ; ///< For OUT endpoints this is the number of bytes that can be received in this buffer. For IN endpoints this is the number of bytes that must be transmitted. HW decrements this value with the packet size every time when a packet is successfully transferred. Note: If a short packet is received on an OUT endpoint, the active bit will be cleared and the NBytes value indicates the remaining buffer space that is not used. Software calculates the received number of bytes by subtracting the remaining NBytes from the programmed value.
volatile uint16_t nbytes : 10 ; ///< For OUT endpoints this is the number of bytes that can be received in this buffer. For IN endpoints this is the number of bytes that must be transmitted. HW decrements this value with the packet size every time when a packet is successfully transferred. Note: If a short packet is received on an OUT endpoint, the active bit will be cleared and the NBytes value indicates the remaining buffer space that is not used. Software calculates the received number of bytes by subtracting the remaining NBytes from the programmed value.
uint16_t is_isochronous : 1 ;
uint16_t feedback_toggle : 1 ; ///< For bulk endpoints and isochronous endpoints this bit is reserved and must be set to zero. For the control endpoint zero this bit is used as the toggle value. When the toggle reset bit is set, the data toggle is updated with the value programmed in this bit. When the endpoint is used as an interrupt endpoint, it can be set to the following values. 0: Interrupt endpoint in ‘toggle mode’ 1: Interrupt endpoint in ‘rate feedback mode’. This means that the data toggle is fixed to zero for all data packets. When the interrupt endpoint is in ‘rate feedback mode’, the TR bit must always be set to zero.
uint16_t toggle_reset : 1 ; ///< When software sets this bit to one, the HW will set the toggle value equal to the value indicated in the “toggle value” (TV) bit. For the control endpoint zero, this is not needed to be used because the hardware resets the endpoint toggle to one for both directions when a setup token is received. For the other endpoints, the toggle can only be reset to zero when the endpoint is reset.
@ -124,7 +124,7 @@ typedef struct {
uint32_t current_ioc; ///< interrupt on complete mask for current TD
uint32_t next_ioc; ///< interrupt on complete mask for next TD
// should start from 128
// must start from 128
ATTR_ALIGNED(64) tusb_control_request_t setup_request;
struct {
@ -224,18 +224,18 @@ static void endpoint_non_control_isr(uint32_t int_status)
// when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
uint16_t const xferred_bytes = dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].total_bytes;
uint16_t const xferred_bytes = dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
dcd_data.current_td[ep_id].xferred_total += xferred_bytes;
// there are still data to transfer.
if ( (arr_qhd[buff_idx].total_bytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
if ( (arr_qhd[buff_idx].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
{ // NOTE although buff_addr_offset has been increased when xfer is completed
// but we still need to increase it one more as we are using double buffering.
queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buff_addr_offset+1, dcd_data.current_td[ep_id].remaining_bytes);
}
// short packet or (no more byte and both buffers are finished)
else if ( (arr_qhd[buff_idx].total_bytes > 0) || !arr_qhd[1-buff_idx].active )
else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active )
{ // current TD (request) is completed
LPC_USB->EPSKIP = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
@ -274,7 +274,7 @@ static void endpoint_control_isr(uint32_t int_status)
uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
// there are still data to transfer.
if ( (dcd_data.qhd[ep_id][0].total_bytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
if ( (dcd_data.qhd[ep_id][0].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
{
queue_xfer_to_buffer(ep_id, 0, dcd_data.qhd[ep_id][0].buff_addr_offset, dcd_data.current_td[ep_id].remaining_bytes);
}else
@ -502,7 +502,7 @@ static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_
dcd_data.current_td[ep_id].remaining_bytes -= queued_bytes;
dcd_data.qhd[ep_id][buff_idx].buff_addr_offset = buff_addr_offset;
dcd_data.qhd[ep_id][buff_idx].total_bytes = queued_bytes;
dcd_data.qhd[ep_id][buff_idx].nbytes = queued_bytes;
dcd_data.qhd[ep_id][buff_idx].active = 1;
}