2013-11-01 06:11:26 +01:00
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/**************************************************************************/
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/*!
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@file msc_device.c
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@author hathach (tinyusb.org)
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@section LICENSE
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Software License Agreement (BSD License)
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Copyright (c) 2013, hathach (tinyusb.org)
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holders nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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#include "tusb_option.h"
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#if (MODE_DEVICE_SUPPORTED && TUSB_CFG_DEVICE_MSC)
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#define _TINY_USB_SOURCE_FILE_
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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2018-03-22 08:15:16 +01:00
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#include "common/tusb_common.h"
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2013-11-01 06:11:26 +01:00
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#include "msc_device.h"
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2018-03-22 08:15:16 +01:00
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#include "device/usbd_pvt.h"
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2013-11-01 06:11:26 +01:00
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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typedef struct {
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2014-03-22 16:50:08 +01:00
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uint8_t scsi_data[64]; // buffer for scsi's response other than read10 & write10. NOTE should be multiple of 64 to be compatible with lpc11/13u
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2018-03-22 10:46:14 +01:00
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ATTR_USB_MIN_ALIGNMENT msc_cbw_t cbw;
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2014-03-12 08:28:43 +01:00
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#if defined (__ICCARM__) && (TUSB_CFG_MCU == MCU_LPC11UXX || TUSB_CFG_MCU == MCU_LPC13UXX)
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2018-03-22 10:46:14 +01:00
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uint8_t padding1[64-sizeof(msc_cbw_t)]; // IAR cannot align struct's member
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2014-03-12 08:28:43 +01:00
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#endif
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2018-03-22 10:46:14 +01:00
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ATTR_USB_MIN_ALIGNMENT msc_csw_t csw;
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2014-03-12 08:28:43 +01:00
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2014-03-22 16:50:08 +01:00
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uint8_t max_lun;
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2018-03-22 10:46:14 +01:00
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uint8_t interface_num;
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uint8_t ep_in, ep_out;
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2013-11-01 06:11:26 +01:00
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}mscd_interface_t;
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2014-03-21 13:23:19 +01:00
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TUSB_CFG_ATTR_USBRAM STATIC_VAR mscd_interface_t mscd_data;
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2013-11-01 06:11:26 +01:00
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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2018-03-11 09:31:46 +01:00
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static bool read10_write10_data_xfer(uint8_t port, mscd_interface_t* p_msc);
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2013-11-01 06:11:26 +01:00
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//--------------------------------------------------------------------+
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// USBD-CLASS API
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//--------------------------------------------------------------------+
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2013-11-13 06:40:11 +01:00
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void mscd_init(void)
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{
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2013-12-01 16:34:59 +01:00
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memclr_(&mscd_data, sizeof(mscd_interface_t));
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2013-11-13 06:40:11 +01:00
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}
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2018-03-09 08:29:23 +01:00
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void mscd_close(uint8_t port)
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2013-11-13 06:40:11 +01:00
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{
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2013-12-01 16:34:59 +01:00
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memclr_(&mscd_data, sizeof(mscd_interface_t));
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2013-11-13 06:40:11 +01:00
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}
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2018-03-09 08:29:23 +01:00
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tusb_error_t mscd_open(uint8_t port, tusb_descriptor_interface_t const * p_interface_desc, uint16_t *p_length)
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2013-11-01 06:11:26 +01:00
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{
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2018-03-11 09:31:46 +01:00
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VERIFY( ( MSC_SUBCLASS_SCSI == p_interface_desc->bInterfaceSubClass &&
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2013-11-01 06:11:26 +01:00
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MSC_PROTOCOL_BOT == p_interface_desc->bInterfaceProtocol ), TUSB_ERROR_MSC_UNSUPPORTED_PROTOCOL );
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mscd_interface_t * p_msc = &mscd_data;
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//------------- Open Data Pipe -------------//
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tusb_descriptor_endpoint_t const *p_endpoint = (tusb_descriptor_endpoint_t const *) descriptor_next( (uint8_t const*) p_interface_desc );
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2018-03-22 10:46:14 +01:00
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for(int i=0; i<2; i++)
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2013-11-01 06:11:26 +01:00
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{
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2018-03-11 15:16:51 +01:00
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TU_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint->bDescriptorType &&
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2018-03-22 10:46:14 +01:00
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TUSB_XFER_BULK == p_endpoint->bmAttributes.xfer, TUSB_ERROR_DESCRIPTOR_CORRUPTED);
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2013-11-01 06:11:26 +01:00
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2018-03-11 09:31:46 +01:00
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TU_ASSERT( tusb_dcd_edpt_open(port, p_endpoint), TUSB_ERROR_DCD_FAILED );
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2018-03-11 14:20:59 +01:00
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if ( p_endpoint->bEndpointAddress & TUSB_DIR_IN_MASK )
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2018-03-11 09:31:46 +01:00
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{
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2018-03-22 10:46:14 +01:00
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p_msc->ep_in = p_endpoint->bEndpointAddress;
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2018-03-11 09:31:46 +01:00
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}else
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{
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2018-03-22 10:46:14 +01:00
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p_msc->ep_out = p_endpoint->bEndpointAddress;
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2018-03-11 09:31:46 +01:00
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}
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2013-11-01 06:11:26 +01:00
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p_endpoint = (tusb_descriptor_endpoint_t const *) descriptor_next( (uint8_t const*) p_endpoint );
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}
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2018-03-22 10:46:14 +01:00
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p_msc->interface_num = p_interface_desc->bInterfaceNumber;
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2013-11-01 06:11:26 +01:00
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(*p_length) += sizeof(tusb_descriptor_interface_t) + 2*sizeof(tusb_descriptor_endpoint_t);
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//------------- Queue Endpoint OUT for Command Block Wrapper -------------//
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2018-03-22 10:46:14 +01:00
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t), true), TUSB_ERROR_DCD_EDPT_XFER );
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2013-11-01 06:11:26 +01:00
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return TUSB_ERROR_NONE;
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}
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2018-03-22 10:28:40 +01:00
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tusb_error_t mscd_control_request_st(uint8_t port, tusb_control_request_t const * p_request)
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2013-11-01 06:11:26 +01:00
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{
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2018-03-21 14:08:57 +01:00
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OSAL_SUBTASK_BEGIN
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2013-11-01 06:11:26 +01:00
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2018-03-21 14:08:57 +01:00
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tusb_error_t err;
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2013-11-01 06:11:26 +01:00
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2018-03-21 14:08:57 +01:00
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TU_ASSERT(p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS, TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT);
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2013-11-01 06:11:26 +01:00
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2018-03-21 14:08:57 +01:00
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mscd_interface_t * p_msc = &mscd_data;
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2013-11-01 06:11:26 +01:00
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2018-03-21 14:08:57 +01:00
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if(MSC_REQUEST_RESET == p_request->bRequest)
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{
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2018-03-22 08:15:16 +01:00
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usbd_control_status(port, p_request->bmRequestType_bit.direction);
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2018-03-21 14:08:57 +01:00
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}
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else if (MSC_REQUEST_GET_MAX_LUN == p_request->bRequest)
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{
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// Note: lpc11/13u need xfer data's address to be aligned 64 -> make use of scsi_data instead of using max_lun directly
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p_msc->scsi_data[0] = p_msc->max_lun;
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2018-03-22 10:28:40 +01:00
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STASK_INVOKE( usbd_control_xfer_st(port, p_request->bmRequestType_bit.direction, p_msc->scsi_data, 1), err);
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2018-03-21 14:08:57 +01:00
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}else
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{
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2018-03-22 08:15:16 +01:00
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usbd_control_stall(port); // stall unsupported request
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2013-11-01 06:11:26 +01:00
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}
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2018-03-21 14:08:57 +01:00
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OSAL_SUBTASK_END
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2013-11-01 06:11:26 +01:00
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}
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2013-12-01 16:34:59 +01:00
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//--------------------------------------------------------------------+
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// MSCD APPLICATION CALLBACK
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//--------------------------------------------------------------------+
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2018-03-22 10:46:14 +01:00
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tusb_error_t mscd_xfer_cb(uint8_t port, uint8_t ep_addr, tusb_event_t event, uint32_t xferred_bytes)
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2013-11-26 07:15:40 +01:00
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{
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static bool is_waiting_read10_write10 = false; // indicate we are transferring data in READ10, WRITE10 command
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2013-11-25 10:42:04 +01:00
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2013-11-26 07:15:40 +01:00
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mscd_interface_t * const p_msc = &mscd_data;
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2018-03-22 10:46:14 +01:00
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msc_cbw_t * const p_cbw = &p_msc->cbw;
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msc_csw_t * const p_csw = &p_msc->csw;
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2013-11-26 07:15:40 +01:00
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2018-03-22 10:46:14 +01:00
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VERIFY( (ep_addr == p_msc->ep_out) || (ep_addr == p_msc->ep_in), TUSB_ERROR_INVALID_PARA);
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2018-03-06 10:50:50 +01:00
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2013-12-01 16:34:59 +01:00
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//------------- new CBW received -------------//
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2014-03-09 09:30:57 +01:00
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if ( !is_waiting_read10_write10 )
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2013-12-01 16:34:59 +01:00
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{
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2018-03-22 10:46:14 +01:00
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// if ( ep_addr == p_msc->edpt_in ) return TUSB_ERROR_NONE; // bulk in interrupt for dcd to clean up
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2013-11-26 07:15:40 +01:00
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2018-03-22 10:46:14 +01:00
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TU_ASSERT( (ep_addr == p_msc->ep_out) &&
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event == TUSB_EVENT_XFER_COMPLETE &&
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xferred_bytes == sizeof(msc_cbw_t) &&
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p_cbw->signature == MSC_CBW_SIGNATURE, TUSB_ERROR_INVALID_PARA );
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2013-11-26 07:15:40 +01:00
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2013-11-26 08:17:58 +01:00
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p_csw->signature = MSC_CSW_SIGNATURE;
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p_csw->tag = p_cbw->tag;
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p_csw->data_residue = 0;
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2013-11-26 07:15:40 +01:00
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if ( (SCSI_CMD_READ_10 != p_cbw->command[0]) && (SCSI_CMD_WRITE_10 != p_cbw->command[0]) )
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{
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2014-03-22 16:50:08 +01:00
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void const *p_buffer = NULL;
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2013-12-01 16:34:59 +01:00
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uint16_t actual_length = (uint16_t) p_cbw->xfer_bytes;
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2013-11-26 07:15:40 +01:00
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2014-03-22 16:50:08 +01:00
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// TODO SCSI data out transfer is not yet supported
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ASSERT_FALSE( p_cbw->xfer_bytes > 0 && !BIT_TEST_(p_cbw->dir, 7), TUSB_ERROR_NOT_SUPPORTED_YET);
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2018-03-11 09:31:46 +01:00
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p_csw->status = tud_msc_scsi_cb(port, p_cbw->lun, p_cbw->command, &p_buffer, &actual_length);
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2013-11-26 07:15:40 +01:00
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2014-03-09 09:30:57 +01:00
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//------------- Data Phase (non READ10, WRITE10) -------------//
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2013-11-26 07:15:40 +01:00
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if ( p_cbw->xfer_bytes )
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2013-11-25 10:42:04 +01:00
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{
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2013-11-26 07:15:40 +01:00
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ASSERT( p_cbw->xfer_bytes >= actual_length, TUSB_ERROR_INVALID_PARA );
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2014-03-22 16:50:08 +01:00
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ASSERT( sizeof(p_msc->scsi_data) >= actual_length, TUSB_ERROR_NOT_ENOUGH_MEMORY); // needs to increase size for scsi_data
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2018-03-22 10:46:14 +01:00
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uint8_t const edpt_data = BIT_TEST_(p_cbw->dir, 7) ? p_msc->ep_in : p_msc->ep_out;
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2013-12-01 16:34:59 +01:00
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2013-11-26 07:15:40 +01:00
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if ( p_buffer == NULL || actual_length == 0 )
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{ // application does not provide data to response --> possibly unsupported SCSI command
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2018-03-11 09:31:46 +01:00
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tusb_dcd_edpt_stall(port, edpt_data);
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2013-11-26 07:15:40 +01:00
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p_csw->status = MSC_CSW_STATUS_FAILED;
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}else
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{
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2014-03-22 16:50:08 +01:00
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memcpy(p_msc->scsi_data, p_buffer, actual_length);
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2018-03-12 16:37:12 +01:00
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TU_ASSERT( tusb_dcd_edpt_queue_xfer(port, edpt_data, p_msc->scsi_data, actual_length), TUSB_ERROR_DCD_EDPT_XFER );
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2013-11-26 07:15:40 +01:00
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}
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2013-11-25 10:42:04 +01:00
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}
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}
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}
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2013-11-01 06:11:26 +01:00
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2013-11-26 07:15:40 +01:00
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//------------- Data Phase For READ10 & WRITE10 (can be executed several times) -------------//
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if ( (SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0]) )
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2013-11-01 06:11:26 +01:00
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{
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2018-03-11 09:31:46 +01:00
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is_waiting_read10_write10 = !read10_write10_data_xfer(port, p_msc);
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2013-11-01 06:11:26 +01:00
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}
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//------------- Status Phase -------------//
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2013-12-01 09:48:49 +01:00
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// Either bulk in & out can be stalled in the data phase, dcd must make sure these queued transfer will be resumed after host clear stall
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2013-11-26 07:15:40 +01:00
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if (!is_waiting_read10_write10)
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{
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2018-03-22 10:46:14 +01:00
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_in , (uint8_t*) p_csw, sizeof(msc_csw_t), false), TUSB_ERROR_DCD_EDPT_XFER );
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2013-11-01 06:11:26 +01:00
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2013-11-26 07:15:40 +01:00
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//------------- Queue the next CBW -------------//
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2018-03-22 10:46:14 +01:00
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) p_cbw, sizeof(msc_cbw_t), true), TUSB_ERROR_DCD_EDPT_XFER );
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2013-11-26 07:15:40 +01:00
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}
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2013-11-01 06:11:26 +01:00
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2013-11-26 07:15:40 +01:00
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return TUSB_ERROR_NONE;
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2013-11-01 06:11:26 +01:00
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}
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2014-03-09 09:30:57 +01:00
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// return true if data phase is complete, false if not yet complete
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2018-03-11 09:31:46 +01:00
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static bool read10_write10_data_xfer(uint8_t port, mscd_interface_t* p_msc)
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2014-03-09 09:30:57 +01:00
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{
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2018-03-22 10:46:14 +01:00
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msc_cbw_t* const p_cbw = &p_msc->cbw;
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msc_csw_t* const p_csw = &p_msc->csw;
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2014-03-09 09:30:57 +01:00
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scsi_read10_t* p_readwrite = (scsi_read10_t*) &p_cbw->command; // read10 & write10 has the same format
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2018-03-22 10:46:14 +01:00
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uint8_t const ep_addr = BIT_TEST_(p_cbw->dir, 7) ? p_msc->ep_in : p_msc->ep_out;
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2014-03-09 09:30:57 +01:00
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uint32_t const lba = __be2n(p_readwrite->lba);
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uint16_t const block_count = __be2n_16(p_readwrite->block_count);
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void *p_buffer = NULL;
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2018-03-11 09:31:46 +01:00
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uint16_t xferred_block = (SCSI_CMD_READ_10 == p_cbw->command[0]) ? tud_msc_read10_cb (port, p_cbw->lun, &p_buffer, lba, block_count) :
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tud_msc_write10_cb(port, p_cbw->lun, &p_buffer, lba, block_count);
|
2014-03-09 09:30:57 +01:00
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xferred_block = min16_of(xferred_block, block_count);
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uint16_t const xferred_byte = xferred_block * (p_cbw->xfer_bytes / block_count);
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|
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if ( 0 == xferred_block )
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|
|
|
{ // xferred_block is zero will cause pipe is stalled & status in CSW set to failed
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|
|
|
p_csw->data_residue = p_cbw->xfer_bytes;
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|
|
|
p_csw->status = MSC_CSW_STATUS_FAILED;
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|
|
|
|
2018-03-22 10:46:14 +01:00
|
|
|
tusb_dcd_edpt_stall(port, ep_addr);
|
2014-03-09 09:30:57 +01:00
|
|
|
|
|
|
|
return true;
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|
|
|
} else if (xferred_block < block_count)
|
|
|
|
{
|
2018-03-22 10:46:14 +01:00
|
|
|
TU_ASSERT( tusb_dcd_edpt_xfer(port, ep_addr, p_buffer, xferred_byte, true), TUSB_ERROR_DCD_EDPT_XFER );
|
2014-03-09 09:30:57 +01:00
|
|
|
|
|
|
|
// adjust lba, block_count, xfer_bytes for the next call
|
|
|
|
p_readwrite->lba = __n2be(lba+xferred_block);
|
|
|
|
p_readwrite->block_count = __n2be_16(block_count - xferred_block);
|
|
|
|
p_cbw->xfer_bytes -= xferred_byte;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}else
|
|
|
|
{
|
|
|
|
p_csw->status = MSC_CSW_STATUS_PASSED;
|
2018-03-22 10:46:14 +01:00
|
|
|
TU_ASSERT( tusb_dcd_edpt_queue_xfer(port, ep_addr, p_buffer, xferred_byte), TUSB_ERROR_DCD_EDPT_XFER );
|
2014-03-09 09:30:57 +01:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-11-01 06:11:26 +01:00
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#endif
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