take changes from busvoodoo branch
parent
922661ffb3
commit
593b0e0e25
12
Rakefile
12
Rakefile
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@ -14,7 +14,7 @@ APPLICATION = "application"
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FIRMWARES = [BOOTLOADER, APPLICATION]
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# which development board is used
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# supported are: SYSTEM_BOARD, MAPLE_MINI, BLUE_PILL, CORE_BOARD
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# supported are: SYSTEM_BOARD, MAPLE_MINI, BLUE_PILL, CORE_BOARD, BUSVOODOO
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BOARD = ENV["BOARD"] || "CORE_BOARD"
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# libopencm3 definitions
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@ -72,7 +72,7 @@ ldflags << "-nostartfiles"
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# only keep used sections
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ldflags << "--gc-sections"
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# add standard libraries (for libc, libm, libnosys, libgcc) because we don't use arm-none-eabi-gcc to locate them
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library_paths = ["/usr/arm-none-eabi/lib/armv7-m/", "/usr/lib/gcc/arm-none-eabi/*/armv7-m/"]
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library_paths = ["/usr/arm-none-eabi/lib/armv7-m/", "/usr/lib/arm-none-eabi/lib/armv7-m/", "/usr/lib/gcc/arm-none-eabi/*/armv7-m/"]
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# add libopencm3
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library_paths += [LIBOPENCM3_LIB]
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# include libraries in flags
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@ -144,7 +144,7 @@ task :doc => ["Doxyfile", "README.md"] do |t|
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end
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desc "compile source into object"
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rule '.o' => ['.c', proc{|f| File.file?(f.ext("h")) ? f.ext("h") : []}, "#{LIBOPENCM3_LIB}/lib#{STM32F1_LIB}.a"] do |t|
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rule '.o' => ['.c', proc{|f| File.file?(f.ext("h")) ? f.ext("h") : []}, proc{|f| dependencies(f).collect{|d| File.file?(d.ext("h")) ? d.ext("h") : []}}, "#{LIBOPENCM3_LIB}/lib#{STM32F1_LIB}.a"] do |t|
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sh "#{CC} #{cflags} #{archflags} -o #{t.name} -c #{t.prerequisites[0]}"
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end
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@ -154,7 +154,7 @@ rule '.d' => ['.c', "#{LIBOPENCM3_LIB}/lib#{STM32F1_LIB}.a"] do |t|
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end
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desc "link binary"
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rule '.elf' => [proc{|f| dependencies(f)}, '.ld', "#{LIBOPENCM3_LIB}/lib#{STM32F1_LIB}.a"] do |t|
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rule '.elf' => ['.o', proc{|f| dependencies(f)}, '.ld', "#{LIBOPENCM3_LIB}/lib#{STM32F1_LIB}.a"] do |t|
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sh "#{LD} #{ldflags} --script #{t.name.ext('ld')} #{t.prerequisites[0..-3].join(' ')} #{ldlibs} -o #{t.name}"
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sh "size #{t.name}"
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end
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@ -198,7 +198,7 @@ BMP_PORT = ENV["BMP_PORT"] || "/dev/ttyACM0"
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desc "flash application using USB DFU"
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task :flash => APPLICATION+".bin" do |t|
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sh "dfu-util -d c440:0d00 -D #{t.source}"
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sh "dfu-util -d 1209:4356 -D #{t.source}"
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end
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desc "flash bootloader using SWD"
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@ -227,7 +227,7 @@ task :debug => APPLICATION+".elf" do |t|
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case SWD_ADAPTER
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when "STLINKV2"
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# for GDB to work with openOCD the firmware needs to be reloaded
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exec("#{GDB} --eval-command='target remote | #{OOCD} --file interface/#{OOCD_INTERFACE}.cfg --file target/#{OOCD_TARGET}.cfg --command \"gdb_port pipe; log_output /dev/null; init\"' --eval-command='monitor reset halt' --eval-command='load' --eval-command='monitor reset init' #{t.source}")
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excec("#{GDB} --eval-command='target remote | #{OOCD} --file interface/#{OOCD_INTERFACE}.cfg --file target/#{OOCD_TARGET}.cfg --command \"gdb_port pipe; log_output /dev/null; init\"' --eval-command='monitor reset halt' --eval-command='load' --eval-command='monitor reset init' #{t.source}")
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when "BMP"
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exec("#{GDB} --eval-command='target extended-remote #{BMP_PORT}' --eval-command='monitor version' --eval-command='monitor swdp_scan' --eval-command='attach 1' #{t.source}")
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end
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@ -39,16 +39,13 @@ void main(void)
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// check if a soft boot has been used
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if (0==(RCC_CSR&0xfc000000)) { // no reset flag present -> this was a soft reset using scb_reset_core() after clearing the flags using RCC_CSR_RMVF, very probably to start the DFU mode
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dfu_force = true;
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} else { // check if
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} else { // check if the force DFU mode input is set
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// disable SWJ pin to use as GPIO
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#if (GPIO(B)==GPIO(DFU_FORCE_PORT)) && (GPIO(4)==GPIO(DFU_FORCE_PIN))
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rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function domain (SWJ)
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gpio_primary_remap(AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST, 0);
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#elif ((GPIO(B)==GPIO(DFU_FORCE_PORT)) && (GPIO(3)==GPIO(DFU_FORCE_PIN))) || ((GPIO(A)==GPIO(DFU_FORCE_PORT)) && (GPIO(15)==GPIO(DFU_FORCE_PIN)))
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rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function domain (SWJ)
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gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON, 0);
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#elif ((GPIO(A)==GPIO(DFU_FORCE_PORT)) && (GPIO(14)==GPIO(DFU_FORCE_PIN))) || ((GPIO(A)==GPIO(DFU_FORCE_PORT)) && (GPIO(13)==GPIO(DFU_FORCE_PIN)))
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rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function domain (SWJ)
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gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF, 0);
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#endif
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rcc_periph_clock_enable(RCC_GPIO(DFU_FORCE_PORT)); // enable clock for GPIO domain
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@ -83,7 +80,11 @@ void main(void)
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rcc_clock_setup_in_hse_8mhz_out_72mhz(); // start main clock
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board_setup(); // setup board to control LED
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#if defined(BUSVOODOO)
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led_red(); // switch red LED to indicate bootloader started
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#else
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led_on(); // indicate bootloader started
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#endif
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usb_dfu_setup(); // setup USB DFU for firmware upload
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usb_dfu_start(); // run DFU mode
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}
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82
global.c
82
global.c
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@ -34,13 +34,14 @@
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#include "global.h" // common methods
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volatile bool button_flag = false;
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volatile uint32_t sleep_duration = 0; /**< sleep duration count down (in SysTick interrupts) */
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volatile bool user_input_available = false;
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static volatile uint8_t user_input_buffer[64] = {0}; /**< ring buffer for received data */
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static volatile uint8_t user_input_i = 0; /**< current position of read received data */
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static volatile uint8_t user_input_used = 0; /**< how much data has been received and not red */
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static volatile uint32_t sleep_duration = 0; /**< sleep duration count down (in SysTick interrupts) */
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char* b2s(uint64_t binary, uint8_t rjust)
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{
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static char string[64+1] = {0}; // the string representation to return
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@ -66,6 +67,10 @@ char* b2s(uint64_t binary, uint8_t rjust)
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/** switch on board LED */
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void led_on(void)
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{
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#if defined(BUSVOODOO)
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timer_disable_counter(TIM1); // disable timer for PWM
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gpio_set_mode(GPIO(LED_PORT), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO(LED_PIN)); // set LED pin to 'output push-pull'
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#endif
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#if defined(LED_ON) && LED_ON
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gpio_set(GPIO(LED_PORT), GPIO(LED_PIN));
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#else
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@ -76,28 +81,77 @@ void led_on(void)
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/** switch off board LED */
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void led_off(void)
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{
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#if defined(BUSVOODOO)
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timer_disable_counter(TIM1); // disable timer for PWM
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gpio_set_mode(GPIO(LED_PORT), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO(LED_PIN)); // set LED pin to 'output push-pull'
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#else
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#if defined(LED_ON) && LED_ON
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gpio_clear(GPIO(LED_PORT), GPIO(LED_PIN));
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#else
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gpio_set(GPIO(LED_PORT), GPIO(LED_PIN));
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#endif
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#endif
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}
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/** toggle board LED */
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void led_toggle(void)
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{
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#if defined(BUSVOODOO)
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timer_disable_counter(TIM1); // disable timer for PWM
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gpio_set_mode(GPIO(LED_PORT), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO(LED_PIN)); // set LED pin to 'output push-pull'
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#endif
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gpio_toggle(GPIO(LED_PORT), GPIO(LED_PIN));
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}
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#if defined(BUSVOODOO)
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void led_blink(double period, double duty)
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{
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if (period<0.0 || period>6.0 || duty<0.0 || duty>1.0) { // input argument out of bounds
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return; // do nothing
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}
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timer_disable_counter(TIM1); // disable timer for PWM before resetting it
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if (0.0==period) { // no blinking
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gpio_set_mode(GPIO(LED_PORT), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO(LED_PIN)); // set LED pin as normal output
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if (duty>0.5) { // LED should be on
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gpio_set(GPIO(LED_PORT), GPIO(LED_PIN)); // switch LED on
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} else { // LED should be off
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gpio_clear(GPIO(LED_PORT), GPIO(LED_PIN)); // switch LED off
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}
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} else {
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gpio_set_mode(GPIO(LED_PORT), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO(LED_PIN)); // set LED pin to alternate function for PWM
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timer_set_counter(TIM1, 0); // reset counter
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timer_set_period(TIM1, 0xffff*(period/6.0)); // set period
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timer_set_oc_value(TIM1, TIM_OC1, 0xffff*(period/6.0)*duty); // PWM duty cycle
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timer_enable_counter(TIM1); // enable timer to start blinking
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}
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}
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void led_blue(void)
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{
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timer_disable_counter(TIM1); // disable timer for PWM
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gpio_set_mode(GPIO(LED_PORT), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO(LED_PIN)); // set LED pin to 'output push-pull'
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gpio_set(GPIO(LED_PORT), GPIO(LED_PIN));
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}
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void led_red(void)
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{
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timer_disable_counter(TIM1); // disable timer for PWM
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gpio_set_mode(GPIO(LED_PORT), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO(LED_PIN)); // set LED pin to 'output push-pull'
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gpio_clear(GPIO(LED_PORT), GPIO(LED_PIN));
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}
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#endif
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void sleep_us(uint32_t duration)
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{
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systick_counter_disable(); // disable SysTick to reconfigure it
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if (!systick_set_frequency(1000000,rcc_ahb_frequency)) { // set SysTick frequency to microseconds
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while (true); // unhandled error
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}
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systick_clear(); // reset SysTick
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systick_set_frequency(1000000,rcc_ahb_frequency); // set SysTick frequency to microseconds
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systick_interrupt_enable(); // enable interrupt to count duration
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sleep_duration = duration; // save sleep duration for count down
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systick_counter_enable(); // start counting
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while (sleep_duration) { // wait for count down to complete
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while (sleep_duration>0) { // wait for count down to complete
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__WFI(); // go to sleep
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}
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}
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@ -105,25 +159,28 @@ void sleep_us(uint32_t duration)
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void sleep_ms(uint32_t duration)
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{
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systick_counter_disable(); // disable SysTick to reconfigure it
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if (!systick_set_frequency(1000,rcc_ahb_frequency)) { // set SysTick frequency to milliseconds
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while (true); // unhandled error
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}
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systick_clear(); // reset SysTick
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systick_set_frequency(1000,rcc_ahb_frequency); // set SysTick frequency to milliseconds
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systick_interrupt_enable(); // enable interrupt to count duration
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sleep_duration = duration; // save sleep duration for count down
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systick_counter_enable(); // start counting
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while (sleep_duration) { // wait for count down to complete
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__WFI(); // go to sleep
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while (sleep_duration>0) { // wait for count down to complete
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// __WFI(); // go to sleep
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}
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}
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/** SysTick interrupt handler */
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void sys_tick_handler(void)
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{
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if (sleep_duration) {
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if (sleep_duration>0) {
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sleep_duration--; // decrement duration
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}
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if (0==sleep_duration) { // sleep complete
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systick_counter_disable(); // stop systick
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systick_interrupt_disable(); // stop interrupting
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sleep_duration = 0; // ensure it still is at 0
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}
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}
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@ -155,7 +212,18 @@ void board_setup(void)
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{
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// setup LED
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rcc_periph_clock_enable(RCC_GPIO(LED_PORT)); // enable clock for LED
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#if defined(BUSVOODOO)
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// LED is connected to TIM1_CH1, allowing to used the PWM output so to display patterns
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rcc_periph_clock_enable(RCC_TIM1); // enable clock for timer domain
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timer_reset(TIM1); // reset timer configuration
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timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1, TIM_CR1_DIR_UP); // configure timer to up counting mode (center aligned for more precise duty cycle control)
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); // use PWM output compare mode
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timer_enable_oc_output(TIM1, TIM_OC1); // enable output compare output
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timer_enable_break_main_output(TIM1); // required to enable timer, even when no dead time is used
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timer_set_prescaler(TIM1, 3296-1); // set prescaler to allow 3/3 seconds PWM output (72MHz/2^16/3296=0.33Hz)
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#else
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gpio_set_mode(GPIO(LED_PORT), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO(LED_PIN)); // set LED pin to 'output push-pull'
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#endif
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led_off(); // switch off LED per default
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// setup button
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73
global.h
73
global.h
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@ -20,7 +20,7 @@
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#pragma once
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/** enable debugging functionalities */
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#define DEBUG true
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#define DEBUG false
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/** get the length of an array */
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#define LENGTH(x) (sizeof(x) / sizeof((x)[0]))
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/** get USART based on USART identifier */
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#define USART(x) CAT2(USART,x)
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/** get RCC for USART based on USART identifier */
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#define USART_RCC(x) CAT2(RCC_USART,x)
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#define RCC_USART(x) CAT2(RCC_USART,x)
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/** get NVIC IRQ for USART based on USART identifier */
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#define USART_IRQ(x) CAT3(NVIC_USART,x,_IRQ)
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/** get interrupt service routine for USART based on USART identifier */
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#define USART_ISR(x) CAT3(usart,x,_isr)
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/** get port for USART based on USART identifier */
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#define USART_PORT(x) CAT2(USART_PORT,x)
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#define USART_PORT1 GPIOA /**< USART 1 is on port A */
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#define USART_PORT2 GPIOA /**< USART 2 is on port A */
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#define USART_PORT3 GPIOB /**< USART 3 is on port B */
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/** get port for USART transmit pin based on USART identifier */
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#define USART_TX_PORT(x) CAT3(GPIO_BANK_USART,x,_TX)
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/** get port for USART receive pin based on USART identifier */
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#define USART_RX_PORT(x) CAT3(GPIO_BANK_USART,x,_RX)
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/** get port for USART RTS pin based on USART identifier */
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#define USART_RTS_PORT(x) CAT3(GPIO_BANK_USART,x,_RTS)
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/** get port for USART CTS pin based on USART identifier */
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#define USART_CTS_PORT(x) CAT3(GPIO_BANK_USART,x,_CTS)
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/** get pin for USART transmit pin based on USART identifier */
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#define USART_TX_PIN(x) CAT3(GPIO_USART,x,_TX)
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/** get pin for USART receive pin based on USART identifier */
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#define USART_RX_PIN(x) CAT3(GPIO_USART,x,_RX)
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/** get pin for USART RTS pin based on USART identifier */
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#define USART_RTS_PIN(x) CAT3(GPIO_USART,x,_RTS)
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/** get pin for USART CTS pin based on USART identifier */
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#define USART_CTS_PIN(x) CAT3(GPIO_USART,x,_CTS)
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/** get RCC for USART port based on USART identifier */
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#define USART_PORT_RCC(x) CAT2(RCC_USART_PORT,x)
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#define RCC_USART_PORT(x) CAT2(RCC_USART_PORT,x)
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#define RCC_USART_PORT1 RCC_GPIOA /**< USART 1 is on port A */
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#define RCC_USART_PORT2 RCC_GPIOA /**< USART 2 is on port A */
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#define RCC_USART_PORT3 RCC_GPIOB /**< USART 3 is on port B */
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/** get transmit pin for USART based on USART identifier */
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#define USART_PIN_TX(x) CAT3(GPIO_USART,x,_TX)
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/** get receive pin for USART based on USART identifier */
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#define USART_PIN_RX(x) CAT3(GPIO_USART,x,_RX)
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/** get port based on ADC12_IN identifier */
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#define ADC12_IN_PORT(x) CAT3(ADC12_IN,x,_PORT)
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#define ADC12_IN0_PORT GPIOA /**< ADC12_IN0 is on PA0 */
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@ -256,26 +263,6 @@
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#define RCC_ADC12_IN15 RCC_GPIOC /**< ADC12_IN15 is on PC5 */
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/** get channel based on ADC12_IN identifier */
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#define ADC_CHANNEL(x) CAT2(ADC_CHANNEL,x)
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/** get I2C based on I2C identifier */
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#define I2C(x) CAT2(I2C,x)
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/** get RCC for I2C based on I2C identifier */
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#define RCC_I2C(x) CAT2(RCC_I2C,x)
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/** get RCC for GPIO port for SCL based on I2C identifier */
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#define RCC_I2C_SCL_PORT(x) CAT3(RCC_I2C,x,_PORT)
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#define RCC_I2C1_PORT RCC_GPIOB /**< RCC for GPIO port for SCL for I2C1 */
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#define RCC_I2C2_PORT RCC_GPIOB /**< RCC for GPIO port for SCL for I2C2 */
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/** get RCC for GPIO port for SCL based on I2C identifier */
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#define RCC_I2C_SDA_PORT(x) CAT3(RCC_I2C,x,_PORT)
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#define RCC_I2C1_SDA_PORT RCC_GPIOB /**< RCC for GPIO port for SDA for I2C1 */
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#define RCC_I2C2_SDA_PORT RCC_GPIOB /**< RCC for GPIO port for SDA for I2C2 */
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/** get I2C port for SCL pin based on I2C identifier */
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#define I2C_SCL_PORT(x) CAT3(GPIO_BANK_I2C,x,_SCL)
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/** get I2C port for SDA pin based on I2C identifier */
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#define I2C_SDA_PORT(x) CAT3(GPIO_BANK_I2C,x,_SDA)
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/** get I2C pin for SCL pin based on I2C identifier */
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#define I2C_SCL_PIN(x) CAT3(GPIO_I2C,x,_SCL)
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/** get I2C port for SDA pin based on I2C identifier */
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#define I2C_SDA_PIN(x) CAT3(GPIO_I2C,x,_SDA)
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/** get SPI based on SPI identifier */
|
||||
#define SPI(x) CAT2(SPI,x)
|
||||
/** get RCC for SPI based on SPI identifier */
|
||||
|
|
@ -382,6 +369,11 @@
|
|||
#define LED_PORT B /**< GPIO port (port B on maple mini) */
|
||||
#define LED_PIN 1 /**< GPIO pin (pin PB1 on maple mini) */
|
||||
#define LED_ON 1 /**< LED is on when pin is high */
|
||||
#elif defined (BUSVOODOO)
|
||||
/* on BusVoodoo LED is on pin PA8 */
|
||||
#define LED_PORT A /**< GPIO port (port A) */
|
||||
#define LED_PIN 8 /**< GPIO pin (pin PA8) */
|
||||
#define LED_ON 1 /**< LED is on when pin is high */
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
|
|
@ -414,6 +406,11 @@
|
|||
#define DFU_FORCE_PORT BUTTON_PORT /**< button port */
|
||||
#define DFU_FORCE_PIN BUTTON_PIN /**< button pin */
|
||||
#define DFU_FORCE_VALUE 0 /**< button floating unpressed, connected to ground pressed to force DFU mode */
|
||||
#elif defined(BUSVOODOO)
|
||||
/* on BusVoodoo DFU input is on PC4 */
|
||||
#define DFU_FORCE_PORT C /**< GPIO port (port C) */
|
||||
#define DFU_FORCE_PIN 4 /**< GPIO pin (pin PC4) */
|
||||
#define DFU_FORCE_VALUE 1 /**< pin floating, set high when shorted with nearby VCC */
|
||||
#else
|
||||
/* use the JNTRST pin as GPIO (this will disable the SWJ function, but we are not using it) */
|
||||
#define DFU_FORCE_PORT B /**< JNTRST port (needs to be remapped to become PB4) */
|
||||
|
|
@ -447,7 +444,17 @@ void led_on(void);
|
|||
void led_off(void);
|
||||
/** toggle board LED */
|
||||
void led_toggle(void);
|
||||
|
||||
#if defined(BUSVOODOO)
|
||||
/** set LED blinking pattern
|
||||
* @param[in] period blue+red pattern duration in seconds (up to 3+3)
|
||||
* @param[in] duty blue LED on duty cycle, before switching to red (0-1)
|
||||
*/
|
||||
void led_blink(double period, double duty);
|
||||
/** switch on blue LED */
|
||||
void led_blue(void);
|
||||
/** switch on red LED */
|
||||
void led_red(void);
|
||||
#endif
|
||||
/** go to sleep for some microseconds
|
||||
* @param[in] duration sleep duration in us
|
||||
*/
|
||||
|
|
|
|||
708
lib/i2c_master.c
708
lib/i2c_master.c
|
|
@ -16,376 +16,618 @@
|
|||
* @file i2c_master.c
|
||||
* @author King Kévin <kingkevin@cuvoodoo.info>
|
||||
* @date 2017-2018
|
||||
* @note peripherals used: I2C @ref i2c_master_i2c, timer @ref i2c_master_timer
|
||||
* @note peripherals used: I2C
|
||||
*/
|
||||
|
||||
/* standard libraries */
|
||||
#include <stdint.h> // standard integer types
|
||||
//#include <stdio.h> // standard I/O facilities
|
||||
#include <stdlib.h> // general utilities
|
||||
|
||||
/* STM32 (including CM3) libraries */
|
||||
#include <libopencm3/stm32/rcc.h> // real-time control clock library
|
||||
#include <libopencm3/stm32/gpio.h> // general purpose input output library
|
||||
#include <libopencm3/stm32/i2c.h> // I2C library
|
||||
#include <libopencm3/stm32/timer.h> // timer utilities
|
||||
|
||||
/* own libraries */
|
||||
#include "global.h" // global utilities
|
||||
#include "i2c_master.h" // I2C header and definitions
|
||||
|
||||
/** @defgroup i2c_master_i2c I2C peripheral used to communicate
|
||||
* @{
|
||||
/** get RCC for I2C based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return RCC address for I2C peripheral
|
||||
*/
|
||||
#define I2C_MASTER_I2C 1 /**< I2C peripheral */
|
||||
/** @} */
|
||||
|
||||
/** @defgroup i2c_master_timer timer peripheral used for timeouts
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MASTER_TIMER 4 /**< timer peripheral */
|
||||
#define I2C_MASTER_TIMEOUT 4 /**< timeout factor (compared to expected time) */
|
||||
/** @} */
|
||||
|
||||
void i2c_master_setup(bool fast)
|
||||
static uint32_t RCC_I2C(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
return RCC_I2C1;
|
||||
break;
|
||||
case I2C2:
|
||||
return RCC_I2C2;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
|
||||
/** get RCC for GPIO port for SCL pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return RCC GPIO address
|
||||
*/
|
||||
static uint32_t RCC_GPIO_PORT_SCL(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
case I2C2:
|
||||
return RCC_GPIOB;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
|
||||
/** get RCC for GPIO port for SDA pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return RCC GPIO address
|
||||
*/
|
||||
static uint32_t RCC_GPIO_PORT_SDA(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
case I2C2:
|
||||
return RCC_GPIOB;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
|
||||
/** get GPIO port for SCL pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return GPIO address
|
||||
*/
|
||||
static uint32_t GPIO_PORT_SCL(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
|
||||
return GPIO_BANK_I2C1_RE_SCL;
|
||||
} else {
|
||||
return GPIO_BANK_I2C1_SCL;
|
||||
}
|
||||
break;
|
||||
case I2C2:
|
||||
return GPIO_BANK_I2C2_SCL;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
|
||||
/** get GPIO port for SDA pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return GPIO address
|
||||
*/
|
||||
static uint32_t GPIO_PORT_SDA(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
|
||||
return GPIO_BANK_I2C1_RE_SDA;
|
||||
} else {
|
||||
return GPIO_BANK_I2C1_SDA;
|
||||
}
|
||||
break;
|
||||
case I2C2:
|
||||
return GPIO_BANK_I2C2_SDA;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
|
||||
/** get GPIO pin for SCL pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return GPIO address
|
||||
*/
|
||||
static uint32_t GPIO_PIN_SCL(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
|
||||
return GPIO_I2C1_RE_SCL;
|
||||
} else {
|
||||
return GPIO_I2C1_SCL;
|
||||
}
|
||||
break;
|
||||
case I2C2:
|
||||
return GPIO_I2C2_SCL;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
|
||||
/** get GPIO pin for SDA pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return GPIO address
|
||||
*/
|
||||
static uint32_t GPIO_PIN_SDA(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
|
||||
return GPIO_I2C1_RE_SDA;
|
||||
} else {
|
||||
return GPIO_I2C1_SDA;
|
||||
}
|
||||
break;
|
||||
case I2C2:
|
||||
return GPIO_I2C2_SDA;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
|
||||
void i2c_master_setup(uint32_t i2c, uint16_t frequency)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// configure I2C peripheral
|
||||
rcc_periph_clock_enable(RCC_I2C_SCL_PORT(I2C_MASTER_I2C)); // enable clock for I2C I/O peripheral
|
||||
gpio_set(I2C_SCL_PORT(I2C_MASTER_I2C), I2C_SCL_PIN(I2C_MASTER_I2C)); // already put signal high to avoid small pulse
|
||||
gpio_set_mode(I2C_SCL_PORT(I2C_MASTER_I2C), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, I2C_SCL_PIN(I2C_MASTER_I2C)); // setup I2C I/O pins
|
||||
rcc_periph_clock_enable(RCC_I2C_SCL_PORT(I2C_MASTER_I2C)); // enable clock for I2C I/O peripheral
|
||||
gpio_set(I2C_SDA_PORT(I2C_MASTER_I2C), I2C_SDA_PIN(I2C_MASTER_I2C)); // already put signal high to avoid small pulse
|
||||
gpio_set_mode(I2C_SDA_PORT(I2C_MASTER_I2C), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, I2C_SDA_PIN(I2C_MASTER_I2C)); // setup I2C I/O pins
|
||||
rcc_periph_clock_enable(RCC_GPIO_PORT_SCL(i2c)); // enable clock for I2C I/O peripheral
|
||||
gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // already put signal high to avoid small pulse
|
||||
gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SCL(i2c)); // setup I2C I/O pins
|
||||
rcc_periph_clock_enable(RCC_GPIO_PORT_SDA(i2c)); // enable clock for I2C I/O peripheral
|
||||
gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // already put signal high to avoid small pulse
|
||||
gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SDA(i2c)); // setup I2C I/O pins
|
||||
rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function
|
||||
rcc_periph_clock_enable(RCC_I2C(I2C_MASTER_I2C)); // enable clock for I2C peripheral
|
||||
i2c_reset(I2C(I2C_MASTER_I2C)); // reset configuration
|
||||
i2c_peripheral_disable(I2C(I2C_MASTER_I2C)); // I2C needs to be disable to be configured
|
||||
i2c_set_clock_frequency(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
|
||||
if (fast) {
|
||||
i2c_set_fast_mode(I2C(I2C_MASTER_I2C));
|
||||
i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/(400000*2)); // set Thigh/Tlow to generate frequency of 400 kHz
|
||||
i2c_set_trise(I2C(I2C_MASTER_I2C), (300/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 300 kHz is 300 ns
|
||||
} else {
|
||||
i2c_set_standard_mode(I2C(I2C_MASTER_I2C)); // the DS1307 has a maximum I2C SCL freq if 100 kHz (corresponding to the standard mode)
|
||||
i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/(100000*2)); // set Thigh/Tlow to generate frequency of 100 kHz
|
||||
i2c_set_trise(I2C(I2C_MASTER_I2C), (1000/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 100 kHz is 1000 ns (~1 MHz)
|
||||
rcc_periph_clock_enable(RCC_I2C(i2c)); // enable clock for I2C peripheral
|
||||
i2c_reset(i2c); // reset peripheral domain
|
||||
i2c_peripheral_disable(i2c); // I2C needs to be disable to be configured
|
||||
I2C_CR1(i2c) |= I2C_CR1_SWRST; // reset peripheral
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // clear peripheral reset
|
||||
if (0==frequency) { // don't allow null frequency
|
||||
frequency = 1;
|
||||
} else if (frequency>400) { // limit frequency to 400 kHz
|
||||
frequency = 400;
|
||||
}
|
||||
i2c_peripheral_enable(I2C(I2C_MASTER_I2C)); // enable I2C after configuration completed
|
||||
|
||||
// configure time for timeouts
|
||||
rcc_periph_clock_enable(RCC_TIM(I2C_MASTER_TIMER)); // enable clock for timer block
|
||||
timer_reset(TIM(I2C_MASTER_TIMER)); // reset timer state
|
||||
timer_set_mode(TIM(I2C_MASTER_TIMER), TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // set timer mode, use undivided timer clock, edge alignment (simple count), and count up
|
||||
timer_one_shot_mode(TIM(I2C_MASTER_TIMER)); // stop counter after update event (we only need to one timeout and reset before next operation)
|
||||
if (fast) {
|
||||
timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/400000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
|
||||
} else {
|
||||
timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/100000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
|
||||
i2c_set_clock_frequency(i2c, rcc_apb1_frequency/1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
|
||||
if (frequency>100) { // use fast mode for frequencies over 100 kHz
|
||||
i2c_set_fast_mode(i2c); // set fast mode (Fm)
|
||||
i2c_set_ccr(i2c, rcc_apb1_frequency/(frequency*1000*2)); // set Thigh/Tlow to generate frequency (fast duty not used)
|
||||
i2c_set_trise(i2c, (300/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for Fm mode (< 400) kHz is 300 ns
|
||||
} else { // use fast mode for frequencies below 100 kHz
|
||||
i2c_set_standard_mode(i2c); // set standard mode (Sm)
|
||||
i2c_set_ccr(i2c, rcc_apb1_frequency/(frequency*1000*2)); // set Thigh/Tlow to generate frequency of 100 kHz
|
||||
i2c_set_trise(i2c, (1000/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for Sm mode (< 100 kHz) is 1000 ns (~1 MHz)
|
||||
}
|
||||
timer_set_period(TIM(I2C_MASTER_TIMER), I2C_MASTER_TIMEOUT*9); // use factor to wait for all 9 bits to be transmitted
|
||||
timer_update_on_overflow(TIM(I2C_MASTER_TIMER)); // only use counter overflow as UEV source (use overflow as timeout)
|
||||
|
||||
// wait one transaction for the signal to be stable (some slave have issues when an I2C transaction immediately follows)
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while ( !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF));
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
i2c_peripheral_enable(i2c); // enable I2C after configuration completed
|
||||
}
|
||||
|
||||
bool i2c_master_start(void)
|
||||
void i2c_master_release(uint32_t i2c)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
i2c_reset(i2c); // reset I2C peripheral configuration
|
||||
i2c_peripheral_disable(i2c); // disable I2C peripheral
|
||||
rcc_periph_clock_disable(RCC_I2C(i2c)); // disable clock for I2C peripheral
|
||||
gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_PIN_SCL(i2c)); // put I2C I/O pins back to floating
|
||||
gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_PIN_SDA(i2c)); // put I2C I/O pins back to floating
|
||||
}
|
||||
|
||||
bool i2c_master_check_signals(uint32_t i2c)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// pull SDA and SDC low to check if there are pull-up resistors
|
||||
uint32_t sda_crl = GPIO_CRL(GPIO_PORT_SDA(i2c)); // backup port configuration
|
||||
uint32_t sda_crh = GPIO_CRH(GPIO_PORT_SDA(i2c)); // backup port configuration
|
||||
uint32_t sda_bsrr = GPIO_BSRR(GPIO_PORT_SDA(i2c)); // backup port configuration
|
||||
uint32_t scl_crl = GPIO_CRL(GPIO_PORT_SCL(i2c)); // backup port configuration
|
||||
uint32_t scl_crh = GPIO_CRH(GPIO_PORT_SCL(i2c)); // backup port configuration
|
||||
uint32_t scl_bsrr = GPIO_BSRR(GPIO_PORT_SCL(i2c)); // backup port configuration
|
||||
gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_PIN_SDA(i2c)); // configure signal as pull down
|
||||
gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_PIN_SCL(i2c)); // configure signal as pull down
|
||||
gpio_clear(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // pull down
|
||||
gpio_clear(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // pull down
|
||||
bool to_return = (0!=gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)) && 0!=gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // check if the signals are still pulled high by external stronger pull-up resistors
|
||||
GPIO_CRL(GPIO_PORT_SDA(i2c)) = sda_crl; // restore port configuration
|
||||
GPIO_CRH(GPIO_PORT_SDA(i2c)) = sda_crh; // restore port configuration
|
||||
GPIO_BSRR(GPIO_PORT_SDA(i2c)) = sda_bsrr; // restore port configuration
|
||||
GPIO_CRL(GPIO_PORT_SCL(i2c)) = scl_crl; // restore port configuration
|
||||
GPIO_CRH(GPIO_PORT_SCL(i2c)) = scl_crh; // restore port configuration
|
||||
GPIO_BSRR(GPIO_PORT_SCL(i2c)) = scl_bsrr; // restore port configuration
|
||||
|
||||
return to_return;
|
||||
}
|
||||
|
||||
void i2c_master_reset(uint32_t i2c)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// follow procedure described in STM32F10xxC/D/E Errata sheet, Section 2.14.7
|
||||
i2c_peripheral_disable(i2c); // disable i2c peripheral
|
||||
gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO_PIN_SCL(i2c)); // put I2C I/O pins to general output
|
||||
gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // set high
|
||||
while (!gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c))); // ensure it is high
|
||||
gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO_PIN_SDA(i2c)); // put I2C I/O pins to general output
|
||||
gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // set high
|
||||
while (!gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // ensure it is high
|
||||
gpio_clear(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // set low (try first transition)
|
||||
while (gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // ensure it is low
|
||||
gpio_clear(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // set low (try first transition)
|
||||
while (gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c))); // ensure it is low
|
||||
gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // set high (try second transition)
|
||||
while (!gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c))); // ensure it is high
|
||||
gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // set high (try second transition)
|
||||
while (!gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // ensure it is high
|
||||
gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SCL(i2c)); // set I2C I/O pins back
|
||||
gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SDA(i2c)); // set I2C I/O pins back
|
||||
I2C_CR1(i2c) |= I2C_CR1_SWRST; // reset device
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // reset device
|
||||
i2c_peripheral_enable(i2c); // re-enable device
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_start(uint32_t i2c)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// send (re-)start condition
|
||||
i2c_send_start(I2C(I2C_MASTER_I2C)); // send start condition to start transaction
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
return false;
|
||||
if (I2C_CR1(i2c) & (I2C_CR1_START|I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
|
||||
return I2C_MASTER_RC_START_STOP_IN_PROGESS;
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // verify if in master mode
|
||||
return false;
|
||||
i2c_send_start(i2c); // send start condition to start transaction
|
||||
while ((I2C_CR1(i2c) & I2C_CR1_START) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until start condition has been accepted and cleared
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
while (!(I2C_SR1(i2c) & I2C_SR1_SB) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until start condition is transmitted
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // verify if in master mode
|
||||
return I2C_MASTER_RC_NOT_MASTER;
|
||||
}
|
||||
|
||||
return true;
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
|
||||
bool i2c_master_select_slave(uint8_t slave, bool write)
|
||||
enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write)
|
||||
{
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
if (!i2c_master_start()) { // send start condition
|
||||
return false; // could not send start condition
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
|
||||
if (!(I2C_SR1(i2c) & I2C_SR1_SB)) { // start condition has not been sent
|
||||
rc = i2c_master_start(i2c); // send start condition
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // I2C device is already not master mode
|
||||
return false;
|
||||
}
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not in master mode
|
||||
return I2C_MASTER_RC_NOT_MASTER;
|
||||
}
|
||||
|
||||
// select slave
|
||||
i2c_send_7bit_address(I2C(I2C_MASTER_I2C), slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred (no ACK received)
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
return false;
|
||||
if (!address_10bit) { // 7-bit address
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
i2c_send_7bit_address(i2c, slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
|
||||
while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until address is transmitted
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
|
||||
return I2C_MASTER_RC_NAK;
|
||||
}
|
||||
} else { // 10-bit address
|
||||
// send first part of address
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
I2C_DR(i2c) = 11110000 | (((slave>>8)&0x3)<<1); // send first header (11110xx0, where xx are 2 MSb of slave address)
|
||||
while (!(I2C_SR1(i2c) & (I2C_SR1_ADD10|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until first part of address is transmitted
|
||||
if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
|
||||
return I2C_MASTER_RC_NAK;
|
||||
}
|
||||
// send second part of address
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
I2C_DR(i2c) = (slave&0xff); // send remaining of address
|
||||
while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
|
||||
return I2C_MASTER_RC_NAK;
|
||||
}
|
||||
// go into receive mode if necessary
|
||||
if (!write) {
|
||||
rc = i2c_master_start(i2c); // send start condition
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
return rc;
|
||||
}
|
||||
// send first part of address with receive flag
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
I2C_DR(i2c) = 11110001 | (((slave>>8)&0x3)<<1); // send header (11110xx1, where xx are 2 MSb of slave address)
|
||||
while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
|
||||
return I2C_MASTER_RC_NAK;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (write) {
|
||||
if (!((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
|
||||
return false;
|
||||
if (!((I2C_SR2(i2c) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
|
||||
return I2C_MASTER_RC_NOT_TRANSMIT;
|
||||
}
|
||||
} else {
|
||||
if ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA)) { // verify we are in read mode (and read SR2 to clear ADDR)
|
||||
return false;
|
||||
if ((I2C_SR2(i2c) & I2C_SR2_TRA)) { // verify we are in read mode (and read SR2 to clear ADDR)
|
||||
return I2C_MASTER_RC_NOT_RECEIVE;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
|
||||
bool i2c_master_read(uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (data==NULL || data_size==0) { // no data to read
|
||||
return true;
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
return false; // address has probably also not been sent
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // I2C device not master mode
|
||||
return false;
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master
|
||||
return I2C_MASTER_RC_NOT_MASTER;
|
||||
}
|
||||
if ((I2C_SR2(i2c) & I2C_SR2_TRA)) { // I2C device not in receiver mode
|
||||
return I2C_MASTER_RC_NOT_RECEIVE;
|
||||
}
|
||||
if (I2C_SR1(i2c) & I2C_SR1_AF) { // check if the previous transaction went well
|
||||
return I2C_MASTER_RC_NOT_READY;
|
||||
}
|
||||
|
||||
// read data
|
||||
for (size_t i=0; i<data_size; i++) { // read bytes
|
||||
if (i==data_size-1) { // prepare to sent NACK for last byte
|
||||
i2c_disable_ack(I2C(I2C_MASTER_I2C)); // NACK received to stop slave transmission
|
||||
i2c_send_stop(I2C(I2C_MASTER_I2C)); // send STOP after receiving byte
|
||||
i2c_disable_ack(i2c); // NACK received to stop slave transmission
|
||||
} else {
|
||||
i2c_enable_ack(I2C(I2C_MASTER_I2C)); // ACK received byte to continue slave transmission
|
||||
i2c_enable_ack(i2c); // ACK received byte to continue slave transmission
|
||||
}
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_RxNE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been received
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
return false;
|
||||
while (!(I2C_SR1(i2c) & I2C_SR1_RxNE) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until byte has been received
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
data[i] = i2c_get_data(I2C(I2C_MASTER_I2C)); // read received byte
|
||||
data[i] = i2c_get_data(i2c); // read received byte
|
||||
}
|
||||
|
||||
return true;
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
|
||||
bool i2c_master_write(const uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (data==NULL || data_size==0) { // no data to write
|
||||
return true;
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
return false; // address has probably also not been sent
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // I2C device is not master mode
|
||||
return false;
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master
|
||||
return I2C_MASTER_RC_NOT_MASTER;
|
||||
}
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_TRA)) { // I2C device not in transmitter mode
|
||||
return I2C_MASTER_RC_NOT_TRANSMIT;
|
||||
}
|
||||
if (I2C_SR1(i2c) & I2C_SR1_AF) { // check if the previous transaction went well
|
||||
return I2C_MASTER_RC_NOT_READY;
|
||||
}
|
||||
|
||||
// write data
|
||||
for (size_t i=0; i<data_size; i++) { // write bytes
|
||||
i2c_send_data(I2C(I2C_MASTER_I2C), data[i]); // send byte to be written in memory
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred (no ACK received)
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
return false;
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
i2c_send_data(i2c, data[i]); // send byte to be written in memory
|
||||
while (!(I2C_SR1(i2c) & (I2C_SR1_TxE|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until byte has been transmitted
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
if (I2C_SR1(i2c) & I2C_SR1_AF) { // data has not been acknowledged
|
||||
return I2C_MASTER_RC_NAK;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
|
||||
void i2c_master_stop(void)
|
||||
enum i2c_master_rc i2c_master_stop(uint32_t i2c)
|
||||
{
|
||||
// sanity check
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY)) { // release is not busy
|
||||
return; // bus has probably already been released
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // release is not busy
|
||||
return I2C_MASTER_RC_NONE; // bus has probably already been released
|
||||
}
|
||||
// send stop condition
|
||||
i2c_send_stop(I2C(I2C_MASTER_I2C)); // send stop to release bus
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until bus released (non master mode)
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
if (I2C_CR1(i2c) & (I2C_CR1_START|I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
|
||||
return I2C_MASTER_RC_START_STOP_IN_PROGESS;
|
||||
}
|
||||
|
||||
i2c_send_stop(i2c); // send stop to release bus
|
||||
while ((I2C_CR1(i2c) & I2C_CR1_STOP) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until stop condition is accepted and cleared
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
while ((I2C_SR2(i2c) & I2C_SR2_MSL) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until bus released (non master mode)
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
|
||||
bool i2c_master_slave_read(uint8_t slave, uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size)
|
||||
{
|
||||
// sanity check
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
return false;
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
|
||||
// send start condition
|
||||
if (!i2c_master_start()) {
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
|
||||
rc = i2c_master_start(i2c); // send (re-)start condition
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// read data
|
||||
if (NULL!=data && data_size>0) {
|
||||
// read data
|
||||
if (!i2c_master_read(data, data_size)) {
|
||||
if (NULL!=data && data_size>0) { // only read data if needed
|
||||
rc = i2c_master_read(i2c, data, data_size);
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
rc = I2C_MASTER_RC_NONE; // all went well
|
||||
error:
|
||||
i2c_master_stop(); // sent stop condition
|
||||
return success;
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return rc;
|
||||
}
|
||||
|
||||
bool i2c_master_slave_write(uint8_t slave, const uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
// sanity check
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
return false;
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
|
||||
// send start condition
|
||||
if (!i2c_master_start()) {
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
|
||||
rc = i2c_master_start(i2c); // send (re-)start condition
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// write data
|
||||
if (NULL!=data && data_size>0) {
|
||||
if (!i2c_master_write(data, data_size)) {
|
||||
if (NULL!=data && data_size>0) { // write data only is some is available
|
||||
rc = i2c_master_write(i2c, data, data_size); // write data
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
rc = I2C_MASTER_RC_NONE; // all went well
|
||||
error:
|
||||
i2c_master_stop(); // sent stop condition
|
||||
return success;
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return rc;
|
||||
}
|
||||
|
||||
bool i2c_master_address_read(uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
|
||||
{
|
||||
// sanity check
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
return false;
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
|
||||
rc = i2c_master_start(i2c); // send (re-)start condition
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
// write address
|
||||
if (NULL!=address && address_size>0) {
|
||||
// send start condition
|
||||
if (!i2c_master_start()) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// send address
|
||||
if (!i2c_master_write(address, address_size)) {
|
||||
rc = i2c_master_write(i2c, address, address_size); // send memory address
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
// read data
|
||||
if (NULL!=data && data_size>0) {
|
||||
// send re-start condition
|
||||
if (!i2c_master_start()) {
|
||||
rc = i2c_master_start(i2c); // send re-start condition
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to read
|
||||
if (!i2c_master_select_slave(slave, false)) {
|
||||
goto error;
|
||||
}
|
||||
// read data
|
||||
if (!i2c_master_read(data, data_size)) {
|
||||
rc = i2c_master_read(i2c, data, data_size); // read memory
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
rc = I2C_MASTER_RC_NONE; // all went well
|
||||
error:
|
||||
i2c_master_stop(); // sent stop condition
|
||||
return success;
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return rc;
|
||||
}
|
||||
|
||||
bool i2c_master_address_write(uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
// sanity check
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
return false;
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
|
||||
rc = i2c_master_start(i2c); // send (re-)start condition
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
// send start condition
|
||||
if (!i2c_master_start()) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// write address
|
||||
if (NULL!=address && address_size>0) {
|
||||
// send address
|
||||
if (!i2c_master_write(address, address_size)) {
|
||||
rc = i2c_master_write(i2c, address, address_size); // send memory address
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
// write data
|
||||
// read data
|
||||
if (NULL!=data && data_size>0) {
|
||||
if (!i2c_master_write(data, data_size)) {
|
||||
rc = i2c_master_write(i2c, data, data_size); // write memory
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
rc = I2C_MASTER_RC_NONE; // all went well
|
||||
error:
|
||||
i2c_master_stop(); // sent stop condition
|
||||
return success;
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return rc;
|
||||
}
|
||||
|
|
|
|||
108
lib/i2c_master.h
108
lib/i2c_master.h
|
|
@ -16,69 +16,117 @@
|
|||
* @file i2c_master.h
|
||||
* @author King Kévin <kingkevin@cuvoodoo.info>
|
||||
* @date 2017-2018
|
||||
* @note peripherals used: I2C @ref i2c_master_i2c, timer @ref i2c_master_timer
|
||||
* @warning only 7-byte I2C slave addresses are supported
|
||||
* @note peripherals used: I2C
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
/** I2C return codes */
|
||||
enum i2c_master_rc {
|
||||
I2C_MASTER_RC_NONE = 0, /**< no error */
|
||||
I2C_MASTER_RC_START_STOP_IN_PROGESS, /**< a start or stop condition is already in progress */
|
||||
I2C_MASTER_RC_NOT_MASTER, /**< not in master mode */
|
||||
I2C_MASTER_RC_NOT_TRANSMIT, /**< not in transmit mode */
|
||||
I2C_MASTER_RC_NOT_RECEIVE, /**< not in receive mode */
|
||||
I2C_MASTER_RC_NOT_READY, /**< slave is not read (previous operations has been nacked) */
|
||||
I2C_MASTER_RC_NAK, /**< not acknowledge received */
|
||||
I2C_MASTER_RC_BUS_ERROR, /**< an error on the I2C bus occurred */
|
||||
};
|
||||
|
||||
/** setup I2C peripheral
|
||||
* @param[in] fast use standard (100 kHz) or fast (400 kHz) mode
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] frequency frequency to use in kHz (1-400)
|
||||
* @note Standard mode (Sm) is used for frequencies up to 100 kHz, and Fast mode (Fm) is used for frequencies up to 400 kHz
|
||||
*/
|
||||
void i2c_master_setup(bool fast);
|
||||
void i2c_master_setup(uint32_t i2c, uint16_t frequency);
|
||||
/** release I2C peripheral
|
||||
* @param[in] i2c I2C base address
|
||||
*/
|
||||
void i2c_master_release(uint32_t i2c);
|
||||
/** reset I2C peripheral, fixing any locked state
|
||||
* @warning the I2C peripheral needs to be re-setup
|
||||
* @note to be used after failed start or stop, and bus error
|
||||
* @param[in] i2c I2C base address
|
||||
*/
|
||||
void i2c_master_reset(uint32_t i2c);
|
||||
/** check if SDA and SCL signals are high
|
||||
* @param[in] i2c I2C base address
|
||||
* @return SDA and SCL signals are high
|
||||
*/
|
||||
bool i2c_master_check_signals(uint32_t i2c);
|
||||
/** send start condition
|
||||
* @return if start condition was sent successfully (true) or error occurred (false)
|
||||
* @param[in] i2c I2C base address
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_start(void);
|
||||
/** select slave device
|
||||
enum i2c_master_rc i2c_master_start(uint32_t i2c);
|
||||
/** select I2C slave device
|
||||
* @warning a start condition should be sent before this operation
|
||||
* @param[in] slave 7-bit I2C address of slave device to select
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] write this transaction will be followed by a read (false) or write (true) operation
|
||||
* @return if slave was selected successfully (true) or error occurred (false)
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_select_slave(uint8_t slave, bool write);
|
||||
/** read data
|
||||
enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write);
|
||||
/** read data over I2C
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_read(uint8_t* data, size_t data_size);
|
||||
/** write data
|
||||
enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size);
|
||||
/** write data over I2C
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_write(const uint8_t* data, size_t data_size);
|
||||
/** sent stop condition */
|
||||
void i2c_master_stop(void);
|
||||
/** read from date from an I2C slave
|
||||
* @param[in] slave 7-bit I2C salve device address to read from
|
||||
enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size);
|
||||
/** sent stop condition
|
||||
* @param[in] i2c I2C base address
|
||||
* @return I2C return code
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_stop(uint32_t i2c);
|
||||
/** read data from slave device
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return if read succeeded
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_slave_read(uint8_t slave, uint8_t* data, size_t data_size);
|
||||
/** write data to an I2C slave
|
||||
* @param[in] slave 7-bit I2C salve device address to write to
|
||||
enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size);
|
||||
/** write data to slave device
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return if write succeeded
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_slave_write(uint8_t slave, const uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size);
|
||||
/** read data at specific address from an I2C memory slave
|
||||
* @param[in] slave 7-bit I2C salve device address to read from
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] address memory address of slave to read from
|
||||
* @param[in] address_size address size in bytes
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return if read succeeded
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_address_read(uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
/** write data at specific address on an I2C memory slave
|
||||
* @param[in] slave 7-bit I2C salve device address to write to
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] address memory address of slave to write to
|
||||
* @param[in] address_size address size in bytes
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return if write succeeded
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_address_write(uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
|
||||
|
|
|
|||