add SN74LVC1G02 NOR gate
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name: SN74LVC1G02
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variations: DBV, DCK, DRL, DRY, DSF, YZP
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# DPW package (X2SON) is not supported by QEDA (not square pads)
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description: single 2-input positive-NOR gate
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datasheet: https://www.ti.com/product/SN74LVC1G02
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pinout@5P: &5P
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Y: 4
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A: 1
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B: 2
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GND: 3
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VCC: 5
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pinout@DBV: *5P
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pinout@DCK: *5P
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pinout@DRL: *5P
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pinout@6P: &6P
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Y: 4
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A: 1
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B: 2
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GND: 3
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VCC: 6
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NC: 5
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pinout@DRY: *6P
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pinout@DSF: *6P
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pinout@YZP: *6P
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properties:
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power: VCC
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ground: GND
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input: A, B
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output: Y
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nc: NS
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schematic:
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symbol: ic
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left: A, B
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right: Y
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top: VCC
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bottom: GND
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housing@DBV: # SOT-23
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suffix: DBV
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outline: JEDEC MO-178 AA
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housing@DCK: # SC70
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suffix: DCK
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outline: JEDEC MO-203 AA
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housing@DRL: # SOT
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suffix: DRL
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pattern: SOT23
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leadCount: 5
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pitch: 0.5
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bodyWidth: 1.1-1.3
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bodyLength: 1.5-1.7
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height: 0.5-0.6
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leadWidth: 0.15-0.25
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leadLength: 0.2-0.4
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leadHeight: 0.00-0.05
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leadSpan: 1.5-1.7
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housing@DRY: # SON
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suffix: DRY
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pattern: QFN
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pitch: 0.5
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bodyLength: 1.4-1.5
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bodyWidth: 0.95-1.05
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height: 0.51-0.61
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pullBack: 0.1
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rowCount: 3
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columnCount: 2
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leadLength: 0.25-0.35
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leadWidth: 0.15-0.25
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housing@DSF: # SON
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suffix: DSF
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pattern: QFN
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pitch: 0.35
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bodyLength: 0.95-1.05
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bodyWidth: 0.95-1.05
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height: 0.34-0.40
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pullBack: 0.0
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rowCount: 3
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columnCount: 2
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leadLength: 0.35-0.45
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leadWidth: 0.14-0.20
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housing@YZP: # BGA
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suffix: YZP
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pattern: BGA
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leadCount: 6 # actually 5, but I'm not sure QEDA handles it well
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pitch: 0.5
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bodyWidth: 0.858-0.918 # E
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bodyLength: 1.358-1.418 # D
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height: 0.5
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leadDiameter: 0.21-0.25
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rowCount: 3
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columnCount: 2
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