diff --git a/ic/nor-gate_ti_sn74lvc1g02.yaml b/ic/nor-gate_ti_sn74lvc1g02.yaml
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+name: SN74LVC1G02
+variations: DBV, DCK, DRL, DRY, DSF, YZP
+# DPW package (X2SON) is not supported by QEDA (not square pads)
+description: single 2-input positive-NOR gate
+datasheet: https://www.ti.com/product/SN74LVC1G02
+
+pinout@5P: &5P
+  Y: 4
+  A: 1
+  B: 2
+  GND: 3
+  VCC: 5
+
+pinout@DBV: *5P
+
+pinout@DCK: *5P
+
+pinout@DRL: *5P
+
+pinout@6P: &6P
+  Y: 4
+  A: 1
+  B: 2
+  GND: 3
+  VCC: 6
+  NC: 5
+
+pinout@DRY: *6P
+
+pinout@DSF: *6P
+
+pinout@YZP: *6P
+
+properties:
+  power: VCC
+  ground: GND
+  input: A, B
+  output: Y
+  nc: NS
+
+schematic:
+  symbol: ic
+  left: A, B
+  right: Y
+  top: VCC
+  bottom: GND
+
+housing@DBV: # SOT-23
+  suffix: DBV
+  outline: JEDEC MO-178 AA
+
+housing@DCK: # SC70
+  suffix: DCK
+  outline: JEDEC MO-203 AA
+
+housing@DRL: # SOT
+  suffix: DRL
+  pattern: SOT23
+  leadCount: 5
+  pitch: 0.5
+  bodyWidth: 1.1-1.3
+  bodyLength: 1.5-1.7
+  height: 0.5-0.6
+  leadWidth: 0.15-0.25
+  leadLength: 0.2-0.4
+  leadHeight: 0.00-0.05
+  leadSpan: 1.5-1.7
+
+housing@DRY: # SON
+  suffix: DRY
+  pattern: QFN
+  pitch: 0.5
+  bodyLength: 1.4-1.5
+  bodyWidth: 0.95-1.05
+  height: 0.51-0.61
+  pullBack: 0.1
+  rowCount: 3
+  columnCount: 2
+  leadLength: 0.25-0.35
+  leadWidth: 0.15-0.25
+
+housing@DSF: # SON
+  suffix: DSF
+  pattern: QFN
+  pitch: 0.35
+  bodyLength: 0.95-1.05
+  bodyWidth: 0.95-1.05
+  height: 0.34-0.40
+  pullBack: 0.0
+  rowCount: 3
+  columnCount: 2
+  leadLength: 0.35-0.45
+  leadWidth: 0.14-0.20
+
+housing@YZP: # BGA
+  suffix: YZP
+  pattern: BGA
+  leadCount: 6 # actually 5, but I'm not sure QEDA handles it well
+  pitch: 0.5
+  bodyWidth: 0.858-0.918 # E
+  bodyLength: 1.358-1.418 # D
+  height: 0.5
+  leadDiameter: 0.21-0.25
+  rowCount: 3
+  columnCount: 2