hathach c545cfc0bc Correct dedicated FIFO SRAM size to 1024 ... add note for up to 5 active IN endpoints (including EP0 IN)		2020-04-10 15:42:50 +07:00
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dcd_esp32s2.c	Correct dedicated FIFO SRAM size to 1024	2020-04-10 15:42:50 +07:00