hathach
f626916a57
update all dwc2 ports to support new dynamic controller support
2022-06-04 23:52:12 +07:00
hathach
31134f41a1
make dwc2 stm32 rhport support dynamic
2022-06-03 17:24:28 +07:00
Ha Thach
fd8afc7e3b
Merge pull request #1454 from Iktek/bugfix_1453
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overwrite grstctl on edpt_disable
2022-06-01 14:36:36 +07:00
hathach
6e7cd220dc
grstctl set fifo + flush in one assign
2022-06-01 13:18:24 +07:00
Ha Thach
9352f75220
Merge pull request #1438 from Nikitarc/master
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Update dwc2_stm32.h
2022-06-01 12:23:32 +07:00
Pascal Speck
f452ab745e
overwrite grstctl on edpt_disable
2022-05-03 09:52:10 +02:00
Nikitarc
c422b9ef41
Update dwc2_stm32.h
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Add missing #endif
2022-04-20 11:29:03 +02:00
Nikitarc
52190e7308
Update dwc2_stm32.h
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Support STM32H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
2022-04-19 21:53:00 +02:00
Reinhard Panhuber
9fde8f2d9e
Fix DSTS_FNSOF in dwc2.c
2022-03-16 07:53:47 +01:00
Reinhard Panhuber
26339e694f
Merge remote-tracking branch 'upstream/add-sof-isr' into add-sof-isr
2022-03-14 20:40:57 +01:00
Reinhard Panhuber
f212899b54
Add SOF callback function for feedback value determination in uac - wip!
2022-03-14 20:40:33 +01:00
Ha Thach
41ffd54fa0
Merge branch 'master' into add-sof-isr
2022-03-14 11:57:01 +07:00
hathach
606f932d92
added dcd_sof_enable() stubs for all other ports
2022-03-07 23:05:05 +07:00
QianHao
65bf5ddb1b
Modify the wrong macro definition code
2022-03-07 08:04:49 +00:00
hathach
a4ba3f2891
add TUP_USBIP_DWC2
2022-02-26 17:13:06 +07:00
hathach
11c89d43ab
more internal rename
2022-02-26 17:06:50 +07:00
hathach
bc63f59af2
mcu specific rename
2022-02-26 15:23:29 +07:00
hathach
99ad3ae2ca
rename and move dcd_attr.h to tusb_mcu_attr.h
2022-02-25 18:35:21 +07:00
hathach
d10326cb4e
rename TUSB_OPT_DEVICE_ENABLED to CFG_TUD_ENABLED
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TUSB_OPT_DEVICE_ENABLED still usable for backward compatible
2022-02-25 18:35:21 +07:00
Scott Shawcroft
a79ffeb764
Add Raspberry Pi Zero W and Zero 2 W
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These are different Broadcom chips. The peripherals are essentially
the same. The main differences are:
* The CPU(s)
* The interrupt controller
* The peripheral base address (but not the peripherals that we use)
2022-01-05 13:47:01 -08:00
Ha Thach
b8d66e4d19
Merge pull request #1206 from hathach/bcm-dwc2-address
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Bcm dwc2 address
2021-11-22 12:07:07 +07:00
hathach
dac7574c98
use USB_OTG_GLOBAL_BASE instead of hard code value
2021-11-22 10:52:28 +07:00
hathach
301d6b4133
clean up
2021-11-17 09:48:08 +07:00
hathach
12e96ce571
set DCFG_XCVRDLY when using external ULPI highspeed phy
2021-11-15 12:18:28 +07:00
hathach
d87a897a7b
xmc4500 ported, cdc msc example run fine
2021-11-05 13:13:21 +07:00
hathach
6cfdf697eb
add hint/question with ISB
2021-11-04 12:42:28 +07:00
hathach
b51d038b65
fix issue with bcm2711 caching issue by ading ISB() after dwc2_dcd_int_enable90
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also add hwcfg_list for reference
2021-11-04 12:30:11 +07:00
hathach
e16506cb52
clean up
2021-11-03 12:24:10 +07:00
hathach
7e68894726
grouping stm32L4 family in bsp
2021-11-02 16:10:40 +07:00
hathach
b809429873
minor clean up
2021-11-02 14:51:15 +07:00
hathach
aa682d7301
add fix for stm32l4 (version 3.10a) which generate transfer complete when setup recieved and control out data complete
2021-11-02 13:52:30 +07:00
hathach
215e0595ab
change F207 to use new dwc2
2021-10-31 00:09:40 +07:00
hathach
b85a6898af
remove dcd_efm32
2021-10-30 20:45:58 +07:00
hathach
9cd5a87c64
add support for EFM32GG
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merge GG12 GG12 to simply OPT_MCU_EFM32GG
2021-10-30 20:42:55 +07:00
hathach
660e8b8c88
skip snpsid check for gd32, abstract phyfs turnaround, set max timeout calibration.
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still has issue with gd32 with msc (does work with running with rtt as
log).
2021-10-29 16:08:19 +07:00
hathach
6c67fc4125
correctly init hs phy for bcm
2021-10-29 00:53:30 +07:00
hathach
7def380058
support bcm2711 on pi4, enhance dcd init with utmi and ulpi hs phy
2021-10-28 12:52:18 +07:00
hathach
9f1cd1a753
add synopsys id check, rename GCCFG_* to STM32_GCCFG-*
2021-10-26 23:10:26 +07:00
hathach
bb5dab5c2e
add hw config struct
2021-10-26 22:48:01 +07:00
hathach
68fa9d4064
enhance fifo read/write
2021-10-26 13:56:56 +07:00
hathach
5d05f8758f
more clean up
2021-10-26 13:36:43 +07:00
hathach
4ebfd00d67
clean up
2021-10-26 13:33:40 +07:00
hathach
de413183d4
use dwc2->epin
2021-10-26 13:07:00 +07:00
hathach
e7655a7567
update the access epout
2021-10-26 13:02:26 +07:00
hathach
34844c9061
use dwc2->fifo[]
2021-10-26 12:53:29 +07:00
hathach
5e1a031800
complete dwc2 regs struct
2021-10-26 12:22:41 +07:00
hathach
3755814f57
add epin, epout to dwc2 regs
2021-10-26 11:49:59 +07:00
hathach
8df078dc9e
more rename
2021-10-26 11:11:46 +07:00
hathach
7369d2441d
update dwc2_type
2021-10-26 00:55:24 +07:00
hathach
460052c8a0
spacing
2021-10-25 21:20:58 +07:00