483 lines
14 KiB
C
483 lines
14 KiB
C
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
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#include "pico.h"
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#include "rp2040_usb.h"
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#if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
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#include "pico/fix/rp2040_usb_device_enumeration.h"
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#endif
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#include "device/dcd.h"
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#include "pico/stdlib.h"
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/*------------------------------------------------------------------*/
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/* Low level controller
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*------------------------------------------------------------------*/
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#define usb_hw_set hw_set_alias(usb_hw)
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#define usb_hw_clear hw_clear_alias(usb_hw)
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// Init these in dcd_init
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static uint8_t assigned_address;
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static uint8_t *next_buffer_ptr;
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// Endpoints 0-15, direction 0 for out and 1 for in.
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static struct hw_endpoint hw_endpoints[16][2] = {0};
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static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, uint8_t in)
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{
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return &hw_endpoints[num][in];
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}
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static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
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{
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uint8_t num = tu_edpt_number(ep_addr);
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uint8_t in = (ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0;
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return hw_endpoint_get_by_num(num, in);
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}
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static void _hw_endpoint_alloc(struct hw_endpoint *ep)
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{
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uint size = 64;
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if (ep->wMaxPacketSize > 64)
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{
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size = ep->wMaxPacketSize;
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}
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// Assumes single buffered for now
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ep->hw_data_buf = next_buffer_ptr;
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next_buffer_ptr += size;
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// Bits 0-5 are ignored by the controller so make sure these are 0
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if ((uintptr_t)next_buffer_ptr & 0b111111u)
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{
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// Round up to the next 64
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uint32_t fixptr = (uintptr_t)next_buffer_ptr;
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fixptr &= ~0b111111u;
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fixptr += 64;
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pico_info("Rounding non 64 byte boundary buffer up from %x to %x\n", (uintptr_t)next_buffer_ptr, fixptr);
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next_buffer_ptr = (uint8_t*)fixptr;
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}
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assert(((uintptr_t)next_buffer_ptr & 0b111111u) == 0);
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uint dpram_offset = hw_data_offset(ep->hw_data_buf);
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assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
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pico_info("Alloced %d bytes at offset 0x%x (0x%p) for ep %d %s\n",
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size,
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dpram_offset,
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ep->hw_data_buf,
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ep->num,
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ep_dir_string[ep->in]);
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// Fill in endpoint control register with buffer offset
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uint32_t reg = EP_CTRL_ENABLE_BITS
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| EP_CTRL_INTERRUPT_PER_BUFFER
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| (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
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| dpram_offset;
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*ep->endpoint_control = reg;
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}
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static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t ep_addr, uint wMaxPacketSize, uint8_t transfer_type)
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{
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uint8_t num = tu_edpt_number(ep_addr);
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bool in = ep_addr & TUSB_DIR_IN_MASK;
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ep->ep_addr = ep_addr;
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ep->in = in;
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// For device, IN is a tx transfer and OUT is an rx transfer
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ep->rx = in == false;
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ep->num = num;
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// Response to a setup packet on EP0 starts with pid of 1
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ep->next_pid = num == 0 ? 1u : 0u;
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// Add some checks around the max packet size
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if (transfer_type == TUSB_XFER_ISOCHRONOUS)
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{
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if (wMaxPacketSize > USB_MAX_ISO_PACKET_SIZE)
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{
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panic("Isochronous wMaxPacketSize %d too large", wMaxPacketSize);
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}
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}
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else
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{
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if (wMaxPacketSize > USB_MAX_PACKET_SIZE)
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{
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panic("Isochronous wMaxPacketSize %d too large", wMaxPacketSize);
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}
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}
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ep->wMaxPacketSize = wMaxPacketSize;
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ep->transfer_type = transfer_type;
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// Every endpoint has a buffer control register in dpram
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if (ep->in)
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{
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ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
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}
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else
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{
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ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out;
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}
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// Clear existing buffer control state
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*ep->buffer_control = 0;
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if (ep->num == 0)
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{
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// EP0 has no endpoint control register because
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// the buffer offsets are fixed
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ep->endpoint_control = NULL;
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// Buffer offset is fixed
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ep->hw_data_buf = (uint8_t*)&usb_dpram->ep0_buf_a[0];
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}
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else
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{
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// Set the endpoint control register (starts at EP1, hence num-1)
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if (in)
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{
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ep->endpoint_control = &usb_dpram->ep_ctrl[num-1].in;
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}
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else
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{
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ep->endpoint_control = &usb_dpram->ep_ctrl[num-1].out;
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}
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// Now alloc a buffer and fill in endpoint control register
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_hw_endpoint_alloc(ep);
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}
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ep->configured = true;
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}
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#if 0 // todo unused
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static void _hw_endpoint_close(struct hw_endpoint *ep)
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{
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// Clear hardware registers and then zero the struct
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// Clears endpoint enable
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*ep->endpoint_control = 0;
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// Clears buffer available, etc
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*ep->buffer_control = 0;
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// Clear any endpoint state
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memset(ep, 0, sizeof(struct hw_endpoint));
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}
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static void hw_endpoint_close(uint8_t ep_addr)
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{
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struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
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_hw_endpoint_close(ep);
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}
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#endif
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static void hw_endpoint_init(uint8_t ep_addr, uint wMaxPacketSize, uint8_t bmAttributes)
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{
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struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
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_hw_endpoint_init(ep, ep_addr, wMaxPacketSize, bmAttributes);
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}
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static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes, bool start)
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{
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struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
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_hw_endpoint_xfer(ep, buffer, total_bytes, start);
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}
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static void hw_handle_buff_status(void)
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{
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uint32_t remaining_buffers = usb_hw->buf_status;
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pico_trace("buf_status 0x%08x\n", remaining_buffers);
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uint bit = 1u;
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for (uint i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
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{
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if (remaining_buffers & bit)
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{
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uint __unused which = (usb_hw->buf_cpu_should_handle & bit) ? 1 : 0;
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// Should be single buffered
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assert(which == 0);
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// clear this in advance
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usb_hw_clear->buf_status = bit;
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// IN transfer for even i, OUT transfer for odd i
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struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u));
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// Continue xfer
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bool done = _hw_endpoint_xfer_continue(ep);
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if (done)
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{
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// Notify
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dcd_event_xfer_complete(0, ep->ep_addr, ep->len, XFER_RESULT_SUCCESS, true);
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hw_endpoint_reset_transfer(ep);
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}
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remaining_buffers &= ~bit;
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}
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bit <<= 1u;
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}
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}
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static void reset_ep0(void)
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{
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// If we have finished this transfer on EP0 set pid back to 1 for next
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// setup transfer. Also clear a stall in case
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uint8_t addrs[] = {0x0, 0x80};
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for (uint i = 0 ; i < count_of(addrs); i++)
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{
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struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]);
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ep->next_pid = 1u;
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ep->stalled = 0;
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}
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}
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static void ep0_0len_status(void)
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{
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// Send 0len complete response on EP0 IN
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reset_ep0();
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hw_endpoint_xfer(0x80, NULL, 0, true);
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}
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static void _hw_endpoint_stall(struct hw_endpoint *ep)
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{
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assert(!ep->stalled);
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if (ep->num == 0)
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{
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// A stall on EP0 has to be armed so it can be cleared on the next setup packet
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usb_hw_set->ep_stall_arm = ep->in ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
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}
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_hw_endpoint_buffer_control_set_mask32(ep, USB_BUF_CTRL_STALL);
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ep->stalled = true;
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}
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static void hw_endpoint_stall(uint8_t ep_addr)
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{
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struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
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_hw_endpoint_stall(ep);
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}
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static void _hw_endpoint_clear_stall(struct hw_endpoint *ep)
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{
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if (ep->num == 0)
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{
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// Probably already been cleared but no harm
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usb_hw_clear->ep_stall_arm = ep->in ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
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}
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_hw_endpoint_buffer_control_clear_mask32(ep, USB_BUF_CTRL_STALL);
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ep->stalled = false;
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}
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static void hw_endpoint_clear_stall(uint8_t ep_addr)
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{
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struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
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_hw_endpoint_clear_stall(ep);
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}
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static void dcd_rp2040_irq(void)
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{
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uint32_t status = usb_hw->ints;
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uint32_t handled = 0;
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if (status & USB_INTS_SETUP_REQ_BITS)
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{
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handled |= USB_INTS_SETUP_REQ_BITS;
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uint8_t const *setup = (uint8_t const *)&usb_dpram->setup_packet;
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// Clear stall bits and reset pid
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reset_ep0();
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// Pass setup packet to tiny usb
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dcd_event_setup_received(0, setup, true);
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usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS;
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}
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if (status & USB_INTS_BUFF_STATUS_BITS)
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{
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handled |= USB_INTS_BUFF_STATUS_BITS;
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hw_handle_buff_status();
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}
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if (status & USB_INTS_BUS_RESET_BITS)
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{
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pico_trace("BUS RESET (addr %d -> %d)\n", assigned_address, 0);
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assigned_address = 0;
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usb_hw->dev_addr_ctrl = assigned_address;
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handled |= USB_INTS_BUS_RESET_BITS;
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dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
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usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
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#if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
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rp2040_usb_device_enumeration_fix();
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#endif
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}
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if (status ^ handled)
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{
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panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
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}
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}
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#define USB_INTS_ERROR_BITS ( \
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USB_INTS_ERROR_DATA_SEQ_BITS | \
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USB_INTS_ERROR_BIT_STUFF_BITS | \
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USB_INTS_ERROR_CRC_BITS | \
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USB_INTS_ERROR_RX_OVERFLOW_BITS | \
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USB_INTS_ERROR_RX_TIMEOUT_BITS)
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/*------------------------------------------------------------------*/
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/* Controller API
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*------------------------------------------------------------------*/
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void dcd_init (uint8_t rhport)
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{
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pico_trace("dcd_init %d\n", rhport);
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assert(rhport == 0);
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// Reset hardware to default state
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rp2040_usb_init();
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irq_set_exclusive_handler(USBCTRL_IRQ, dcd_rp2040_irq);
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memset(hw_endpoints, 0, sizeof(hw_endpoints));
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assigned_address = 0;
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next_buffer_ptr = &usb_dpram->epx_data[0];
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|
|
// EP0 always exists so init it now
|
||
|
|
// EP0 OUT
|
||
|
|
hw_endpoint_init(0x0, 64, 0);
|
||
|
|
// EP0 IN
|
||
|
|
hw_endpoint_init(0x80, 64, 0);
|
||
|
|
|
||
|
|
// Initializes the USB peripheral for device mode and enables it.
|
||
|
|
// Don't need to enable the pull up here. Force VBUS
|
||
|
|
usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS;
|
||
|
|
|
||
|
|
// Enable individual controller IRQS here. Processor interrupt enable will be used
|
||
|
|
// for the global interrupt enable...
|
||
|
|
usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS;
|
||
|
|
usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS;
|
||
|
|
|
||
|
|
dcd_connect(rhport);
|
||
|
|
}
|
||
|
|
|
||
|
|
void dcd_int_enable(uint8_t rhport)
|
||
|
|
{
|
||
|
|
assert(rhport == 0);
|
||
|
|
irq_set_enabled(USBCTRL_IRQ, true);
|
||
|
|
}
|
||
|
|
|
||
|
|
void dcd_int_disable(uint8_t rhport)
|
||
|
|
{
|
||
|
|
assert(rhport == 0);
|
||
|
|
irq_set_enabled(USBCTRL_IRQ, false);
|
||
|
|
}
|
||
|
|
|
||
|
|
void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
|
||
|
|
{
|
||
|
|
pico_trace("dcd_set_address %d %d\n", rhport, dev_addr);
|
||
|
|
assert(rhport == 0);
|
||
|
|
|
||
|
|
// Can't set device address in hardware until status xfer has complete
|
||
|
|
assigned_address = dev_addr;
|
||
|
|
|
||
|
|
ep0_0len_status();
|
||
|
|
}
|
||
|
|
|
||
|
|
void dcd_remote_wakeup(uint8_t rhport)
|
||
|
|
{
|
||
|
|
panic("dcd_remote_wakeup %d\n", rhport);
|
||
|
|
assert(rhport == 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
// disconnect by disabling internal pull-up resistor on D+/D-
|
||
|
|
void dcd_disconnect(uint8_t rhport)
|
||
|
|
{
|
||
|
|
pico_info("dcd_disconnect %d\n", rhport);
|
||
|
|
assert(rhport == 0);
|
||
|
|
usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
|
||
|
|
}
|
||
|
|
|
||
|
|
// connect by enabling internal pull-up resistor on D+/D-
|
||
|
|
void dcd_connect(uint8_t rhport)
|
||
|
|
{
|
||
|
|
pico_info("dcd_connect %d\n", rhport);
|
||
|
|
assert(rhport == 0);
|
||
|
|
usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*------------------------------------------------------------------*/
|
||
|
|
/* DCD Endpoint port
|
||
|
|
*------------------------------------------------------------------*/
|
||
|
|
|
||
|
|
void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
|
||
|
|
{
|
||
|
|
pico_trace("dcd_edpt0_status_complete %d\n", rhport);
|
||
|
|
assert(rhport == 0);
|
||
|
|
|
||
|
|
if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
|
||
|
|
request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
|
||
|
|
request->bRequest == TUSB_REQ_SET_ADDRESS)
|
||
|
|
{
|
||
|
|
pico_trace("Set HW address %d\n", assigned_address);
|
||
|
|
usb_hw->dev_addr_ctrl = assigned_address;
|
||
|
|
}
|
||
|
|
|
||
|
|
reset_ep0();
|
||
|
|
}
|
||
|
|
|
||
|
|
bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
||
|
|
{
|
||
|
|
pico_info("dcd_edpt_open %d %02x\n", rhport, desc_edpt->bEndpointAddress);
|
||
|
|
assert(rhport == 0);
|
||
|
|
hw_endpoint_init(desc_edpt->bEndpointAddress, desc_edpt->wMaxPacketSize.size, desc_edpt->bmAttributes.xfer);
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
||
|
|
{
|
||
|
|
assert(rhport == 0);
|
||
|
|
// True means start new xfer
|
||
|
|
hw_endpoint_xfer(ep_addr, buffer, total_bytes, true);
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
|
||
|
|
{
|
||
|
|
pico_trace("dcd_edpt_stall %d %02x\n", rhport, ep_addr);
|
||
|
|
assert(rhport == 0);
|
||
|
|
hw_endpoint_stall(ep_addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
||
|
|
{
|
||
|
|
pico_trace("dcd_edpt_clear_stall %d %02x\n", rhport, ep_addr);
|
||
|
|
assert(rhport == 0);
|
||
|
|
hw_endpoint_clear_stall(ep_addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
|
||
|
|
{
|
||
|
|
// usbd.c says: In progress transfers on this EP may be delivered after this call
|
||
|
|
pico_trace("dcd_edpt_close %d %02x\n", rhport, ep_addr);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|