Commit Graph

1180 Commits

Author SHA1 Message Date
Ha Thach 6f3378f71d
Merge pull request #476 from kasjer/kasjer/fix-synopsys-fix-iso-frame-bit
Fix synopsys odd/even frame bit for IN ISO endpoints
2020-08-05 22:36:05 +07:00
Jerzy Kasenberg e9aa36a6e8 Fix synopsys odd/even frame bit for IN ISO endpoints
For ISO endpoint driver has to specify when data
is to be transmitted (odd or even frame).
Currently code was not updating this bit resulting in
data being sent every other frame.
If interval was 1ms full data packed was sent every 2ms, and
ZLP was sent in between.
2020-08-04 09:32:41 +02:00
hathach 7d9efd0697 manually submit unplugged event for nrf dcd_disconnect() 2020-08-04 14:18:12 +07:00
Ha Thach 026a1e7ac8
Merge pull request #478 from hathach/move-dcdconnect-to-dcdinit
Move pull-up enabling to dcd_init() instead of usbd
2020-08-04 14:11:32 +07:00
Ha Thach 72464faca4
Merge pull request #472 from hathach/fix-msp430-warning
fix msp430 gcc 9.2.0 warning
2020-08-02 12:53:03 +07:00
hathach acde49ccc9
enable pull-up in dcd_init() instead of usbd 2020-08-01 20:14:58 +07:00
Ha Thach 310797a580
Merge pull request #477 from hathach/fix-nrf-unplugg-isr-event
correct isr context for nrf DCD_EVENT_UNPLUGGED
2020-08-01 12:31:48 +07:00
hathach 9bf2b33366
correct isr context for nrf DCD_EVENT_UNPLUGGED
also rename debug lookup to prevent conflict
2020-08-01 12:02:59 +07:00
Jerzy Kasenberg c3b0389f10 Fix synopsys size check for ISO endpoint
Constraint was incorrect for ISO endpoint as stated in TODO.
2020-07-31 15:52:21 +02:00
hathach 10a8ef7614
fix nested extern declaration of 'SystemCoreClock' [-Werror=nested-externs] 2020-07-29 17:04:47 +07:00
hathach 5af08e2ffc
fix strict prototype 2020-07-29 16:59:07 +07:00
Ha Thach 78f1576e93
Merge pull request #412 from hathach/fix-net-cast-align
suppress cast-align warnings for net device driver
2020-07-29 11:23:11 +07:00
Ha Thach 8dda0a0dd1
Merge pull request #454 from me-no-dev/esp32-s2-fifos
ESP32-S2: Handle the fact that available EP IN FIFOs are less than the number of available EP INs
2020-07-28 15:16:15 +07:00
me-no-dev a1a390a788 Update dcd_esp32s2.c 2020-07-28 10:54:23 +03:00
hathach 6976e64217 fix msp430 gcc 9.2.0 warning in #465 2020-07-28 14:36:15 +07:00
hathach 503c15217e
example to call tud_init() after freeRTOS kernel is started
add note for usb init when using with RTOS
2020-07-23 09:20:45 +07:00
hathach 0407cfe16c fix samd21 race condition with setup packet
reproduced with Adafruit_TinyUSB_ArduinoCore port commit 11d669b4d2a40eb2fc5e51b2a9707a6de9d42363 and SAMD BSP 1.6.1
2020-07-23 01:39:15 +07:00
Ha Thach 7d2fc12445
Merge pull request #469 from hathach/followup-pr466-pr468
Followup pr466 pr468
2020-07-21 21:56:57 +07:00
hathach dfca92d29b
follow up to pr468 2020-07-21 21:06:10 +07:00
Ha Thach be744e1e01
Merge pull request #466 from chang196700/feature/string_desc_msos
Remove 0xEE index string if statement & change TU_ASSERT to TU_VERIFY
2020-07-21 20:25:08 +07:00
me-no-dev 3822a6a385 FreeRTOS: Yield from ISR to notify the USB task
If we do not yeld in ISR when we write to queue/give semaphore, the scheduler will not know of the change and will not check the queue untill the next OS tick. This change causes the task to be called immediately and makes communication many times faster.
2020-07-20 00:46:16 +03:00
Chang Feng 5cd654838b
Remove 0xEE index string if statement & change TU_ASSERT to TU_VERIFY
Signed-off-by: Chang Feng <chang_196700@hotmail.com>
2020-07-19 19:13:17 +08:00
hathach 881025afdc add new name warning to cdc and midi (skip msc, hid warning for now) 2020-07-17 23:01:39 +07:00
hathach 7baeea7a00 update actual link speed for spresense 2020-07-17 18:28:19 +07:00
hathach dc00f0cae1
update link speed detection for nuc505 2020-07-16 20:44:06 +07:00
hathach 0517f4a2f1
dcd tdi report link speed on reset 2020-07-16 16:12:21 +07:00
hathach 5ca748a68e
rename CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE
rename CFG_TUD_HID_BUFSIZE to CFG_TUD_HID_EP_BUFSIZE
2020-07-16 15:34:16 +07:00
hathach fea6fb73a1
add fs & hs config for cdc_msc_freertos, midi_test, msc_dual_lun 2020-07-16 13:04:10 +07:00
hathach 706413f751 add tud_speed_get()
- define both fs and hs configuration descriptor
- rename CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE with default size of 64 for FS, and 512 for HS
2020-07-16 00:44:09 +07:00
Craig Hutchinson 323ae5a84f
Improve comment on CDC tud_cdc_write_available()
Fixes #460
2020-07-10 12:24:09 +01:00
Ha Thach 81392da1ea
Merge pull request #456 from me-no-dev/esp32-s2-epin-to
ESP32-S2: Detect EP IN Xfer Timeout
2020-07-10 12:29:06 +07:00
Ha Thach dbced9911d
Merge pull request #447 from hathach/add-stm-hs
Add support for STM32 OTG HS core
2020-07-08 19:47:24 +07:00
hathach 0fd074afd8
change REDUCE_SPEED=0/1 to explicitly SPEED=high/full
update readme, boards.md to add link to new stm boards
2020-07-08 16:29:48 +07:00
Ha Thach a192d99bf0
Merge pull request #457 from UweBonnes/add-stm-hs
Add stm hs
2020-07-05 14:07:08 +07:00
Uwe Bonnes fd38178189 STM32/OTG_HS: Allow OTG_HS port to run at FS speed.
Add "REDUCE_SPEED=1" to the compile options.
2020-07-03 10:52:57 +02:00
hathach ad5ae8c31d
update per review 2020-07-03 14:50:39 +07:00
hathach a09a86d299
fix NVIC disable typo 2020-07-03 01:19:02 +07:00
me-no-dev d493724a7b ESP32-S2: Detect EP IN Xfer Timeout
In some rare ocasions (bad cable, noise, etc.) data transfer might timeout and hang the endpoint, unless the interrupt flag is cleared.
This pull request targets to solve that case.
2020-07-02 13:05:17 +03:00
hathach 4cec866994
correct HSE_VALUE in hal_conf
- although it is define in CFLAGS, it is worth to correct to be
consistent with other build
- extract set_speed()
2020-07-02 14:57:00 +07:00
hathach 9a290febcd
change default port some stm bsp
- f769disco default port is highspeed port1
- remove PORT0 on stlink since the board only populated HS connector
2020-07-02 11:58:40 +07:00
hathach 4966fb2e13 clean up 2020-07-02 01:25:21 +07:00
hathach c2289777f7 Merge branch 'add-stm-hs' of github.com:hathach/tinyusb into add-stm-hs 2020-07-01 23:53:33 +07:00
Uwe Bonnes 196bdbc702 st/synopsys/dcd_synopsys.c: Remove USBC PHY PLL stabilization delay for now
While the ST code has a 2 ms stabilization delay for the USBC PHY PLL,
running without this delay showed no problem for at leat 10 USB un/replug
cycles. Observe for problems!
2020-07-01 14:45:07 +02:00
hathach d2450abaaf only set turnaround in reset complete 2020-07-01 18:51:04 +07:00
hathach e3974d6869 correctly set turn around according to cpu clock
help to run with low speed mcu
2020-07-01 18:44:52 +07:00
hathach a512a31c9d Merge branch 'master' into add-stm-hs 2020-07-01 17:58:02 +07:00
hathach ed1b670c55 clean up code 2020-07-01 17:57:37 +07:00
me-no-dev 6178f8de2f ESP32-S2: Handle the fact that available EP IN FIFOs are less than the number of available EP INs
ESP32-S2 has only 5 available endpoint-in FIFOs (including EP0) but 7 available EP IN numbers. This change decouples the fifo number from the endpoint number, providing FIFO numbers until they reach the limit, at which point it will return false and assert an error that too many endpoints were allocated.
2020-07-01 13:38:59 +03:00
Ha Thach 0c9932440b
Merge pull request #452 from hathach/fix-dfu-rt
Fix dfu rt
2020-07-01 15:24:39 +07:00
hathach 12a145b27d fix dfu-rt to response to SET_INTERFACE and DFU_GETSTATUS
fix #450
2020-07-01 01:33:02 +07:00