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/*
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* The MIT License ( MIT )
*
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* Copyright ( c ) 2019 Ha Thach ( tinyusb . org )
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*
* Permission is hereby granted , free of charge , to any person obtaining a copy
* of this software and associated documentation files ( the " Software " ) , to deal
* in the Software without restriction , including without limitation the rights
* to use , copy , modify , merge , publish , distribute , sublicense , and / or sell
* copies of the Software , and to permit persons to whom the Software is
* furnished to do so , subject to the following conditions :
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software .
*
* THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR
* IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY ,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM , DAMAGES OR OTHER
* LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , ARISING FROM ,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE .
*
* This file is part of the TinyUSB stack .
*/
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# include "tusb_option.h"
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# if TUSB_OPT_DEVICE_ENABLED && \
( CFG_TUSB_MCU = = OPT_MCU_LPC18XX | | CFG_TUSB_MCU = = OPT_MCU_LPC43XX | | CFG_TUSB_MCU = = OPT_MCU_MIMXRT10XX )
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//--------------------------------------------------------------------+
// INCLUDE
//--------------------------------------------------------------------+
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# if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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# include "fsl_device_registers.h"
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# define INCLUDE_FSL_DEVICE_REGISTERS
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# else
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// LPCOpen for 18xx & 43xx
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# include "chip.h"
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# endif
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# include "common/tusb_common.h"
# include "device/dcd.h"
# include "common_transdimension.h"
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# if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
# define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
# else
# define CleanInvalidateDCache_by_Addr(_addr, _dsize)
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# endif
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//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
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// ENDPTCTRL
enum {
ENDPTCTRL_STALL = TU_BIT ( 0 ) ,
ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT ( 5 ) , ///< used for test only
ENDPTCTRL_TOGGLE_RESET = TU_BIT ( 6 ) ,
ENDPTCTRL_ENABLE = TU_BIT ( 7 )
} ;
// USBSTS, USBINTR
enum {
INTR_USB = TU_BIT ( 0 ) ,
INTR_ERROR = TU_BIT ( 1 ) ,
INTR_PORT_CHANGE = TU_BIT ( 2 ) ,
INTR_RESET = TU_BIT ( 6 ) ,
INTR_SOF = TU_BIT ( 7 ) ,
INTR_SUSPEND = TU_BIT ( 8 ) ,
INTR_NAK = TU_BIT ( 16 )
} ;
// Queue Transfer Descriptor
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typedef struct
{
// Word 0: Next QTD Pointer
uint32_t next ; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
// Word 1: qTQ Token
uint32_t : 3 ;
volatile uint32_t xact_err : 1 ;
uint32_t : 1 ;
volatile uint32_t buffer_err : 1 ;
volatile uint32_t halted : 1 ;
volatile uint32_t active : 1 ;
uint32_t : 2 ;
uint32_t iso_mult_override : 2 ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
uint32_t : 3 ;
uint32_t int_on_complete : 1 ;
volatile uint32_t total_bytes : 15 ;
uint32_t : 0 ;
// Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
uint32_t buffer [ 5 ] ; ///< buffer1 has frame_n for TODO Isochronous
//------------- DCD Area -------------//
uint16_t expected_bytes ;
uint8_t reserved [ 2 ] ;
} dcd_qtd_t ;
TU_VERIFY_STATIC ( sizeof ( dcd_qtd_t ) = = 32 , " size is not correct " ) ;
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// Queue Head
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typedef struct
{
// Word 0: Capabilities and Characteristics
uint32_t : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
uint32_t int_on_setup : 1 ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
uint32_t max_package_size : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
uint32_t : 2 ;
uint32_t zero_length_termination : 1 ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
uint32_t iso_mult : 2 ; ///<
uint32_t : 0 ;
// Word 1: Current qTD Pointer
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volatile uint32_t qtd_addr ;
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// Word 2-9: Transfer Overlay
volatile dcd_qtd_t qtd_overlay ;
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// Word 10-11: Setup request (control OUT only)
volatile tusb_control_request_t setup_request ;
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//--------------------------------------------------------------------+
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/// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
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/// thus there are 16 bytes padding free that we can make use of.
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//--------------------------------------------------------------------+
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uint8_t reserved [ 16 ] ;
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} dcd_qhd_t ;
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TU_VERIFY_STATIC ( sizeof ( dcd_qhd_t ) = = 64 , " size is not correct " ) ;
//--------------------------------------------------------------------+
// Variables
//--------------------------------------------------------------------+
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typedef struct
{
dcd_registers_t * regs ; // registers
const IRQn_Type irqnum ; // IRQ number
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const uint8_t ep_count ; // Max bi-directional Endpoints
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} dcd_controller_t ;
# if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
// Each endpoint with direction (IN/OUT) occupies a queue head
// Therefore QHD_MAX is 2 x max endpoint count
# define QHD_MAX (8*2)
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static const dcd_controller_t _dcd_controller [ ] =
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{
// RT1010 and RT1020 only has 1 USB controller
# if FSL_FEATURE_SOC_USBHS_COUNT == 1
{ . regs = ( dcd_registers_t * ) USB_BASE , . irqnum = USB_OTG1_IRQn , . ep_count = 8 }
# else
{ . regs = ( dcd_registers_t * ) USB1_BASE , . irqnum = USB_OTG1_IRQn , . ep_count = 8 } ,
{ . regs = ( dcd_registers_t * ) USB2_BASE , . irqnum = USB_OTG2_IRQn , . ep_count = 8 }
# endif
} ;
# else
# define QHD_MAX (6*2)
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static const dcd_controller_t _dcd_controller [ ] =
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{
{ . regs = ( dcd_registers_t * ) LPC_USB0_BASE , . irqnum = USB0_IRQn , . ep_count = 6 } ,
{ . regs = ( dcd_registers_t * ) LPC_USB1_BASE , . irqnum = USB1_IRQn , . ep_count = 4 }
} ;
# endif
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# define QTD_NEXT_INVALID 0x01
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typedef struct {
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// Must be at 2K alignment
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dcd_qhd_t qhd [ QHD_MAX ] TU_ATTR_ALIGNED ( 64 ) ;
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dcd_qtd_t qtd [ QHD_MAX ] TU_ATTR_ALIGNED ( 32 ) ; // for portability, TinyUSB only queue 1 TD for each Qhd
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} dcd_data_t ;
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CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED ( 2048 )
static dcd_data_t _dcd_data ;
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//--------------------------------------------------------------------+
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// Controller API
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//--------------------------------------------------------------------+
/// follows LPC43xx User Manual 23.10.3
static void bus_reset ( uint8_t rhport )
{
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dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
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// The reset value for all endpoint types is the control endpoint. If one endpoint
// direction is enabled and the paired endpoint of opposite direction is disabled, then the
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// endpoint type of the unused direction must be changed from the control type to any other
// type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
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// for the data PID tracking on the active endpoint.
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for ( int i = 1 ; i < _dcd_controller [ rhport ] . ep_count ; i + + )
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{
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dcd_reg - > ENDPTCTRL [ i ] = ( TUSB_XFER_BULK < < 2 ) | ( TUSB_XFER_BULK < < 18 ) ;
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}
//------------- Clear All Registers -------------//
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dcd_reg - > ENDPTNAK = dcd_reg - > ENDPTNAK ;
dcd_reg - > ENDPTNAKEN = 0 ;
dcd_reg - > USBSTS = dcd_reg - > USBSTS ;
dcd_reg - > ENDPTSETUPSTAT = dcd_reg - > ENDPTSETUPSTAT ;
dcd_reg - > ENDPTCOMPLETE = dcd_reg - > ENDPTCOMPLETE ;
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while ( dcd_reg - > ENDPTPRIME ) { }
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dcd_reg - > ENDPTFLUSH = 0xFFFFFFFF ;
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while ( dcd_reg - > ENDPTFLUSH ) { }
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// read reset bit in portsc
//------------- Queue Head & Queue TD -------------//
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tu_memclr ( & _dcd_data , sizeof ( dcd_data_t ) ) ;
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//------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
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_dcd_data . qhd [ 0 ] . zero_length_termination = _dcd_data . qhd [ 1 ] . zero_length_termination = 1 ;
_dcd_data . qhd [ 0 ] . max_package_size = _dcd_data . qhd [ 1 ] . max_package_size = CFG_TUD_ENDPOINT0_SIZE ;
_dcd_data . qhd [ 0 ] . qtd_overlay . next = _dcd_data . qhd [ 1 ] . qtd_overlay . next = QTD_NEXT_INVALID ;
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_dcd_data . qhd [ 0 ] . int_on_setup = 1 ; // OUT only
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}
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void dcd_init ( uint8_t rhport )
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{
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tu_memclr ( & _dcd_data , sizeof ( dcd_data_t ) ) ;
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dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
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// Reset controller
dcd_reg - > USBCMD | = USBCMD_RESET ;
while ( dcd_reg - > USBCMD & USBCMD_RESET ) { }
// Set mode to device, must be set immediately after reset
dcd_reg - > USBMODE = USBMODE_CM_DEVICE ;
dcd_reg - > OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION ;
// TODO Force fullspeed on non-highspeed port
// dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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CleanInvalidateDCache_by_Addr ( ( uint32_t * ) & _dcd_data , sizeof ( dcd_data_t ) ) ;
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dcd_reg - > ENDPTLISTADDR = ( uint32_t ) _dcd_data . qhd ; // Endpoint List Address has to be 2K alignment
dcd_reg - > USBSTS = dcd_reg - > USBSTS ;
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dcd_reg - > USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND ;
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dcd_reg - > USBCMD & = ~ 0x00FF0000 ; // Interrupt Threshold Interval = 0
dcd_reg - > USBCMD | = USBCMD_RUN_STOP ; // Connect
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}
void dcd_int_enable ( uint8_t rhport )
{
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NVIC_EnableIRQ ( _dcd_controller [ rhport ] . irqnum ) ;
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}
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void dcd_int_disable ( uint8_t rhport )
{
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NVIC_DisableIRQ ( _dcd_controller [ rhport ] . irqnum ) ;
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}
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void dcd_set_address ( uint8_t rhport , uint8_t dev_addr )
{
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// Response with status first before changing device address
dcd_edpt_xfer ( rhport , tu_edpt_addr ( 0 , TUSB_DIR_IN ) , NULL , 0 ) ;
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dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
dcd_reg - > DEVICEADDR = ( dev_addr < < 25 ) | TU_BIT ( 24 ) ;
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}
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void dcd_remote_wakeup ( uint8_t rhport )
{
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dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
( void ) dcd_reg ;
// dcd_reg->PORTSC1 =
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}
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void dcd_connect ( uint8_t rhport )
{
dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
dcd_reg - > USBCMD | = USBCMD_RUN_STOP ;
}
void dcd_disconnect ( uint8_t rhport )
{
dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
dcd_reg - > USBCMD & = ~ USBCMD_RUN_STOP ;
}
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//--------------------------------------------------------------------+
// HELPER
//--------------------------------------------------------------------+
// index to bit position in register
static inline uint8_t ep_idx2bit ( uint8_t ep_idx )
{
return ep_idx / 2 + ( ( ep_idx % 2 ) ? 16 : 0 ) ;
}
static void qtd_init ( dcd_qtd_t * p_qtd , void * data_ptr , uint16_t total_bytes )
{
tu_memclr ( p_qtd , sizeof ( dcd_qtd_t ) ) ;
p_qtd - > next = QTD_NEXT_INVALID ;
p_qtd - > active = 1 ;
p_qtd - > total_bytes = p_qtd - > expected_bytes = total_bytes ;
if ( data_ptr ! = NULL )
{
p_qtd - > buffer [ 0 ] = ( uint32_t ) data_ptr ;
for ( uint8_t i = 1 ; i < 5 ; i + + )
{
p_qtd - > buffer [ i ] | = tu_align4k ( p_qtd - > buffer [ i - 1 ] ) + 4096 ;
}
}
}
//--------------------------------------------------------------------+
// DCD Endpoint Port
//--------------------------------------------------------------------+
void dcd_edpt_stall ( uint8_t rhport , uint8_t ep_addr )
{
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uint8_t const epnum = tu_edpt_number ( ep_addr ) ;
uint8_t const dir = tu_edpt_dir ( ep_addr ) ;
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dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
dcd_reg - > ENDPTCTRL [ epnum ] | = ENDPTCTRL_STALL < < ( dir ? 16 : 0 ) ;
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}
void dcd_edpt_clear_stall ( uint8_t rhport , uint8_t ep_addr )
{
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uint8_t const epnum = tu_edpt_number ( ep_addr ) ;
uint8_t const dir = tu_edpt_dir ( ep_addr ) ;
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// data toggle also need to be reset
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dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
dcd_reg - > ENDPTCTRL [ epnum ] | = ENDPTCTRL_TOGGLE_RESET < < ( dir ? 16 : 0 ) ;
dcd_reg - > ENDPTCTRL [ epnum ] & = ~ ( ENDPTCTRL_STALL < < ( dir ? 16 : 0 ) ) ;
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}
bool dcd_edpt_open ( uint8_t rhport , tusb_desc_endpoint_t const * p_endpoint_desc )
{
// TODO not support ISO yet
TU_VERIFY ( p_endpoint_desc - > bmAttributes . xfer ! = TUSB_XFER_ISOCHRONOUS ) ;
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uint8_t const epnum = tu_edpt_number ( p_endpoint_desc - > bEndpointAddress ) ;
uint8_t const dir = tu_edpt_dir ( p_endpoint_desc - > bEndpointAddress ) ;
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uint8_t const ep_idx = 2 * epnum + dir ;
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// Must not exceed max endpoint number
TU_ASSERT ( epnum < _dcd_controller [ rhport ] . ep_count ) ;
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//------------- Prepare Queue Head -------------//
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dcd_qhd_t * p_qhd = & _dcd_data . qhd [ ep_idx ] ;
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tu_memclr ( p_qhd , sizeof ( dcd_qhd_t ) ) ;
p_qhd - > zero_length_termination = 1 ;
p_qhd - > max_package_size = p_endpoint_desc - > wMaxPacketSize . size ;
p_qhd - > qtd_overlay . next = QTD_NEXT_INVALID ;
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CleanInvalidateDCache_by_Addr ( ( uint32_t * ) & _dcd_data , sizeof ( dcd_data_t ) ) ;
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// Enable EP Control
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dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
dcd_reg - > ENDPTCTRL [ epnum ] | = ( ( p_endpoint_desc - > bmAttributes . xfer < < 2 ) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET ) < < ( dir ? 16 : 0 ) ;
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return true ;
}
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void dcd_edpt_close_all ( uint8_t rhport )
{
( void ) rhport ;
// TODO implement dcd_edpt_close_all()
}
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bool dcd_edpt_xfer ( uint8_t rhport , uint8_t ep_addr , uint8_t * buffer , uint16_t total_bytes )
{
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dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
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uint8_t const epnum = tu_edpt_number ( ep_addr ) ;
uint8_t const dir = tu_edpt_dir ( ep_addr ) ;
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uint8_t const ep_idx = 2 * epnum + dir ;
if ( epnum = = 0 )
{
// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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while ( dcd_reg - > ENDPTSETUPSTAT & TU_BIT ( 0 ) ) { }
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}
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dcd_qhd_t * p_qhd = & _dcd_data . qhd [ ep_idx ] ;
dcd_qtd_t * p_qtd = & _dcd_data . qtd [ ep_idx ] ;
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// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
// address to 32-byte boundaries.
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// void* cast to suppress cast-align warning, buffer must be
CleanInvalidateDCache_by_Addr ( ( uint32_t * ) tu_align ( ( uint32_t ) buffer , 4 ) , total_bytes + 31 ) ;
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//------------- Prepare qtd -------------//
qtd_init ( p_qtd , buffer , total_bytes ) ;
p_qtd - > int_on_complete = true ;
p_qhd - > qtd_overlay . next = ( uint32_t ) p_qtd ; // link qtd to qhd
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CleanInvalidateDCache_by_Addr ( ( uint32_t * ) & _dcd_data , sizeof ( dcd_data_t ) ) ;
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// start transfer
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dcd_reg - > ENDPTPRIME = TU_BIT ( ep_idx2bit ( ep_idx ) ) ;
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return true ;
}
//--------------------------------------------------------------------+
// ISR
//--------------------------------------------------------------------+
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void dcd_int_handler ( uint8_t rhport )
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{
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dcd_registers_t * dcd_reg = _dcd_controller [ rhport ] . regs ;
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uint32_t const int_enable = dcd_reg - > USBINTR ;
uint32_t const int_status = dcd_reg - > USBSTS & int_enable ;
dcd_reg - > USBSTS = int_status ; // Acknowledge handled interrupt
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// disabled interrupt sources
if ( int_status = = 0 ) return ;
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if ( int_status & INTR_RESET )
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{
bus_reset ( rhport ) ;
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uint32_t speed = ( dcd_reg - > PORTSC1 & PORTSC1_PORT_SPEED ) > > PORTSC1_PORT_SPEED_POS ;
dcd_event_bus_reset ( rhport , ( tusb_speed_t ) speed , true ) ;
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}
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if ( int_status & INTR_SUSPEND )
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{
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if ( dcd_reg - > PORTSC1 & PORTSC1_SUSPEND )
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{
// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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// Skip suspend event if we are not addressed
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if ( ( dcd_reg - > DEVICEADDR > > 25 ) & 0x0f )
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{
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dcd_event_bus_signal ( rhport , DCD_EVENT_SUSPEND , true ) ;
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}
}
}
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// Set if the port controller enters the full or high-speed operational state.
if ( int_status & INTR_PORT_CHANGE )
{
if ( ! ( dcd_reg - > PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS ) )
{
dcd_event_bus_signal ( rhport , DCD_EVENT_UNPLUGGED , true ) ;
}
}
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// Make sure we read the latest version of _dcd_data.
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CleanInvalidateDCache_by_Addr ( ( uint32_t * ) & _dcd_data , sizeof ( dcd_data_t ) ) ;
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if ( int_status & INTR_USB )
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{
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uint32_t const edpt_complete = dcd_reg - > ENDPTCOMPLETE ;
dcd_reg - > ENDPTCOMPLETE = edpt_complete ; // acknowledge
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if ( dcd_reg - > ENDPTSETUPSTAT )
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{
//------------- Set up Received -------------//
// 23.10.10.2 Operational model for setup transfers
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dcd_reg - > ENDPTSETUPSTAT = dcd_reg - > ENDPTSETUPSTAT ; // acknowledge
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dcd_event_setup_received ( rhport , ( uint8_t * ) & _dcd_data . qhd [ 0 ] . setup_request , true ) ;
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}
if ( edpt_complete )
{
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for ( uint8_t ep_idx = 0 ; ep_idx < QHD_MAX ; ep_idx + + )
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{
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if ( tu_bit_test ( edpt_complete , ep_idx2bit ( ep_idx ) ) )
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{
// 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
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dcd_qtd_t * p_qtd = & _dcd_data . qtd [ ep_idx ] ;
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uint8_t result = p_qtd - > halted ? XFER_RESULT_STALLED :
( p_qtd - > xact_err | | p_qtd - > buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS ;
uint8_t const ep_addr = ( ep_idx / 2 ) | ( ( ep_idx & 0x01 ) ? TUSB_DIR_IN_MASK : 0 ) ;
dcd_event_xfer_complete ( rhport , ep_addr , p_qtd - > expected_bytes - p_qtd - > total_bytes , result , true ) ; // only number of bytes in the IOC qtd
}
}
}
}
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if ( int_status & INTR_SOF )
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{
dcd_event_bus_signal ( rhport , DCD_EVENT_SOF , true ) ;
}
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if ( int_status & INTR_NAK ) { }
if ( int_status & INTR_ERROR ) TU_ASSERT ( false , ) ;
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}
# endif