2019-03-20 10:11:42 +01:00
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/*
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* The MIT License (MIT)
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*
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2019-05-14 06:48:05 +02:00
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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2019-03-20 10:11:42 +01:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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2018-12-04 06:47:58 +01:00
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#include "tusb_option.h"
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2018-12-04 07:17:12 +01:00
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#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX)
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2018-12-04 06:47:58 +01:00
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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#include "common/tusb_common.h"
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#include "device/dcd.h"
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2018-12-04 07:17:12 +01:00
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#include "dcd_lpc18_43.h"
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2018-12-04 06:47:58 +01:00
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#include "chip.h"
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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2018-12-04 10:06:50 +01:00
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#define QHD_MAX 12
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#define QTD_NEXT_INVALID 0x01
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2018-12-04 06:47:58 +01:00
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typedef struct {
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2018-12-04 10:06:50 +01:00
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// Must be at 2K alignment
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dcd_qhd_t qhd[QHD_MAX] ATTR_ALIGNED(64);
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dcd_qtd_t qtd[QHD_MAX] ATTR_ALIGNED(32);
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2018-12-04 06:47:58 +01:00
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}dcd_data_t;
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#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
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CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
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#endif
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#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
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CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
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#endif
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static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
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static dcd_data_t* const dcd_data_ptr[2] =
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{
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#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
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&dcd_data0,
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#else
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NULL,
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#endif
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#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
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&dcd_data1
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#else
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NULL
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#endif
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};
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//--------------------------------------------------------------------+
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// CONTROLLER API
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//--------------------------------------------------------------------+
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/// follows LPC43xx User Manual 23.10.3
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static void bus_reset(uint8_t rhport)
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{
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LPC_USBHS_T* lpc_usb = LPC_USB[rhport];
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// The reset value for all endpoint types is the control endpoint. If one endpoint
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// direction is enabled and the paired endpoint of opposite direction is disabled, then the
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// endpoint type of the unused direction must bechanged from the control type to any other
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// type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
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// for the data PID tracking on the active endpoint.
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// USB0 has 5 but USB1 only has 3 non-control endpoints
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for( int i=1; i < (rhport ? 6 : 4); i++)
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{
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lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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}
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//------------- Clear All Registers -------------//
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lpc_usb->ENDPTNAK = lpc_usb->ENDPTNAK;
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lpc_usb->ENDPTNAKEN = 0;
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lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
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lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
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lpc_usb->ENDPTCOMPLETE = lpc_usb->ENDPTCOMPLETE;
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while (lpc_usb->ENDPTPRIME);
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lpc_usb->ENDPTFLUSH = 0xFFFFFFFF;
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while (lpc_usb->ENDPTFLUSH);
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// read reset bit in portsc
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//------------- Queue Head & Queue TD -------------//
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dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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tu_memclr(p_dcd, sizeof(dcd_data_t));
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//------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
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p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1;
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p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDOINT0_SIZE;
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p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
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p_dcd->qhd[0].int_on_setup = 1; // OUT only
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}
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2019-03-29 10:23:00 +01:00
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void dcd_init(uint8_t rhport)
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2018-12-04 06:47:58 +01:00
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{
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LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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tu_memclr(p_dcd, sizeof(dcd_data_t));
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lpc_usb->ENDPOINTLISTADDR = (uint32_t) p_dcd->qhd; // Endpoint List Address has to be 2K alignment
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lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
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lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
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lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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2018-12-14 09:28:38 +01:00
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lpc_usb->USBCMD_D |= TU_BIT(0); // connect
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2018-12-05 07:20:25 +01:00
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}
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void dcd_int_enable(uint8_t rhport)
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{
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2018-12-04 06:47:58 +01:00
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NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
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2018-12-05 07:20:25 +01:00
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}
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2018-12-04 06:47:58 +01:00
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2018-12-05 07:20:25 +01:00
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void dcd_int_disable(uint8_t rhport)
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{
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NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
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2018-12-04 06:47:58 +01:00
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}
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2018-12-17 06:14:11 +01:00
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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{
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2019-03-13 17:14:48 +01:00
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// Response with status first before changing device address
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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2018-12-17 06:14:11 +01:00
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LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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}
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void dcd_set_config(uint8_t rhport, uint8_t config_num)
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{
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(void) rhport;
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(void) config_num;
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// nothing to do
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}
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2019-03-30 08:47:11 +01:00
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void dcd_remote_wakeup(uint8_t rhport)
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{
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(void) rhport;
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}
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2018-12-04 06:47:58 +01:00
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//--------------------------------------------------------------------+
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// HELPER
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//--------------------------------------------------------------------+
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// index to bit position in register
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static inline uint8_t ep_idx2bit(uint8_t ep_idx)
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{
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return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
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}
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static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
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{
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tu_memclr(p_qtd, sizeof(dcd_qtd_t));
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p_qtd->next = QTD_NEXT_INVALID;
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p_qtd->active = 1;
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p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
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if (data_ptr != NULL)
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{
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p_qtd->buffer[0] = (uint32_t) data_ptr;
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for(uint8_t i=1; i<5; i++)
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{
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p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
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}
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}
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}
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//--------------------------------------------------------------------+
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// DCD Endpoint Port
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//--------------------------------------------------------------------+
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void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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{
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2018-12-12 05:51:31 +01:00
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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2018-12-04 06:47:58 +01:00
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2019-03-13 17:14:48 +01:00
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LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
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2018-12-04 06:47:58 +01:00
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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{
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2018-12-12 05:51:31 +01:00
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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2018-12-04 06:47:58 +01:00
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// data toggle also need to be reset
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LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
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LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir ? 16 : 0));
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}
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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{
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// TODO not support ISO yet
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TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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2018-12-12 05:51:31 +01:00
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uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
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uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
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2018-12-04 06:47:58 +01:00
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uint8_t const ep_idx = 2*epnum + dir;
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2018-12-04 10:06:50 +01:00
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// USB0 has 5, USB1 has 3 non-control endpoints
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TU_ASSERT( epnum <= (rhport ? 3 : 5) );
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2018-12-04 06:47:58 +01:00
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//------------- Prepare Queue Head -------------//
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dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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tu_memclr(p_qhd, sizeof(dcd_qhd_t));
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p_qhd->zero_length_termination = 1;
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p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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// Enable EP Control
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LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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return true;
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}
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bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
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{
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2018-12-12 05:51:31 +01:00
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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2018-12-04 06:47:58 +01:00
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uint8_t const ep_idx = 2*epnum + dir;
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dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
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return p_qtd->active;
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// return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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2018-12-12 05:51:31 +01:00
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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2018-12-04 06:47:58 +01:00
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uint8_t const ep_idx = 2*epnum + dir;
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if ( epnum == 0 )
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{
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// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
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// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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2018-12-14 09:28:38 +01:00
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while(LPC_USB[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
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2018-12-04 06:47:58 +01:00
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}
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dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
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//------------- Prepare qtd -------------//
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qtd_init(p_qtd, buffer, total_bytes);
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p_qtd->int_on_complete = true;
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
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// start transfer
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2018-12-14 09:28:38 +01:00
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LPC_USB[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
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2018-12-04 06:47:58 +01:00
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return true;
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}
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//--------------------------------------------------------------------+
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// ISR
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//--------------------------------------------------------------------+
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void hal_dcd_isr(uint8_t rhport)
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{
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LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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uint32_t const int_enable = lpc_usb->USBINTR_D;
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uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
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lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
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if (int_status == 0) return;// disabled interrupt sources
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if (int_status & INT_MASK_RESET)
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{
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bus_reset(rhport);
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dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
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}
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if (int_status & INT_MASK_SUSPEND)
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{
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if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
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{
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// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
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{
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2019-03-28 19:34:53 +01:00
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dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
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2018-12-04 06:47:58 +01:00
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}
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}
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}
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// TODO disconnection does not generate interrupt !!!!!!
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// if (int_status & INT_MASK_PORT_CHANGE)
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// {
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// if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
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// {
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// dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
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// dcd_event_handler(&event, true);
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// }
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// }
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if (int_status & INT_MASK_USB)
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|
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{
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uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
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lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
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dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
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if (lpc_usb->ENDPTSETUPSTAT)
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|
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|
{
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//------------- Set up Received -------------//
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// 23.10.10.2 Operational model for setup transfers
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lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
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|
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dcd_event_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request, true);
|
|
|
|
}
|
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|
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|
|
if ( edpt_complete )
|
|
|
|
{
|
2018-12-04 10:06:50 +01:00
|
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|
for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
|
2018-12-04 06:47:58 +01:00
|
|
|
{
|
2019-05-14 07:54:29 +02:00
|
|
|
if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
|
2018-12-04 06:47:58 +01:00
|
|
|
{
|
|
|
|
// 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
|
|
|
|
dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
|
|
|
|
|
|
|
|
uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
|
|
|
|
( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
|
|
|
|
|
|
|
|
uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
|
|
|
|
dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (int_status & INT_MASK_SOF)
|
|
|
|
{
|
|
|
|
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (int_status & INT_MASK_NAK) {}
|
|
|
|
if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
|
|
|
|
}
|
|
|
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|
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|
|
#endif
|