make: improve panelization

lib: update repo
brd: add contraints and predefined sizes
2024-04-27 10:40:12 +02:00 · 2024-04-19 04:20:05 +02:00 · 2024-04-19 04:18:14 +02:00 · 2024-04-19 04:01:49 +02:00 · 2024-04-19 04:00:26 +02:00 · 2024-04-19 04:00:26 +02:00
25 changed files with 7503 additions and 253 deletions
--- a/.gitignore
+++ b/.gitignore
@ -14,6 +14,7 @@ fp-info-cache
 # temporary files
 *~
 \#*\#
+~*.lck

 # outputs
 *.svg
@ -23,6 +24,7 @@ fp-info-cache
 *.zip
 *.bom.csv
 *.cpl.csv
+*.3d.step
 *.versioned.*
 fabrication

--- a/.qeda.yaml
+++ b/.qeda.yaml
@ -1,6 +1,8 @@
 config:
  nodate: true
-  output: kicad
+  output: kicad7
+  symbol:
+    pinIcon: false
  pattern:
    densityLevel: 'N'
    lineWidth:
--- a/DEVELOPMENT.md
+++ b/DEVELOPMENT.md
@ -5,18 +5,28 @@ requirements

 to be able to generate the outputs, you need following software:

- rake: the central script taking care of generating the output files (Makefile is too cumbersome to parse files)
 - [QEDA](http://qeda.org/): to generate footprints for the parts
- [KiCad](https://www.kicad.org/): EDA software used for schematic capture and board layout
+- [KiCad v8](https://www.kicad.org/): EDA software used for schematic capture and board layout
 - [PcbDraw](https://github.com/yaqwsx/PcbDraw): to generate board layout rendering
 - [KiKit](https://github.com/yaqwsx/KiKit): to generate fabrications files (Gerber, Excellon)
- [KiAuto](https://github.com/INTI-CMNB/KiAuto): to generate schematic printout (PDF)
 - [KiBoM](https://github.com/SchrodingersGat/KiBoM): to generate Bill of Material (CSV)
+- [Interactive HTML BOM](https://github.com/openscopeproject/InteractiveHtmlBom): to generate placement guide
+
+install Interactive HTML BOM using KiCad's Plugin and Content Manager.
+
+for the others:
+
+~~~
+npm install qeda
+pip install pcbdraw kibom kikit
+~~~
+
+you can additionally install  KiKit using KiCad's Plugin and Content Manager for an integrated GUI.

 compiling
 =========

-to generate schematic, BoM, board render, and fabrication output, run `rake`.
+to generate schematic, BoM, board render, and fabrication output, run `make`.

 library
 -------
@ -25,11 +35,13 @@ almost all of the symbols and footprints used in the schematic and board layout
 the `library` folder contains the QEDA parts definitions.

 to install QEDA using NPM from the official repository:
+
 ~~~
 sudo npm install -g qeda
 ~~~

 to install QEDA from the sources:
+
 ~~~
 git clone https://github.com/qeda/qeda
 cd qeda
@ -38,8 +50,9 @@ sudo npm install --global
 ~~~

 to generate the parts:
+
 ~~~
-rake library
+make lib
 ~~~

 this will use the parts definition (.yaml files) in the `library` to generate the symbols (.sym files) and footprints used by KiCAD in the `kicad` folder.
@ -54,16 +67,18 @@ it uses standard symbols, and the ones in the `kicad/` folder.
 most symbols are generated by QEDA as described above.

 to export as pdf:
+
 ~~~
-rake print
+make print
 ~~~

 BOM
 ---

 to export the bill of material (as CSV):
+
 ~~~
-rake bom
+make bom
 ~~~

 board
@ -76,8 +91,9 @@ it uses the footprints from the `kicad/` folder.
 most symbols are generated by QEDA as described above.

 to export gerber files for PCB manufacturer (and photo preview + overview document):
+
 ~~~
-rake fabrication
+make fabrication
 ~~~

 versioning
@ -86,8 +102,7 @@ versioning
 the source schematic and board layout do not include version information.
 when generating schematic or board fabrication output, a copy of the source files with date and version information is done as `.versioned.` files.
 the date corresponds to the last changes (i.e. commit).
-the version is formatted as `v.r hhhhhhh`:
+the version is formatted as `v.r`:

 - `v` corresponds to the major version information defined in `version`
 - `r` corresponds to the total number of changes done to the source files
- `hhhhhhh` corresponds to the git hash of the commit used to generate the version information
--- a/JLCPCB_CORRECTION.csv
+++ b/JLCPCB_CORRECTION.csv
@ -1,6 +0,0 @@
-package,x,y,rot
-LEDC2012X80N,0,0,-90
-UC1608X55N,0,0,90
-SOT95P237X112-3N,0,0,180
-CONNECTOR_MY-1220-03,0,-1.1,0
-CONNECTOR_XKB_U262-24XN-4BV64,0,-1.3,180
--- a/KiBOM_CLI.py
+++ b/KiBOM_CLI.py
@ -0,0 +1,28 @@
+#!/usr/bin/env python3
+"""
+    @package
+    KiBOM - Bill of Materials generation for KiCad
+
+    Generate BOM in xml, csv, txt, tsv, html or xlsx formats.
+
+    - Components are automatically grouped into BoM rows (grouping is configurable)
+    - Component groups count number of components and list component designators
+    - Rows are automatically sorted by component reference(s)
+    - Supports board variants
+
+    Extended options are available in the "bom.ini" config file in the PCB directory
+    (this file is auto-generated with default options the first time the script is executed).
+
+    For usage help:
+    python KiBOM_CLI.py -h
+"""
+
+import sys
+import os
+
+here = os.path.abspath(os.path.dirname(__file__))
+sys.path.insert(0, here)
+
+from kibom.__main__ import main  # noqa: E402
+
+main()
--- a/87
+++ b/87
@ -1,14 +1,21 @@
 # project file name (use for schematic and board layout)
 NAME ?= template
+SUBSHEET ?= 
+# path to KiCad CLI
+KICAD = kicad-cli
 # path to qeda
 QEDA := qeda
+# path to KiBOM
+KIBOM := kibom
+# path to InteractiveHtmlBom
+IBOMGEN := ~/.local/share/kicad/8.0/3rdparty/plugins/org_openscopeproject_InteractiveHtmlBom/generate_interactive_bom.py

 # read project version
 VERSION := $(shell cat version)
 # current date for stamping output
 DATE = $(shell date +%Y-%m-%d)
-# revision based on number of changes on schematic or board layout and current git commit
-REVISION := $(shell git log --pretty=oneline "${NAME}.kicad_sch" "${NAME}.kicad_pcb" | wc -l) $(shell git rev-parse --short HEAD)
+# revision based on number of changes on schematic or board layout
+REVISION := $(shell git log --pretty=oneline "${NAME}.kicad_sch" "${NAME}.kicad_pcb" | wc -l)

 # generate file with version information
 VERSIONED_EXT = kicad_sch kicad_pcb kicad_pro json
@ -18,15 +25,34 @@ define version_rule
 	sed --in-place 's/\$$$$version\$$$$/${VERSION}/g' $$@
 	sed --in-place 's/\$$$$date\$$$$/${DATE}/g' $$@
 	sed --in-place 's/\$$$$revision\$$$$/${REVISION}/g' $$@
+	sed --in-place 's/\.kicad_sch/.versioned.kicad_sch/g' $$@
 endef
 $(foreach EXT,$(VERSIONED_EXT),$(eval $(call version_rule,$(EXT))))
+VERSIONED_SHEET = $(foreach SHEET,$(NAME) $(SUBSHEET),$(SHEET).versioned.kicad_sch)

-all: ${NAME}.sch.pdf ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.bom.csv
+FABRICATION_DIR := fabrication
+IBOM := ${FABRICATION_DIR}/ibom.html
+
+all: $(VERSIONED_SHEET) ${NAME}.sch.pdf ${NAME}.bom.csv render fab
+
+fab: ${FABRICATION_DIR} ${IBOM}
+
+render: ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.brd-top.svg ${NAME}.brd-bot.svg ${NAME}.3d.step

 # generate fabrication files (gerbers/drill/BoM/PnP)
-FABRICATION_DIR := fabrication
-fabrication: ${NAME}.versioned.kicad_sch ${NAME}.versioned.kicad_pcb
-	kikit fab jlcpcb --drc --assembly --schematic $^ ${FABRICATION_DIR}
+${FABRICATION_DIR}: ${NAME}.versioned.kicad_sch ${NAME}.versioned.kicad_pcb
+	kikit fab jlcpcb --no-drc --assembly --field JLCPCB,LCSC --schematic $^ $@
+
+# generate fabrication files (gerbers/drill/uncorrected PnP)
+#${FABRICATION_DIR}: ${NAME}.versioned.kicad_pcb
+#	mkdir -p ${FABRICATION_DIR}
+#	$(KICAD) pcb export gerbers --output ${FABRICATION_DIR} $<
+#	$(KICAD) pcb export drill --output ${FABRICATION_DIR}/ $<
+#	$(KICAD) pcb export pos --output ${FABRICATION_DIR}/${NAME}.versioned.pos $<
+
+# generate interactive BoM
+${IBOM}: ${NAME}.versioned.kicad_pcb
+	python $(IBOMGEN) --no-browser --dest-dir `dirname $@` --name-format `basename $@ ".html"` --show-fields "Value" $< &>/dev/null

 # generate symbols and footprints from parts
 lib:
@ -34,36 +60,53 @@ lib:

 # generate printable version (PDF) of schematic
 %.sch.pdf: %.versioned.kicad_sch %.versioned.kicad_pro
-	eeschema_do export $< .
-	mv $*.versioned.pdf $@
+	$(KICAD) sch export pdf --output $@ $<

 # generate render from layout (top side)
 %.brd-top.png: %.versioned.kicad_pcb
-	pcbdraw --silent $< --dpi 600 $@
+	pcbdraw plot --silent --no-components --dpi 600 --side front $< $@

 # generate render from layout (bottom side)
 %.brd-bot.png: %.versioned.kicad_pcb
-	pcbdraw --silent $< --dpi 600 --back $@
+	pcbdraw plot --silent --no-components --dpi 600 --side back $< $@
+
+# generate render from layout (top side)
+%.brd-top.svg: %.versioned.kicad_pcb
+	$(KICAD) pcb export svg --layers F.Cu,F.Paste,F.Silkscreen,Edge.Cuts --page-size-mode 2 --exclude-drawing-sheet --output $@ $<
+
+# generate render from layout (bottom side)
+%.brd-bot.svg: %.versioned.kicad_pcb
+	$(KICAD) pcb export svg --layers B.Cu,B.Paste,B.Silkscreen,Edge.Cuts --mirror --page-size-mode 2 --exclude-drawing-sheet --output $@ $<

 # export Bill of Material (as CSV)
-%.bom.csv: %.versioned.kicad_sch %.versioned.kicad_pro
-	eeschema_do bom_xml $< .
-	kibom $*.versioned.xml $@
+%.bom.xml: %.versioned.kicad_sch %.versioned.kicad_pro
+	$(KICAD) sch export python-bom --output $@ $<
+
+# export 3D model
+%.3d.step: %.versioned.kicad_pcb
+	$(KICAD) pcb export step --output $@ $<
+
+# export Bill of Material (as CSV)
+%.bom.csv: %.bom.xml
+	$(KIBOM) $< $@

 # generate panel
-PANEL_DIR := panel
-panel: panel.kicad_pcb
-panel.kicad_pcb: ${NAME}.versioned.kicad_pcb ${NAME}.versioned.kicad_pro ${NAME}.versioned.kicad_sch ${NAME}.versioned.json
-	kikit panelize -p ${NAME}.versioned.json ${NAME}.versioned.kicad_pcb $@
-	pcbdraw --silent $@ --dpi 600 panel.brd-top.png
-	pcbdraw --silent $@ --dpi 600 --back panel.brd-bot.png
+PANEL_DIR := panel_fab
+
+panel: panel.kicad_pcb panel.brd-top.svg panel.brd-bot.svg panel.brd-top.png panel.brd-bot.png ${PANEL_DIR}
+
+panel.kicad_pcb: ${NAME}.versioned.kicad_pcb ${NAME}.versioned.kicad_pro ${NAME}.versioned.kicad_sch panel.versioned.json
+	kikit panelize -p panel.versioned.json ${NAME}.versioned.kicad_pcb $@
 	sed --in-place 's/\"missing_courtyard\": \"warning\"/\"missing_courtyard\": \"ignore\"/g' $(patsubst %.kicad_pcb,%.kicad_pro,$@) # the mouse bites don't have a courtyard
-	kikit fab jlcpcb --drc --assembly --missingError --schematic ${NAME}.versioned.kicad_sch $@ ${PANEL_DIR}
+
+${PANEL_DIR}: ${NAME}.versioned.kicad_sch panel.kicad_pcb
+	kikit fab jlcpcb --assembly --missingError --field JLCPCB,LCSC --schematic $^ $@

 clean:
 	rm -f $(foreach EXT,$(VERSIONED_EXT),${NAME}.versioned.$(EXT))
-	rm -f ${NAME}.sch.pdf ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.versioned.xml ${NAME}.bom.csv
+	rm -f ${NAME}.sch.pdf ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.brd-top.svg ${NAME}.brd-bot.svg ${NAME}.versioned.xml ${NAME}.bom.csv
 	rm -f ${NAME}.versioned.kicad_prl ${NAME}.versioned.kicad_pro-bak ${NAME}.versioned.xml ${NAME}.versioned.csv
+	rm -f ${IBOM}
 	rm -rf ${FABRICATION_DIR}
-	rm -f panel.kicad_pcb panel.kicad_pro 
+	rm -f panel.versioned.json panel.kicad_pcb panel.kicad_pro panel.brd-top.svg panel.brd-bot.svg panel.brd-top.png panel.brd-bot.png
 	rm -rf ${PANEL_DIR}
--- a/bom.ini
+++ b/bom.ini
@ -1,10 +1,37 @@
 [BOM_OPTIONS]
+; General BoM options here
+; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
 ignore_dnf = 0
-number_rows = 0
+; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
+html_generate_dnf = 1
+; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
+use_alt = 0
+; If 'alt_wrap' option is set to and integer N, the references field will wrap after N entries are printed
+alt_wrap = 0
+; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
+number_rows = 1
+; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
 group_connectors = 1
-test_regex = 0
+; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
+test_regex = 1
+; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
 merge_blank_fields = 1
+; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
 output_file_name = %O%V
+; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
+variant_file_name_format = _(%V)
+; Field name used to determine if a particular part is to be fitted
+fit_field = Config
+; Make a backup of the bom before generating the new one, using the following template
+;make_backup = %O.tmp
+; Default number of boards to produce if none given on CLI with -n
+number_boards = 1
+; Default PCB variant if none given on CLI with -r
+board_variant = ['default']
+; Whether to hide headers from output file
+hide_headers = False
+; Whether to hide PCB info from output file
+hide_pcb_info = False

 [IGNORE_COLUMNS]
 ; Any column heading that appears here will be excluded from the Generated BoM
@ -15,9 +42,14 @@ Footprint
 Footprint Lib
 Build Quantity
 sheetpath
+qeda_part
+qeda_variant
+name
+JLCPCB_CORRECTION
+Rating

 [COLUMN_ORDER]
-; Columns will apear in the order they are listed here
+; Columns will appear in the order they are listed here
 ; Titles are case-insensitive
 References
 Value
@ -28,15 +60,49 @@ Part Lib
 Footprint
 Footprint Lib
 Build Quantity
+Manufacturer
+MPN
+DigiKey
 LCSC
+JLCPCB
 Datasheet

 [GROUP_FIELDS]
 ; List of fields used for sorting individual components into groups
 ; Components which match (comparing *all* fields) will be grouped together
 ; Field names are case-insensitive
-Part
-Part Lib
 Value
 Footprint
 Footprint Lib
+
+[COMPONENT_ALIASES]
+; A series of values which are considered to be equivalent for the part name
+; Each line represents a list of equivalent component name values separated by white space
+; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
+; Aliases are case-insensitive
+c	c_small	cap	capacitor
+r	r_small	res	resistor
+sw	switch
+l	l_small	inductor
+zener	zenersmall
+d	diode	d_small
+
+[REGEX_INCLUDE]
+; A series of regular expressions used to include parts in the BoM
+; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
+; Column names are case-insensitive
+; Format is: "[ColumName] [Regex]" (white-space separated)
+
+[REGEX_EXCLUDE]
+; A series of regular expressions used to exclude parts from the BoM
+; If a component matches ANY of these, it will be excluded from the BoM
+; Column names are case-insensitive
+; Format is: "[ColumName] [Regex]" (white-space separated)
+References	^TP[0-9]*
+References	^FID
+Part	mount.*hole
+Part	solder.*bridge
+Part	test.*point
+Footprint	test.*point
+Footprint	mount.*hole
+Footprint	fiducial
--- a/2
+++ b/2
@ -1,4 +1,6 @@
 (fp_lib_table
+  (version 7)
  (lib (name "qeda")(type "KiCad")(uri "${KIPRJMOD}/kicad/qeda.pretty")(options "")(descr ""))
  (lib (name "kikit")(type "KiCad")(uri "${KIPRJMOD}/kicad/kikit.pretty")(options "")(descr ""))
+  (lib (name "logo")(type "KiCad")(uri "${KIPRJMOD}/kicad/logo.pretty")(options "")(descr ""))
 )
--- a/kicad/logo.pretty/CuVoodoo_copper.kicad_mod
+++ b/kicad/logo.pretty/CuVoodoo_copper.kicad_mod
@ -0,0 +1,950 @@
+(footprint "CuVoodoo_copper" (version 20221018) (generator pcbnew)
+  (layer "F.Cu")
+  (descr "CuVoodoo logo")
+  (attr smd board_only exclude_from_pos_files exclude_from_bom allow_missing_courtyard)
+  (fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS") hide
+      (effects (font (size 1 1) (thickness 0.1)))
+    (tstamp f846a54a-9ddc-4bbc-be16-9ad293284767)
+  )
+  (fp_text value "CuVoodoo_copper" (at 0 1 unlocked) (layer "F.Fab") hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    (tstamp a2d5c5b6-08b2-4c1d-af6a-961acdb63b34)
+  )
+  (fp_line (start 6 5) (end 6 4)
+    (stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp db907c8a-7c13-47f0-8576-f8342c6fc43f))
+  (fp_line (start 8.75 3.75) (end 6.25 3.75)
+    (stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp 375d8ca2-9b58-471f-b2aa-d5a472f93281))
+  (fp_arc (start 6 4) (mid 6.073223 3.823223) (end 6.25 3.75)
+    (stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp 0af9ea9b-3856-4e16-89c4-11bf31d4c0f6))
+  (fp_poly
+    (pts
+      (xy 1.25 3.999999)
+      (xy 0.5 3.999999)
+      (xy 0.5 3.499999)
+      (xy 1.25 3.499999)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp d164f9a4-dbe2-44e7-8ad8-2d914a8f7a6c))
+  (fp_poly
+    (pts
+      (xy 3.749999 9.499998)
+      (xy 3.499999 9.499998)
+      (xy 3.499999 8.999998)
+      (xy 3.749999 8.999998)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 028a1ea9-a14e-4d86-884a-794e4e371399))
+  (fp_poly
+    (pts
+      (xy 6.249999 9.499998)
+      (xy 5.999999 9.499998)
+      (xy 5.999999 8.999998)
+      (xy 6.249999 8.999998)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 6183cedd-1b0c-488e-b67c-11b1d2d2911f))
+  (fp_poly
+    (pts
+      (xy 9.499998 3.999999)
+      (xy 8.749998 3.999999)
+      (xy 8.749998 3.499999)
+      (xy 9.499998 3.499999)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 9f335a7b-79ff-4f78-b12d-8e0ae29f952f))
+  (fp_poly
+    (pts
+      (xy 4.499999 4.749999)
+      (xy 3.999999 4.749999)
+      (xy 3.999999 5.749999)
+      (xy 4.749999 5.749999)
+      (xy 4.749999 6.249999)
+      (xy 3.499999 6.249999)
+      (xy 3.499999 4.249999)
+      (xy 4.499999 4.249999)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp b5fef6d2-7e7e-4965-bcdc-f4722e8267a7))
+  (fp_poly
+    (pts
+      (xy 6.249999 6.249999)
+      (xy 4.999999 6.249999)
+      (xy 4.999999 5.499999)
+      (xy 5.499999 5.499999)
+      (xy 5.499999 5.749999)
+      (xy 5.749999 5.749999)
+      (xy 5.749999 4.999999)
+      (xy 6.249999 4.999999)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 8bb02f0d-c4a1-49c9-a185-6c1be76e4313))
+  (fp_poly
+    (pts
+      (xy 4.750097 1.749764)
+      (xy 3.999755 1.749764)
+      (xy 3.999755 1.250053)
+      (xy 4.249869 1.250053)
+      (xy 4.249869 1.500167)
+      (xy 4.499983 1.500167)
+      (xy 4.499983 1.250053)
+      (xy 4.249869 1.250053)
+      (xy 3.999755 1.250053)
+      (xy 3.999755 0.999939)
+      (xy 4.750097 0.999939)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 3d4db89c-b5bd-4689-87d8-3730cf8df8f4))
+  (fp_poly
+    (pts
+      (xy 4.499999 6.499999)
+      (xy 4.249999 6.749999)
+      (xy 3.849999 6.749999)
+      (xy 3.749999 6.849998)
+      (xy 3.749999 8.999998)
+      (xy 3.499999 8.999998)
+      (xy 3.499999 6.749999)
+      (xy 3.749999 6.499999)
+      (xy 4.149999 6.499999)
+      (xy 4.249999 6.399999)
+      (xy 4.249999 6.249999)
+      (xy 4.499999 6.249999)
+    )
+
+    (stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp f8a10a30-88d4-4521-a785-068b4a34a6b4))
+  (fp_poly
+    (pts
+      (xy 5.099999 3.949999)
+      (xy 5.099999 4.299999)
+      (xy 4.799999 4.599999)
+      (xy 4.499999 4.599999)
+      (xy 4.499999 4.399999)
+      (xy 4.749999 4.399999)
+      (xy 4.899999 4.249999)
+      (xy 4.899999 3.999999)
+      (xy 4.749999 3.849999)
+      (xy 1.25 3.849999)
+      (xy 1.25 3.649999)
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--- a/kicad/logo.pretty/CuVoodoo_silk.kicad_mod
+++ b/kicad/logo.pretty/CuVoodoo_silk.kicad_mod
@ -0,0 +1,617 @@
+(footprint "CuVoodoo_silk" (version 20221018) (generator pcbnew)
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--- a/kicad/logo.pretty/OSHW.kicad_mod
+++ b/kicad/logo.pretty/OSHW.kicad_mod
@ -0,0 +1,108 @@
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--- a/kicad/logo.pretty/bunny.kicad_mod
+++ b/kicad/logo.pretty/bunny.kicad_mod
@ -0,0 +1,599 @@
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+      (xy 2.188289 3.47189)
+      (xy 2.208415 3.242973)
+      (xy 2.239072 3.024372)
+      (xy 2.277221 2.816213)
+      (xy 2.319386 2.615833)
+      (xy 2.366035 2.422758)
+      (xy 2.417633 2.236518)
+      (xy 2.474647 2.05664)
+      (xy 2.537545 1.882652)
+      (xy 2.606794 1.714081)
+      (xy 2.682859 1.550457)
+      (xy 2.766207 1.391305)
+      (xy 2.857307 1.236156)
+      (xy 2.956623 1.084536)
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+      (xy 3.181775 0.789995)
+      (xy 3.308544 0.646131)
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+      (xy 4.465452 0.183125)
+      (xy 4.643061 0.166618)
+      (xy 4.821278 0.156654)
+      (xy 4.999922 0.153259)
+    )
+
+    (stroke (width 0.030656) (type solid)) (fill solid) (layer "F.SilkS") (tstamp 3dfa6f02-7e21-4feb-9fef-4f78bfeaddc9))
+)
--- a/kicad/logo/bunny.svg
+++ b/kicad/logo/bunny.svg
--- a/kicad/logo/dragon.svg
+++ b/kicad/logo/dragon.svg
--- a/kicad/partdb.kicad_dbl
+++ b/kicad/partdb.kicad_dbl
--- a/kicad/qeda.3dshapes/UPC2012X80N.wrl
+++ b/kicad/qeda.3dshapes/UPC2012X80N.wrl
@ -0,0 +1,35 @@
+#VRML V2.0 utf8
+Shape {
+  appearance Appearance {
+    material Material {
+    diffuseColor 0.37 0.37 0.37
+    emissiveColor 0.0 0.0 0.0
+    specularColor 1.0 1.0 1.0
+    ambientIntensity 1.0
+    transparency 0.5
+    shininess 1.0
+    }
+  }
+  geometry IndexedFaceSet {
+    coord Coordinate {
+      point [
+        -0.6 -1 0,
+        0.6 -1 0,
+        0.6 1 0,
+        -0.6 1 0,
+        -0.6 -1 0.8,
+        0.6 -1 0.8,
+        0.6 1 0.8,
+        -0.6 1 0.8
+      ]
+    }
+    coordIndex [
+      0,1,2,3,-1
+      4,5,6,7,-1
+      0,1,5,4,-1
+      2,3,7,6,-1
+      0,3,7,4,-1
+      1,2,6,5,-1
+    ]
+  }
+}
--- a/kicad/qeda.dcm
+++ b/kicad/qeda.dcm
@ -1,17 +0,0 @@
-EESchema-DOCLIB  Version 2.0 Date: 00/00/0000 00:00:00
-#
-$CMP R0603
-D resistor, chip, 1.6x0.8 mm
-$ENDCMP
-#
-$CMP C0603
-D Chip capacitor 1.6x0.8 mm
-K Capacitor
-$ENDCMP
-#
-$CMP LED0805
-D diode, LED, chip, 2.0x1.2 mm
-K LED
-$ENDCMP
-#
-# End Doc Library
--- a/kicad/qeda.kicad_sym
+++ b/kicad/qeda.kicad_sym
@ -0,0 +1,142 @@
+(kicad_symbol_lib (version 20211014) (generator qeda)
+  (symbol "R0603" (pin_numbers hide) (pin_names hide) (in_bom yes) (on_board yes)
+    (property "Reference" "R"
+      (id 0)
+      (at 0.000 1.778 0)
+      (effects (font (size 1.27 1.27)) (justify bottom))
+    )
+    (property "Value" "R0603"
+      (id 1)
+      (at 0.000 -1.778 0)
+      (effects (font (size 1.27 1.27)) (justify top))
+    )
+    (property "Footprint" "qeda:UC1608X55N"
+      (id 2)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_description" "resistor, chip, 1.6x0.8 mm"
+      (id 3)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (rectangle (start -2.540 1.016) (end 2.540 -1.016) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type background)))
+    (pin passive line
+      (at -3.810 0.000 0)
+      (length 1.270)
+      (name "L"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "1"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+    (pin passive line
+      (at 3.810 0.000 180)
+      (length 1.270)
+      (name "R"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "2"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+  )
+  (symbol "C0603" (pin_numbers hide) (pin_names hide) (in_bom yes) (on_board yes)
+    (property "Reference" "C"
+      (id 0)
+      (at 0.000 2.794 0)
+      (effects (font (size 1.27 1.27)) (justify bottom))
+    )
+    (property "Value" "C0603"
+      (id 1)
+      (at 0.000 -2.794 0)
+      (effects (font (size 1.27 1.27)) (justify top))
+    )
+    (property "Footprint" "qeda:CAPC1608X92N"
+      (id 2)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_description" "Chip capacitor 1.6x0.8 mm"
+      (id 3)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_keywords" "Capacitor"
+      (id 4)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (polyline (pts (xy -0.381 2.032) (xy -0.381 -2.032)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (polyline (pts (xy 0.381 2.032) (xy 0.381 -2.032)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (pin passive line
+      (at -2.540 0.000 0)
+      (length 2.159)
+      (name "L"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "1"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+    (pin passive line
+      (at 2.540 0.000 180)
+      (length 2.159)
+      (name "R"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "2"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+  )
+  (symbol "LED0805" (pin_numbers hide) (pin_names hide) (in_bom yes) (on_board yes)
+    (property "Reference" "D"
+      (id 0)
+      (at 0.000 2.032 0)
+      (effects (font (size 1.27 1.27)) (justify bottom))
+    )
+    (property "Value" "LED0805"
+      (id 1)
+      (at 0.000 -2.032 0)
+      (effects (font (size 1.27 1.27)) (justify top))
+    )
+    (property "Footprint" "qeda:UPC2012X80N"
+      (id 2)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "ki_description" "diode, LED, chip, 2.0x1.2 mm"
+      (id 3)
+      (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (polyline (pts (xy -1.016 1.270) (xy 1.016 0.000) (xy -1.016 -1.270) (xy -1.016 1.270)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type background)))
+    (polyline (pts (xy 1.016 1.270) (xy 1.016 -1.270)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (polyline (pts (xy 1.270 1.905) (xy 2.540 3.175)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (polyline (pts (xy 1.725 2.720) (xy 2.540 3.175) (xy 2.085 2.360) (xy 1.725 2.720)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type outline)))
+    (polyline (pts (xy 1.905 1.270) (xy 3.175 2.540)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type none)))
+    (polyline (pts (xy 2.360 2.085) (xy 3.175 2.540) (xy 2.720 1.725) (xy 2.360 2.085)) (stroke (width 0.305) (type default) (color 0 0 0 0)) (fill (type outline)))
+    (pin passive line
+      (at -2.540 0.000 0)
+      (length 1.524)
+      (name "A"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "2"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+    (pin passive line
+      (at 2.540 0.000 180)
+      (length 1.524)
+      (name "C"
+        (effects (font (size 1.27 1.27)))
+      )
+      (number "1"
+        (effects (font (size 1.27 1.27)))
+      )
+    )
+  )
+)
--- a/kicad/qeda.lib
+++ b/kicad/qeda.lib
@ -1,57 +0,0 @@
-EESchema-LIBRARY Version 2.3 Date: 00/00/0000 00:00:00
-#encoding utf-8
-#
-# R0603
-#
-DEF R0603 R 0 40 N N 1 L N
-F0 "R" 0 70 50 H V C BNN
-F1 "R0603" 0 -70 50 H V C TNN
-F2 "qeda:UC1608X55N" 0 0 0 H I C CNN
-$FPLIST
-  UC1608X55N
-$ENDFPLIST
-DRAW
-S -100 40 100 -40 1 1 12 f
-X L 1 -150 0 50 R 50 50 1 1 P
-X R 2 150 0 50 L 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# C0603
-#
-DEF C0603 C 0 40 N N 1 L N
-F0 "C" 0 110 50 H V C BNN
-F1 "C0603" 0 -110 50 H V C TNN
-F2 "qeda:CAPC1608X92N" 0 0 0 H I C CNN
-$FPLIST
-  CAPC1608X92N
-$ENDFPLIST
-DRAW
-P 2 1 1 12 -15 80 -15 -80 N
-P 2 1 1 12 15 80 15 -80 N
-X L 1 -100 0 85 R 50 50 1 1 P
-X R 2 100 0 85 L 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# LED0805
-#
-DEF LED0805 D 0 40 N N 1 L N
-F0 "D" 0 80 50 H V C BNN
-F1 "LED0805" 0 -80 50 H V C TNN
-F2 "qeda:LEDC2012X80N" 0 0 0 H I C CNN
-$FPLIST
-  LEDC2012X80N
-$ENDFPLIST
-DRAW
-P 4 1 1 12 -40 50 40 0 -40 -50 -40 50 f
-P 2 1 1 12 40 50 40 -50 N
-P 2 1 1 12 50 75 100 125 N
-P 4 1 1 12 68 107 100 125 82 93 68 107 F
-P 2 1 1 12 75 50 125 100 N
-P 4 1 1 12 93 82 125 100 107 68 93 82 F
-X A 2 -100 0 60 R 50 50 1 1 P
-X C 1 100 0 60 L 50 50 1 1 P
-ENDDRAW
-ENDDEF
-# End Library
--- a/kicad/qeda.pretty/UPC2012X80N.kicad_mod
+++ b/kicad/qeda.pretty/UPC2012X80N.kicad_mod
@ -0,0 +1,42 @@
+(module UPC2012X80N (layer F.Cu)
+  (attr smd)
+  (pad 1 smd rect (at 0.000 -0.900) (size 1.600 1.100) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (pad 2 smd rect (at 0.000 0.900) (size 1.600 1.100) (layers F.Cu F.Mask F.Paste)
+    (solder_mask_margin 0.050))
+  (fp_text reference REF** (at 0.000 0.000) (layer F.SilkS)
+    (effects (font (size 1.200 1.200) (thickness 0.200)))
+  )
+  (fp_line (start -1.100 -1.100) (end -1.100 1.100) (layer F.SilkS) (width 0.200))
+  (fp_line (start 1.100 -1.100) (end 1.100 1.100) (layer F.SilkS) (width 0.200))
+  (fp_line (start -1.100 -1.100) (end -1.100 -1.750) (layer F.SilkS) (width 0.200))
+  (fp_line (start -1.100 -1.750) (end 1.100 -1.750) (layer F.SilkS) (width 0.200))
+  (fp_line (start 1.100 -1.750) (end 1.100 -1.100) (layer F.SilkS) (width 0.200))
+  (fp_circle (center 0.000 0.000) (end 0.000 0.500) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.700 0.000) (end 0.700 0.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.000 -0.700) (end 0.000 0.700) (layer F.Fab) (width 0.100))
+  (fp_text value UPC2012X80N (at 0.000 0.000 90) (layer F.Fab)
+    (effects (font (size 0.792 0.792) (thickness 0.100)))
+  )
+  (fp_text user REF** (at 0.000 0.000 90) hide (layer F.Fab)
+    (effects (font (size 0.792 0.792) (thickness 0.100)))
+  )
+  (fp_line (start 0.000 -1.000) (end 0.600 -1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.600 -1.000) (end 0.600 1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start 0.600 1.000) (end -0.600 1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.600 1.000) (end -0.600 -0.400) (layer F.Fab) (width 0.100))
+  (fp_line (start -0.600 -0.400) (end 0.000 -1.000) (layer F.Fab) (width 0.100))
+  (fp_line (start -1.050 -1.700) (end -1.050 -1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -1.050 -1.250) (end -1.050 1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -1.050 1.250) (end -1.050 1.700) (layer F.CrtYd) (width 0.050))
+  (fp_line (start -1.050 1.700) (end 1.050 1.700) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 1.700) (end 1.050 1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 1.250) (end 1.050 -1.250) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 -1.250) (end 1.050 -1.700) (layer F.CrtYd) (width 0.050))
+  (fp_line (start 1.050 -1.700) (end -1.050 -1.700) (layer F.CrtYd) (width 0.050))
+  (model UPC2012X80N.wrl
+    (at (xyz 0 0 0))
+    (scale (xyz 0.3937 0.3937 0.3937))
+    (rotate (xyz 0 0 0 ))
+  )
+)
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 47ad2bcbf9c3696c251db59592c7095a634bdb33
+Subproject commit 3f3f15e7c3aacf85d86bfeb31cfcd14abf2f66e1
--- a/5
+++ b/5
@ -1,3 +1,6 @@
 (sym_lib_table
-  (lib (name "qeda")(type "Legacy")(uri "${KIPRJMOD}/kicad/qeda.lib")(options "")(descr ""))
+  (version 7)
+  (lib (name "qeda")(type "KiCad")(uri "${KIPRJMOD}/kicad/qeda.kicad_sym")(options "")(descr ""))
+  (lib (name "partdb")(type "Database")(uri "${KIPRJMOD}/kicad/partdb.kicad_dbl")(options "")(descr ""))
+  (lib (name "Connector_Audio")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Connector_Audio.kicad_sym")(options "")(descr ""))
 )
--- a/template.kicad_pcb
+++ b/template.kicad_pcb
@ -1,86 +1,113 @@
-(kicad_pcb (version 20211014) (generator pcbnew)
-
-  (general
-    (thickness 1.6)
-  )
-
-  (paper "A4")
-  (title_block
-    (date "$date$")
-    (rev "$version$.$revision$")
-    (company "CuVoodoo")
-    (comment 1 "King Kévin")
-    (comment 2 "CERN-OHL-S")
-  )
-
-  (layers
-    (0 "F.Cu" signal)
-    (31 "B.Cu" signal)
-    (33 "F.Adhes" user "F.Adhesive")
-    (34 "B.Paste" user)
-    (35 "F.Paste" user)
-    (36 "B.SilkS" user "B.Silkscreen")
-    (37 "F.SilkS" user "F.Silkscreen")
-    (38 "B.Mask" user)
-    (39 "F.Mask" user)
-    (44 "Edge.Cuts" user)
-    (45 "Margin" user)
-    (46 "B.CrtYd" user "B.Courtyard")
-    (47 "F.CrtYd" user "F.Courtyard")
-    (48 "B.Fab" user)
-    (49 "F.Fab" user)
-  )
-
-  (setup
-    (stackup
-      (layer "F.SilkS" (type "Top Silk Screen"))
-      (layer "F.Paste" (type "Top Solder Paste"))
-      (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
-      (layer "F.Cu" (type "copper") (thickness 0.035))
-      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
-      (layer "B.Cu" (type "copper") (thickness 0.035))
-      (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
-      (layer "B.Paste" (type "Bottom Solder Paste"))
-      (layer "B.SilkS" (type "Bottom Silk Screen"))
-      (copper_finish "None")
-      (dielectric_constraints no)
-    )
-    (pad_to_mask_clearance 0)
-    (pcbplotparams
-      (layerselection 0x00010fc_ffffffff)
-      (disableapertmacros false)
-      (usegerberextensions false)
-      (usegerberattributes true)
-      (usegerberadvancedattributes true)
-      (creategerberjobfile true)
-      (svguseinch false)
-      (svgprecision 6)
-      (excludeedgelayer true)
-      (plotframeref false)
-      (viasonmask false)
-      (mode 1)
-      (useauxorigin false)
-      (hpglpennumber 1)
-      (hpglpenspeed 20)
-      (hpglpendiameter 15.000000)
-      (dxfpolygonmode true)
-      (dxfimperialunits true)
-      (dxfusepcbnewfont true)
-      (psnegative false)
-      (psa4output false)
-      (plotreference true)
-      (plotvalue true)
-      (plotinvisibletext false)
-      (sketchpadsonfab false)
-      (subtractmaskfromsilk false)
-      (outputformat 1)
-      (mirror false)
-      (drillshape 1)
-      (scaleselection 1)
-      (outputdirectory "")
-    )
-  )
-
-  (net 0 "")
-
-)
+(kicad_pcb
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(general
+		(thickness 1.6)
+		(legacy_teardrops no)
+	)
+	(paper "A4")
+	(title_block
+		(date "$date$")
+		(rev "$version$.$revision$")
+		(company "CuVoodoo")
+		(comment 1 "King Kévin")
+		(comment 2 "CERN-OHL-S")
+	)
+	(layers
+		(0 "F.Cu" signal)
+		(31 "B.Cu" signal)
+		(33 "F.Adhes" user "F.Adhesive")
+		(36 "B.SilkS" user "B.Silkscreen")
+		(37 "F.SilkS" user "F.Silkscreen")
+		(38 "B.Mask" user)
+		(39 "F.Mask" user)
+		(44 "Edge.Cuts" user)
+		(45 "Margin" user)
+		(46 "B.CrtYd" user "B.Courtyard")
+		(47 "F.CrtYd" user "F.Courtyard")
+		(48 "B.Fab" user)
+		(49 "F.Fab" user)
+	)
+	(setup
+		(stackup
+			(layer "F.SilkS"
+				(type "Top Silk Screen")
+				(color "White")
+			)
+			(layer "F.Mask"
+				(type "Top Solder Mask")
+				(color "Green")
+				(thickness 0.01)
+			)
+			(layer "F.Cu"
+				(type "copper")
+				(thickness 0.035)
+			)
+			(layer "dielectric 1"
+				(type "core")
+				(color "Polyimide")
+				(thickness 1.51)
+				(material "FR4")
+				(epsilon_r 4.5)
+				(loss_tangent 0.02)
+			)
+			(layer "B.Cu"
+				(type "copper")
+				(thickness 0.035)
+			)
+			(layer "B.Mask"
+				(type "Bottom Solder Mask")
+				(color "Green")
+				(thickness 0.01)
+			)
+			(layer "B.SilkS"
+				(type "Bottom Silk Screen")
+				(color "White")
+			)
+			(copper_finish "HAL SnPb")
+			(dielectric_constraints no)
+		)
+		(pad_to_mask_clearance 0.038)
+		(solder_mask_min_width 0.1)
+		(allow_soldermask_bridges_in_footprints no)
+		(pcbplotparams
+			(layerselection 0x00010fc_ffffffff)
+			(plot_on_all_layers_selection 0x0000000_00000000)
+			(disableapertmacros no)
+			(usegerberextensions no)
+			(usegerberattributes yes)
+			(usegerberadvancedattributes yes)
+			(creategerberjobfile yes)
+			(dashed_line_dash_ratio 12.000000)
+			(dashed_line_gap_ratio 3.000000)
+			(svgprecision 6)
+			(plotframeref no)
+			(viasonmask no)
+			(mode 1)
+			(useauxorigin no)
+			(hpglpennumber 1)
+			(hpglpenspeed 20)
+			(hpglpendiameter 15.000000)
+			(pdf_front_fp_property_popups yes)
+			(pdf_back_fp_property_popups yes)
+			(dxfpolygonmode yes)
+			(dxfimperialunits yes)
+			(dxfusepcbnewfont yes)
+			(psnegative no)
+			(psa4output no)
+			(plotreference yes)
+			(plotvalue yes)
+			(plotfptext yes)
+			(plotinvisibletext no)
+			(sketchpadsonfab no)
+			(subtractmaskfromsilk no)
+			(outputformat 1)
+			(mirror no)
+			(drillshape 1)
+			(scaleselection 1)
+			(outputdirectory "")
+		)
+	)
+	(net 0 "")
+)
--- a/template.kicad_pro
+++ b/template.kicad_pro
@ -1,26 +1,30 @@
 {
  "board": {
+    "3dviewports": [],
    "design_settings": {
      "defaults": {
-        "board_outline_line_width": 0.09999999999999999,
-        "copper_line_width": 0.19999999999999998,
+        "apply_defaults_to_fp_fields": false,
+        "apply_defaults_to_fp_shapes": false,
+        "apply_defaults_to_fp_text": false,
+        "board_outline_line_width": 0.05,
+        "copper_line_width": 0.2,
        "copper_text_italic": false,
        "copper_text_size_h": 1.5,
        "copper_text_size_v": 1.5,
        "copper_text_thickness": 0.3,
        "copper_text_upright": false,
-        "courtyard_line_width": 0.049999999999999996,
+        "courtyard_line_width": 0.05,
        "dimension_precision": 4,
        "dimension_units": 3,
        "dimensions": {
          "arrow_length": 1270000,
          "extension_offset": 500000,
          "keep_text_aligned": true,
-          "suppress_zeroes": false,
+          "suppress_zeroes": true,
          "text_position": 0,
          "units_format": 1
        },
-        "fab_line_width": 0.09999999999999999,
+        "fab_line_width": 0.1,
        "fab_text_italic": false,
        "fab_text_size_h": 1.0,
        "fab_text_size_v": 1.0,
@ -53,6 +57,11 @@
          "gap": 0.0,
          "via_gap": 0.0,
          "width": 0.0
+        },
+        {
+          "gap": 0.43,
+          "via_gap": 0.0,
+          "width": 0.2
        }
      ],
      "drc_exclusions": [],
@ -62,20 +71,27 @@
      "rule_severities": {
        "annular_width": "error",
        "clearance": "error",
+        "connection_width": "warning",
        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
        "courtyards_overlap": "error",
        "diff_pair_gap_out_of_range": "error",
        "diff_pair_uncoupled_length_too_long": "error",
        "drill_out_of_range": "error",
        "duplicate_footprints": "warning",
        "extra_footprint": "warning",
-        "footprint_type_mismatch": "error",
+        "footprint": "error",
+        "footprint_symbol_mismatch": "warning",
+        "footprint_type_mismatch": "warning",
        "hole_clearance": "error",
        "hole_near_hole": "error",
        "invalid_outline": "error",
+        "isolated_copper": "warning",
        "item_on_disabled_layer": "error",
        "items_not_allowed": "error",
        "length_out_of_range": "error",
+        "lib_footprint_issues": "ignore",
+        "lib_footprint_mismatch": "ignore",
        "malformed_courtyard": "error",
        "microvia_drill_out_of_range": "error",
        "missing_courtyard": "warning",
@ -85,9 +101,14 @@
        "padstack": "error",
        "pth_inside_courtyard": "ignore",
        "shorting_items": "error",
+        "silk_edge_clearance": "ignore",
        "silk_over_copper": "warning",
        "silk_overlap": "warning",
        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_thickness": "warning",
        "through_hole_pad_without_hole": "error",
        "too_many_vias": "error",
        "track_dangling": "warning",
@ -104,33 +125,131 @@
        "allow_microvias": false,
        "max_error": 0.005,
        "min_clearance": 0.127,
-        "min_copper_edge_clearance": 0.19999999999999998,
+        "min_connection": 0.127,
+        "min_copper_edge_clearance": 0.3,
        "min_hole_clearance": 0.254,
        "min_hole_to_hole": 0.254,
-        "min_microvia_diameter": 0.19999999999999998,
-        "min_microvia_drill": 0.09999999999999999,
-        "min_silk_clearance": 0.0,
+        "min_microvia_diameter": 0.2,
+        "min_microvia_drill": 0.1,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.15,
+        "min_text_height": 1.0,
+        "min_text_thickness": 0.153,
        "min_through_hole_diameter": 0.3,
        "min_track_width": 0.127,
        "min_via_annular_width": 0.13,
        "min_via_diameter": 0.5,
        "solder_mask_clearance": 0.0,
        "solder_mask_min_width": 0.0,
+        "solder_mask_to_copper_clearance": 0.05,
        "use_height_for_length_calcs": true
      },
-      "track_widths": [
-        0.0
+      "teardrop_options": [
+        {
+          "td_onpadsmd": true,
+          "td_onroundshapesonly": false,
+          "td_ontrackend": false,
+          "td_onviapad": true
+        }
      ],
+      "teardrop_parameters": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
+      "track_widths": [
+        0.0,
+        0.127,
+        0.2,
+        0.3,
+        0.5
+      ],
+      "tuning_pattern_settings": {
+        "diff_pair_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 1.0
+        },
+        "diff_pair_skew_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        },
+        "single_track_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        }
+      },
      "via_dimensions": [
        {
          "diameter": 0.0,
          "drill": 0.0
+        },
+        {
+          "diameter": 0.6,
+          "drill": 0.3
+        },
+        {
+          "diameter": 0.8,
+          "drill": 0.4
+        },
+        {
+          "diameter": 1.0,
+          "drill": 0.5
        }
      ],
      "zones_allow_external_fillets": false,
      "zones_use_no_outline": true
    },
-    "layer_presets": []
+    "ipc2581": {
+      "dist": "",
+      "distpn": "",
+      "internal_id": "",
+      "mfg": "",
+      "mpn": ""
+    },
+    "layer_presets": [],
+    "viewports": []
  },
  "boards": [],
  "cvpcb": {
@ -314,18 +433,23 @@
    "rule_severities": {
      "bus_definition_conflict": "error",
      "bus_entry_needed": "error",
-      "bus_label_syntax": "error",
      "bus_to_bus_conflict": "error",
      "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
      "different_unit_footprint": "error",
      "different_unit_net": "error",
      "duplicate_reference": "error",
      "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
      "extra_units": "error",
      "global_label_dangling": "warning",
      "hier_label_mismatch": "error",
      "label_dangling": "error",
      "lib_symbol_issues": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
      "multiple_net_names": "warning",
      "net_not_bus_member": "warning",
      "no_connect_connected": "warning",
@ -335,6 +459,7 @@
      "pin_to_pin": "warning",
      "power_pin_not_driven": "error",
      "similar_labels": "warning",
+      "simulation_model_issue": "error",
      "unannotated": "error",
      "unit_value_mismatch": "error",
      "unresolved_variable": "error",
@ -352,7 +477,7 @@
  "net_settings": {
    "classes": [
      {
-        "bus_width": 12.0,
+        "bus_width": 12,
        "clearance": 0.2,
        "diff_pair_gap": 0.25,
        "diff_pair_via_gap": 0.25,
@ -366,10 +491,10 @@
        "track_width": 0.2,
        "via_diameter": 0.6,
        "via_drill": 0.3,
-        "wire_width": 6.0
+        "wire_width": 6
      },
      {
-        "bus_width": 12.0,
+        "bus_width": 12,
        "clearance": 0.2,
        "diff_pair_gap": 0.25,
        "diff_pair_via_gap": 0.25,
@ -378,16 +503,15 @@
        "microvia_diameter": 0.3,
        "microvia_drill": 0.1,
        "name": "Thick",
-        "nets": [],
        "pcb_color": "rgba(0, 0, 0, 0.000)",
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.5,
        "via_diameter": 0.8,
        "via_drill": 0.4,
-        "wire_width": 6.0
+        "wire_width": 6
      },
      {
-        "bus_width": 12.0,
+        "bus_width": 12,
        "clearance": 0.15,
        "diff_pair_gap": 0.25,
        "diff_pair_via_gap": 0.25,
@ -396,34 +520,98 @@
        "microvia_diameter": 0.3,
        "microvia_drill": 0.1,
        "name": "Thin",
-        "nets": [],
        "pcb_color": "rgba(0, 0, 0, 0.000)",
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.15,
        "via_diameter": 0.5,
        "via_drill": 0.3,
-        "wire_width": 6.0
+        "wire_width": 6
      }
    ],
    "meta": {
-      "version": 2
+      "version": 3
    },
-    "net_colors": null
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
  },
  "pcbnew": {
    "last_paths": {
      "gencad": "",
      "idf": "",
      "netlist": "",
+      "plot": "",
+      "pos_files": "",
      "specctra_dsn": "",
      "step": "",
+      "svg": "",
      "vrml": ""
    },
    "page_layout_descr_file": ""
  },
  "schematic": {
    "annotate_start_num": 0,
+    "bom_fmt_presets": [],
+    "bom_fmt_settings": {
+      "field_delimiter": ",",
+      "keep_line_breaks": false,
+      "keep_tabs": false,
+      "name": "CSV",
+      "ref_delimiter": ",",
+      "ref_range_delimiter": "",
+      "string_delimiter": "\""
+    },
+    "bom_presets": [],
+    "bom_settings": {
+      "exclude_dnp": false,
+      "fields_ordered": [
+        {
+          "group_by": false,
+          "label": "Reference",
+          "name": "Reference",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Value",
+          "name": "Value",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Datasheet",
+          "name": "Datasheet",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Footprint",
+          "name": "Footprint",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Qty",
+          "name": "${QUANTITY}",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "DNP",
+          "name": "${DNP}",
+          "show": true
+        }
+      ],
+      "filter_string": "",
+      "group_symbols": true,
+      "name": "Grouped By Value",
+      "sort_asc": true,
+      "sort_field": "Reference"
+    },
+    "connection_grid_size": 50.0,
    "drawing": {
+      "dashed_lines_dash_length_ratio": 12.0,
+      "dashed_lines_gap_length_ratio": 3.0,
      "default_line_thickness": 6.0,
      "default_text_size": 50.0,
      "field_names": [],
@ -434,6 +622,11 @@
      "intersheets_ref_suffix": "",
      "junction_size_choice": 3,
      "label_size_ratio": 0.375,
+      "operating_point_overlay_i_precision": 3,
+      "operating_point_overlay_i_range": "~A",
+      "operating_point_overlay_v_precision": 3,
+      "operating_point_overlay_v_range": "~V",
+      "overbar_offset_ratio": 1.23,
      "pin_symbol_size": 25.0,
      "text_offset_ratio": 0.15
    },
@ -455,14 +648,19 @@
    "page_layout_descr_file": "",
    "plot_directory": "",
    "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
    "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_dissipations": false,
+    "spice_save_all_voltages": false,
    "subpart_first_id": 65,
    "subpart_id_separator": 0
  },
  "sheets": [
    [
      "43fc3289-82a7-492c-a423-3030e10115dc",
-      ""
+      "Root"
    ]
  ],
  "text_variables": {}
--- a/template.kicad_sch
+++ b/template.kicad_sch
@ -1,22 +1,20 @@
-(kicad_sch (version 20211123) (generator eeschema)
-
-  (uuid 43fc3289-82a7-492c-a423-3030e10115dc)
-
-  (paper "A4")
-
-  (title_block
-    (date "$date$")
-    (rev "$version$.$revision$")
-    (company "CuVoodoo")
-    (comment 1 "King Kévin")
-    (comment 2 "CERN-OHL-S")
-  )
-
-  (lib_symbols
-  )
-
-
-  (sheet_instances
-    (path "/" (page "1"))
-  )
-)
+(kicad_sch
+	(version 20231120)
+	(generator "eeschema")
+	(generator_version "8.0")
+	(uuid "43fc3289-82a7-492c-a423-3030e10115dc")
+	(paper "A4")
+	(title_block
+		(date "$date$")
+		(rev "$version$.$revision$")
+		(company "CuVoodoo")
+		(comment 1 "King Kévin")
+		(comment 2 "CERN-OHL-S")
+	)
+	(lib_symbols)
+	(sheet_instances
+		(path "/"
+			(page "1")
+		)
+	)
+)
Author	SHA1	Message	Date
King Kévin	a8810edd3b	make: improve panelization	2024-04-27 10:40:12 +02:00
King Kévin	0038c3bdf3	lib: update repo	2024-04-19 04:20:05 +02:00
King Kévin	209b5852e0	brd: add contraints and predefined sizes	2024-04-19 04:18:14 +02:00
King Kévin	870be28af6	sch/brd: save as KiCAD v8	2024-04-19 04:01:49 +02:00
King Kévin	bf94fcb10c	make: fix clean	2024-04-19 04:00:26 +02:00
King Kévin	6823a71175	doc: update dev notes to KiCAD v8	2024-04-19 04:00:26 +02:00
King Kévin	9b8c48a33c	make: add svg render	2024-04-19 04:00:26 +02:00
King Kévin	2497f9d94b	make: use ibom from kicad8	2024-04-19 04:00:26 +02:00
King Kévin	88deb003a6	lib: update repo	2024-03-18 23:44:10 +01:00
King Kévin	529880abb4	make dragon kicad compatible	2024-03-18 23:43:19 +01:00
King Kévin	fa16059e46	add old and new year logo	2024-03-08 07:24:21 +01:00
King Kévin	200f8b179d	make: remove components from 2d rendering	2024-03-08 07:14:50 +01:00
King Kévin	07570f2911	make: update bom tool	2024-03-08 07:14:21 +01:00
King Kévin	0830600044	make: include DNF parts	2024-03-08 07:14:21 +01:00
King Kévin	3933cbccf8	make: export 3d model	2024-03-08 07:14:21 +01:00
King Kévin	89b65b72de	make: add MPN in BoM	2024-03-08 07:13:47 +01:00
King Kévin	9e186892e5	make: ignore DRC	2024-03-08 07:12:31 +01:00
King Kévin	ddf9deb7fc	lib: update repo	2024-03-08 07:07:09 +01:00
King Kévin	0d73e5171d	remove refdes2fab.py and this is a just a gloabal plugin for me	2023-12-18 20:47:12 +01:00
King Kévin	3e78d6beb5	lib: update logo properties	2023-10-01 10:12:16 +02:00
King Kévin	c133c944de	lib: add silk logo (less DRC errors)	2023-10-01 10:12:16 +02:00
King Kévin	16b19cc0d4	lib: update repo	2023-10-01 10:09:52 +02:00
King Kévin	7310a8173a	lib: update repo	2023-09-19 05:12:28 +02:00
King Kévin	e97b5bf01f	lib: update part database	2023-09-19 05:11:40 +02:00
King Kévin	4aef742dc5	lib: generate Kicad7 library	2023-09-19 05:11:17 +02:00
King Kévin	f84deb30b8	lib: remove JLCPCB correction info as it is in the database now	2023-09-19 05:10:41 +02:00
King Kévin	50444cd555	bom: ignore some fields	2023-08-11 11:06:14 +02:00
King Kévin	cedd9571ee	lib: update repo	2023-08-11 11:05:29 +02:00
King Kévin	7ba4b33939	make: use JLCPCB field in bom fabrication export	2023-08-11 11:04:37 +02:00
King Kévin	6fe5a0e425	make: prevent bom backup	2023-08-11 11:04:37 +02:00
King Kévin	6eb31f0646	ignore kicad lock files	2023-08-11 11:04:37 +02:00
King Kévin	b893e7b57d	make: ignore DRC for export	2023-08-11 11:04:37 +02:00
King Kévin	ffbdffdf48	kicad: update files to v7	2023-03-30 22:32:40 +02:00
King Kévin	59b145d66e	doc: better list dependencies	2023-03-30 22:30:26 +02:00
King Kévin	c63fbf1689	make: use kikit again to generate fabrication	2023-03-30 22:30:26 +02:00
King Kévin	d0d4203d20	make: add bom generator (not included in pip)	2023-03-30 22:30:26 +02:00
King Kévin	cacdcb4ceb	make: update bom generation	2023-03-30 22:30:26 +02:00
King Kévin	87cb8cb49b	make: now use ibom plugin	2023-03-30 22:30:26 +02:00
King Kévin	99ab15f5eb	make: switch back from kicad nightly	2023-03-30 22:30:26 +02:00
King Kévin	253f301eb0	lib: update database	2023-03-30 22:30:26 +02:00
King Kévin	f1227afdcb	make: fabrication does not need schematic	2023-03-30 22:30:26 +02:00
King Kévin	33f9b2cb87	make: add subsheet support	2023-03-30 22:29:07 +02:00
King Kévin	8fa5152b25	make: use kicad-cli to export fabrication (kikit does not support v7 yet)	2023-03-30 22:26:57 +02:00
King Kévin	b066d8b473	make: update pcbdraw call	2023-03-30 22:26:57 +02:00
King Kévin	d6ed8e8f86	make: use kicad-cli to generate bom	2023-03-30 22:26:57 +02:00
King Kévin	ad93fccfcd	make: use kicad-cli to render schematic	2023-03-30 22:26:54 +02:00
King Kévin	5849e04d54	lib: update partdb library	2023-03-30 22:25:49 +02:00
King Kévin	0b268fef02	lib: add logos	2023-03-30 22:25:49 +02:00
King Kévin	cf6e95493f	lib: switch kicad footprint to v7	2023-03-30 22:25:49 +02:00
King Kévin	58e504ea47	lib: disable qeda pin shapes	2023-03-30 22:23:41 +02:00
King Kévin	87819cd3e6	lib: add partdb library	2023-03-30 22:23:41 +02:00
King Kévin	5d9a596047	lib: enable audio connector library	2023-03-30 22:23:41 +02:00
King Kévin	8992163da1	lib: switch to version 7	2023-03-30 22:23:41 +02:00
King Kévin	4e8d15f64c	sch: set kicad6 library	2022-12-24 03:09:46 +01:00
King Kévin	9b313a227c	lib: update repo	2022-12-24 03:08:33 +01:00
King Kévin	283b18e1e9	lib: switch output to KiCad 6	2022-12-24 03:08:20 +01:00
King Kévin	9490a25e50	lib: add JLCPCB corrections for USB connectors	2022-12-24 03:05:45 +01:00
King Kévin	f69a88300f	brd: add material propertires	2022-09-13 12:19:22 +02:00
King Kévin	f558b68515	add script to put refdes in fab layer	2022-09-13 12:14:21 +02:00
King Kévin	b612622310	make: specify ibom generator	2022-08-10 17:43:30 +02:00
King Kévin	c3ce63cbcd	make: output iteractive bom	2022-08-10 14:45:31 +02:00
King Kévin	1d561046dd	doc: add JLCPCB position correction	2022-08-10 12:39:29 +02:00
King Kévin	4636a6508b	doc: replace rake with make	2022-08-10 12:37:46 +02:00
King Kévin	e787a3412e	add parts placement corrections	2022-07-13 11:10:43 +02:00
King Kévin	dc767e3e37	make: output panel fab sooner	2022-07-13 11:10:21 +02:00
King Kévin	ac4807e5ac	make: remove git hash from revision	2022-07-04 10:17:51 +02:00