kicad: update files to v7
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@ -1,4 +1,4 @@
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(kicad_pcb (version 20211014) (generator pcbnew)
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(kicad_pcb (version 20221018) (generator pcbnew)
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(general
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(thickness 1.6)
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@ -44,14 +44,15 @@
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(pad_to_mask_clearance 0)
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(pcbplotparams
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(layerselection 0x00010fc_ffffffff)
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(plot_on_all_layers_selection 0x0000000_00000000)
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(disableapertmacros false)
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(usegerberextensions false)
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(usegerberattributes true)
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(usegerberadvancedattributes true)
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(creategerberjobfile true)
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(svguseinch false)
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(dashed_line_dash_ratio 12.000000)
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(dashed_line_gap_ratio 3.000000)
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(svgprecision 6)
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(excludeedgelayer true)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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@ -1,5 +1,6 @@
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{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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@ -130,7 +131,8 @@
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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"layer_presets": []
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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@ -314,18 +316,23 @@
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"conflicting_netclasses": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"missing_bidi_pin": "warning",
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"missing_input_pin": "warning",
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"missing_power_pin": "error",
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"missing_unit": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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@ -335,6 +342,7 @@
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"simulation_model_issue": "error",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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@ -352,7 +360,7 @@
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"net_settings": {
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"classes": [
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@ -366,10 +374,10 @@
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6.0
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"wire_width": 6
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},
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@ -378,16 +386,15 @@
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Thick",
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"nets": [],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.5,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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"wire_width": 6
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},
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.15,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@ -396,19 +403,20 @@
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Thin",
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"nets": [],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.15,
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"via_diameter": 0.5,
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"via_drill": 0.3,
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"wire_width": 6.0
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"wire_width": 6
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}
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],
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"meta": {
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"version": 2
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"version": 3
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},
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"net_colors": null
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": []
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},
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"pcbnew": {
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"last_paths": {
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@ -424,6 +432,8 @@
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"schematic": {
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"annotate_start_num": 0,
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_line_thickness": 6.0,
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"default_text_size": 50.0,
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"field_names": [],
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@ -455,7 +465,11 @@
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"page_layout_descr_file": "",
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"plot_directory": "",
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"spice_adjust_passive_values": false,
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"spice_current_sheet_as_root": false,
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"spice_external_command": "spice \"%I\"",
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"spice_model_current_sheet_as_root": true,
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"spice_save_all_currents": false,
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"spice_save_all_voltages": false,
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"subpart_first_id": 65,
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"subpart_id_separator": 0
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},
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@ -1,4 +1,4 @@
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(kicad_sch (version 20211123) (generator eeschema)
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(kicad_sch (version 20230121) (generator eeschema)
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(uuid 43fc3289-82a7-492c-a423-3030e10115dc)
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