i2c_master: make error checking simpler
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parent
a7af5896a6
commit
3afd4eac87
31
i2c_master.c
31
i2c_master.c
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@ -94,7 +94,7 @@ enum i2c_master_rc i2c_master_start(void)
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I2C_SR2 = 0; // clear error flags
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I2C_SR2 = 0; // clear error flags
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rim(); // enable interrupts
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rim(); // enable interrupts
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while ((I2C_CR2 & I2C_CR2_START) || !(I2C_SR1 & I2C_SR1_SB) || !(I2C_SR3 & I2C_SR3_MSL)) { // wait until start condition has been accepted, send, and we are in aster mode
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while ((I2C_CR2 & I2C_CR2_START) || !(I2C_SR1 & I2C_SR1_SB) || !(I2C_SR3 & I2C_SR3_MSL)) { // wait until start condition has been accepted, send, and we are in aster mode
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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if (I2C_SR2) {
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return I2C_MASTER_RC_BUS_ERROR;
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return I2C_MASTER_RC_BUS_ERROR;
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}
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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if (I2C_CR2 & I2C_CR2_STOP) {
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@ -114,7 +114,7 @@ static enum i2c_master_rc i2c_master_wait_stop(void)
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{
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{
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I2C_SR2 = 0; // clear error flags
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I2C_SR2 = 0; // clear error flags
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while (I2C_CR2 & I2C_CR2_STOP) { // wait until stop condition is accepted and cleared
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while (I2C_CR2 & I2C_CR2_STOP) { // wait until stop condition is accepted and cleared
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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if (I2C_SR2) {
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return I2C_MASTER_RC_BUS_ERROR;
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return I2C_MASTER_RC_BUS_ERROR;
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}
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}
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// there is no interrupt flag we can use here
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// there is no interrupt flag we can use here
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@ -168,14 +168,13 @@ enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, b
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I2C_SR2 = 0; // clear error flags
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I2C_SR2 = 0; // clear error flags
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rim(); // enable interrupts
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rim(); // enable interrupts
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while (!(I2C_SR1 & I2C_SR1_ADDR)) { // wait until address is transmitted (or error)
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while (!(I2C_SR1 & I2C_SR1_ADDR)) { // wait until address is transmitted (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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return I2C_MASTER_RC_TIMEOUT;
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}
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}
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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return I2C_MASTER_RC_NAK;
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} else if (I2C_SR2) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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}
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I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts
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I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts
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wfi(); // got to sleep to prevent EMI causing glitches
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wfi(); // got to sleep to prevent EMI causing glitches
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@ -186,14 +185,13 @@ enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, b
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I2C_SR2 = 0; // clear error flags
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I2C_SR2 = 0; // clear error flags
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rim(); // enable interrupts
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rim(); // enable interrupts
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while (!(I2C_SR1 & I2C_SR1_ADD10)) { // wait until address is transmitted (or error)
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while (!(I2C_SR1 & I2C_SR1_ADD10)) { // wait until address is transmitted (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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return I2C_MASTER_RC_TIMEOUT;
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}
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}
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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return I2C_MASTER_RC_NAK;
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} else if (I2C_SR2) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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}
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I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts
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I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts
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wfi(); // got to sleep to prevent EMI causing glitches
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wfi(); // got to sleep to prevent EMI causing glitches
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@ -204,14 +202,13 @@ enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, b
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I2C_SR2 = 0; // clear error flags
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I2C_SR2 = 0; // clear error flags
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rim(); // enable interrupts
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rim(); // enable interrupts
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while (!(I2C_SR1 & I2C_SR1_ADDR)) { // wait until address is transmitted (or error)
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while (!(I2C_SR1 & I2C_SR1_ADDR)) { // wait until address is transmitted (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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return I2C_MASTER_RC_TIMEOUT;
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}
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}
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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return I2C_MASTER_RC_NAK;
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} else if (I2C_SR2) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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}
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I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts
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I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts
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wfi(); // got to sleep to prevent EMI causing glitches
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wfi(); // got to sleep to prevent EMI causing glitches
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@ -227,14 +224,13 @@ enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, b
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I2C_DR = 11110001 | (((slave >> 8) & 0x3) << 1); // send header (11110xx1, where xx are 2 MSb of slave address)
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I2C_DR = 11110001 | (((slave >> 8) & 0x3) << 1); // send header (11110xx1, where xx are 2 MSb of slave address)
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I2C_SR2 = 0; // clear error flags
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I2C_SR2 = 0; // clear error flags
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while (!(I2C_SR1 & I2C_SR1_ADDR)) { // wait until address is transmitted (or error)
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while (!(I2C_SR1 & I2C_SR1_ADDR)) { // wait until address is transmitted (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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return I2C_MASTER_RC_TIMEOUT;
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}
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}
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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if (I2C_SR2 & I2C_SR2_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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return I2C_MASTER_RC_NAK;
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} else if (I2C_SR2) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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}
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I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts
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I2C_ITR = (I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable relevant I²C interrupts
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wfi(); // got to sleep to prevent EMI causing glitches
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wfi(); // got to sleep to prevent EMI causing glitches
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@ -278,7 +274,7 @@ enum i2c_master_rc i2c_master_read(uint8_t* data, uint16_t data_size)
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}
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}
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rim(); // enable interrupts
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rim(); // enable interrupts
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while (!(I2C_SR1 & I2C_SR1_RXNE)) { // wait until data is received (or error)
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while (!(I2C_SR1 & I2C_SR1_RXNE)) { // wait until data is received (or error)
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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if (I2C_SR2) { // an error occurred
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return I2C_MASTER_RC_BUS_ERROR;
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return I2C_MASTER_RC_BUS_ERROR;
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}
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}
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I2C_ITR = (I2C_ITR_ITBUFEN | I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable all I²C interrupts
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I2C_ITR = (I2C_ITR_ITBUFEN | I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable all I²C interrupts
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@ -312,14 +308,13 @@ enum i2c_master_rc i2c_master_write(const uint8_t* data, uint16_t data_size)
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rim(); // enable interrupts
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rim(); // enable interrupts
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while (!(I2C_SR1 & I2C_SR1_TXE)) { // wait until byte has been transmitted
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while (!(I2C_SR1 & I2C_SR1_TXE)) { // wait until byte has been transmitted
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IWDG->KR.fields.KEY = IWDG_KR_KEY_REFRESH; // reset watchdog
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IWDG->KR.fields.KEY = IWDG_KR_KEY_REFRESH; // reset watchdog
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if (I2C_SR2 & (I2C_SR2_BERR | I2C_SR2_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_CR2 & I2C_CR2_STOP) {
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if (I2C_CR2 & I2C_CR2_STOP) {
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return I2C_MASTER_RC_TIMEOUT;
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return I2C_MASTER_RC_TIMEOUT;
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}
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}
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if (I2C_SR2 & I2C_SR2_AF) { // data has not been acknowledged
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if (I2C_SR2 & I2C_SR2_AF) { // data has not been acknowledged
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return I2C_MASTER_RC_NAK;
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return I2C_MASTER_RC_NAK;
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} else if (I2C_SR2) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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}
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I2C_ITR = (I2C_ITR_ITBUFEN | I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable all I²C interrupts
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I2C_ITR = (I2C_ITR_ITBUFEN | I2C_ITR_ITEVTEN | I2C_ITR_ITERREN); // enable all I²C interrupts
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wfi(); // got to sleep to prevent EMI causing glitches
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wfi(); // got to sleep to prevent EMI causing glitches
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