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I2C (minor): add space around operators for readability

This commit is contained in:
King Kévin 2019-03-26 18:25:23 +01:00
parent a50a181b86
commit 62b83fd34d
1 changed files with 68 additions and 68 deletions
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136
lib/i2c_master.c
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@ -174,7 +174,7 @@ static uint32_t GPIO_PIN_SDA(uint32_t i2c)
void i2c_master_setup(uint32_t i2c, uint16_t frequency) void i2c_master_setup(uint32_t i2c, uint16_t frequency)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
@ -193,18 +193,18 @@ void i2c_master_setup(uint32_t i2c, uint16_t frequency)
I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // clear peripheral reset I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // clear peripheral reset
if (0==frequency) { // don't allow null frequency if (0==frequency) { // don't allow null frequency
frequency = 1; frequency = 1;
} else if (frequency>400) { // limit frequency to 400 kHz } else if (frequency > 400) { // limit frequency to 400 kHz
frequency = 400; frequency = 400;
} }
i2c_set_clock_frequency(i2c, rcc_apb1_frequency/1000000); // configure the peripheral clock to the APB1 freq (where it is connected to) i2c_set_clock_frequency(i2c, rcc_apb1_frequency / 1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
if (frequency>100) { // use fast mode for frequencies over 100 kHz if (frequency>100) { // use fast mode for frequencies over 100 kHz
i2c_set_fast_mode(i2c); // set fast mode (Fm) i2c_set_fast_mode(i2c); // set fast mode (Fm)
i2c_set_ccr(i2c, rcc_apb1_frequency/(frequency*1000*2)); // set Thigh/Tlow to generate frequency (fast duty not used) i2c_set_ccr(i2c, rcc_apb1_frequency / (frequency * 1000 * 2)); // set Thigh/Tlow to generate frequency (fast duty not used)
i2c_set_trise(i2c, (300/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for Fm mode (< 400) kHz is 300 ns i2c_set_trise(i2c, (300 / (1000 / (rcc_apb1_frequency / 1000000))) + 1); // max rise time for Fm mode (< 400) kHz is 300 ns
} else { // use fast mode for frequencies below 100 kHz } else { // use fast mode for frequencies below 100 kHz
i2c_set_standard_mode(i2c); // set standard mode (Sm) i2c_set_standard_mode(i2c); // set standard mode (Sm)
i2c_set_ccr(i2c, rcc_apb1_frequency/(frequency*1000*2)); // set Thigh/Tlow to generate frequency of 100 kHz i2c_set_ccr(i2c, rcc_apb1_frequency / (frequency * 1000 * 2)); // set Thigh/Tlow to generate frequency of 100 kHz
i2c_set_trise(i2c, (1000/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for Sm mode (< 100 kHz) is 1000 ns (~1 MHz) i2c_set_trise(i2c, (1000 / (1000 / (rcc_apb1_frequency / 1000000))) + 1); // max rise time for Sm mode (< 100 kHz) is 1000 ns (~1 MHz)
} }
i2c_peripheral_enable(i2c); // enable I2C after configuration completed i2c_peripheral_enable(i2c); // enable I2C after configuration completed
} }
@ -212,7 +212,7 @@ void i2c_master_setup(uint32_t i2c, uint16_t frequency)
void i2c_master_release(uint32_t i2c) void i2c_master_release(uint32_t i2c)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
@ -226,7 +226,7 @@ void i2c_master_release(uint32_t i2c)
bool i2c_master_check_signals(uint32_t i2c) bool i2c_master_check_signals(uint32_t i2c)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
@ -241,7 +241,7 @@ bool i2c_master_check_signals(uint32_t i2c)
gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_PIN_SCL(i2c)); // configure signal as pull down gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_PIN_SCL(i2c)); // configure signal as pull down
gpio_clear(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // pull down gpio_clear(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // pull down
gpio_clear(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // pull down gpio_clear(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // pull down
bool to_return = (0!=gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)) && 0!=gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // check if the signals are still pulled high by external stronger pull-up resistors bool to_return = (0 != gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)) && 0 != gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // check if the signals are still pulled high by external stronger pull-up resistors
GPIO_CRL(GPIO_PORT_SDA(i2c)) = sda_crl; // restore port configuration GPIO_CRL(GPIO_PORT_SDA(i2c)) = sda_crl; // restore port configuration
GPIO_CRH(GPIO_PORT_SDA(i2c)) = sda_crh; // restore port configuration GPIO_CRH(GPIO_PORT_SDA(i2c)) = sda_crh; // restore port configuration
GPIO_BSRR(GPIO_PORT_SDA(i2c)) = sda_bsrr; // restore port configuration GPIO_BSRR(GPIO_PORT_SDA(i2c)) = sda_bsrr; // restore port configuration
@ -255,7 +255,7 @@ bool i2c_master_check_signals(uint32_t i2c)
bool i2c_master_reset(uint32_t i2c) bool i2c_master_reset(uint32_t i2c)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
@ -288,7 +288,7 @@ bool i2c_master_reset(uint32_t i2c)
enum i2c_master_rc i2c_master_start(uint32_t i2c) enum i2c_master_rc i2c_master_start(uint32_t i2c)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
@ -297,7 +297,7 @@ enum i2c_master_rc i2c_master_start(uint32_t i2c)
try: try:
to_return = I2C_MASTER_RC_NONE; // return code to_return = I2C_MASTER_RC_NONE; // return code
// send (re-)start condition // send (re-)start condition
if (I2C_CR1(i2c) & (I2C_CR1_START|I2C_CR1_STOP)) { // ensure start or stop operations are not in progress if (I2C_CR1(i2c) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
return I2C_MASTER_RC_START_STOP_IN_PROGESS; return I2C_MASTER_RC_START_STOP_IN_PROGESS;
} }
// prepare timer in case the peripheral hangs on sending stop condition (see errata 2.14.4 Wrong behavior of I2C peripheral in master mode after a misplaced Stop) // prepare timer in case the peripheral hangs on sending stop condition (see errata 2.14.4 Wrong behavior of I2C peripheral in master mode after a misplaced Stop)
@ -309,13 +309,13 @@ try:
i2c_send_start(i2c); // send start condition to start transaction i2c_send_start(i2c); // send start condition to start transaction
bool timeout = false; // remember if the timeout has been reached bool timeout = false; // remember if the timeout has been reached
systick_counter_enable(); // start timer systick_counter_enable(); // start timer
while ((I2C_CR1(i2c) & I2C_CR1_START) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) && !timeout) { // wait until start condition has been accepted and cleared while ((I2C_CR1(i2c) & I2C_CR1_START) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until start condition has been accepted and cleared
timeout |= systick_get_countflag(); // verify if timeout has been reached timeout |= systick_get_countflag(); // verify if timeout has been reached
} }
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) { if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
to_return = I2C_MASTER_RC_BUS_ERROR; to_return = I2C_MASTER_RC_BUS_ERROR;
} }
while (!(I2C_SR1(i2c) & I2C_SR1_SB) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) && !timeout && I2C_MASTER_RC_NONE == to_return) { // wait until start condition is transmitted while (!(I2C_SR1(i2c) & I2C_SR1_SB) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout && I2C_MASTER_RC_NONE == to_return) { // wait until start condition is transmitted
timeout |= systick_get_countflag(); // verify if timeout has been reached timeout |= systick_get_countflag(); // verify if timeout has been reached
} }
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) { if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
@ -348,7 +348,7 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
if (!(I2C_SR1(i2c) & I2C_SR1_SB)) { // start condition has not been sent if (!(I2C_SR1(i2c) & I2C_SR1_SB)) { // start condition has not been sent
rc = i2c_master_start(i2c); // send start condition rc = i2c_master_start(i2c); // send start condition
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
return rc; return rc;
} }
} }
@ -360,8 +360,8 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
if (!address_10bit) { // 7-bit address if (!address_10bit) { // 7-bit address
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
i2c_send_7bit_address(i2c, slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag i2c_send_7bit_address(i2c, slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until address is transmitted while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR | I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until address is transmitted
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) { if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
return I2C_MASTER_RC_BUS_ERROR; return I2C_MASTER_RC_BUS_ERROR;
} }
if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
@ -370,16 +370,16 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
} else { // 10-bit address } else { // 10-bit address
// send first part of address // send first part of address
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
I2C_DR(i2c) = 11110000 | (((slave>>8)&0x3)<<1); // send first header (11110xx0, where xx are 2 MSb of slave address) I2C_DR(i2c) = 11110000 | (((slave >> 8 ) & 0x3) << 1); // send first header (11110xx0, where xx are 2 MSb of slave address)
while (!(I2C_SR1(i2c) & (I2C_SR1_ADD10|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until first part of address is transmitted while (!(I2C_SR1(i2c) & (I2C_SR1_ADD10 | I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until first part of address is transmitted
if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
return I2C_MASTER_RC_NAK; return I2C_MASTER_RC_NAK;
} }
// send second part of address // send second part of address
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
I2C_DR(i2c) = (slave&0xff); // send remaining of address I2C_DR(i2c) = (slave & 0xff); // send remaining of address
while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until remaining part of address is transmitted while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) { if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
return I2C_MASTER_RC_BUS_ERROR; return I2C_MASTER_RC_BUS_ERROR;
} }
if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
@ -388,14 +388,14 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
// go into receive mode if necessary // go into receive mode if necessary
if (!write) { if (!write) {
rc = i2c_master_start(i2c); // send start condition rc = i2c_master_start(i2c); // send start condition
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
return rc; return rc;
} }
// send first part of address with receive flag // send first part of address with receive flag
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
I2C_DR(i2c) = 11110001 | (((slave>>8)&0x3)<<1); // send header (11110xx1, where xx are 2 MSb of slave address) I2C_DR(i2c) = 11110001 | (((slave >> 8) & 0x3) << 1); // send header (11110xx1, where xx are 2 MSb of slave address)
while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until remaining part of address is transmitted while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR | I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) { if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
return I2C_MASTER_RC_BUS_ERROR; return I2C_MASTER_RC_BUS_ERROR;
} }
if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
@ -410,12 +410,12 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size) enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
// sanity check // sanity check
if (data==NULL || data_size==0) { // no data to read if (NULL == data || 0 == data_size) { // no data to read
return I2C_MASTER_RC_NONE; return I2C_MASTER_RC_NONE;
} }
if (1 == data_size) { if (1 == data_size) {
@ -440,7 +440,7 @@ enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size
} }
// read data // read data
for (size_t i=0; i<data_size; i++) { // read bytes for (size_t i = 0; i < data_size; i++) { // read bytes
if (2 == data_size - i) { // prepare to sent NACK for second last byte if (2 == data_size - i) { // prepare to sent NACK for second last byte
i2c_nack_next(i2c); // NACK next byte i2c_nack_next(i2c); // NACK next byte
i2c_disable_ack(i2c); // NACK received to stop slave transmission i2c_disable_ack(i2c); // NACK received to stop slave transmission
@ -450,7 +450,7 @@ enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size
} else { } else {
i2c_enable_ack(i2c); // ACK received byte to continue slave transmission i2c_enable_ack(i2c); // ACK received byte to continue slave transmission
} }
while (!(I2C_SR1(i2c) & I2C_SR1_RxNE) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until byte has been received while (!(I2C_SR1(i2c) & I2C_SR1_RxNE) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been received
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) { if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
return I2C_MASTER_RC_BUS_ERROR; return I2C_MASTER_RC_BUS_ERROR;
} }
@ -463,12 +463,12 @@ enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size
enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size) enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
// sanity check // sanity check
if (data==NULL || data_size==0) { // no data to write if (NULL == data || 0 == data_size) { // no data to write
return I2C_MASTER_RC_NONE; return I2C_MASTER_RC_NONE;
} }
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master
@ -482,11 +482,11 @@ enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t da
} }
// write data // write data
for (size_t i=0; i<data_size; i++) { // write bytes for (size_t i = 0; i < data_size; i++) { // write bytes
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
i2c_send_data(i2c, data[i]); // send byte to be written in memory i2c_send_data(i2c, data[i]); // send byte to be written in memory
while (!(I2C_SR1(i2c) & (I2C_SR1_TxE|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO))); // wait until byte has been transmitted while (!(I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been transmitted
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) { if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
return I2C_MASTER_RC_BUS_ERROR; return I2C_MASTER_RC_BUS_ERROR;
} }
if (I2C_SR1(i2c) & I2C_SR1_AF) { // data has not been acknowledged if (I2C_SR1(i2c) & I2C_SR1_AF) { // data has not been acknowledged
@ -500,7 +500,7 @@ enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t da
enum i2c_master_rc i2c_master_stop(uint32_t i2c) enum i2c_master_rc i2c_master_stop(uint32_t i2c)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
@ -508,7 +508,7 @@ enum i2c_master_rc i2c_master_stop(uint32_t i2c)
if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // release is not busy if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // release is not busy
return I2C_MASTER_RC_NONE; // bus has probably already been released return I2C_MASTER_RC_NONE; // bus has probably already been released
} }
if (I2C_CR1(i2c) & (I2C_CR1_START|I2C_CR1_STOP)) { // ensure start or stop operations are not in progress if (I2C_CR1(i2c) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
return I2C_MASTER_RC_START_STOP_IN_PROGESS; return I2C_MASTER_RC_START_STOP_IN_PROGESS;
} }
@ -527,16 +527,16 @@ enum i2c_master_rc i2c_master_stop(uint32_t i2c)
i2c_send_stop(i2c); // send stop to release bus i2c_send_stop(i2c); // send stop to release bus
systick_counter_enable(); // start timer systick_counter_enable(); // start timer
i2c_send_stop(i2c); // send stop to release bus i2c_send_stop(i2c); // send stop to release bus
while ((I2C_CR1(i2c) & I2C_CR1_STOP) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) && !timeout) { // wait until stop condition is accepted and cleared while ((I2C_CR1(i2c) & I2C_CR1_STOP) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until stop condition is accepted and cleared
timeout |= systick_get_countflag(); // verify if timeout has been reached timeout |= systick_get_countflag(); // verify if timeout has been reached
} }
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) { if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
to_return = I2C_MASTER_RC_BUS_ERROR; to_return = I2C_MASTER_RC_BUS_ERROR;
} }
while ((I2C_SR2(i2c) & I2C_SR2_MSL) && !(I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) && !timeout) { // wait until bus released (non master mode) while ((I2C_SR2(i2c) & I2C_SR2_MSL) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until bus released (non master mode)
timeout |= systick_get_countflag(); // verify if timeout has been reached timeout |= systick_get_countflag(); // verify if timeout has been reached
} }
if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) { if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
to_return = I2C_MASTER_RC_BUS_ERROR; to_return = I2C_MASTER_RC_BUS_ERROR;
} }
@ -551,7 +551,7 @@ enum i2c_master_rc i2c_master_stop(uint32_t i2c)
enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size) enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
@ -561,12 +561,12 @@ enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool addr
return rc; return rc;
} }
rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
if (NULL!=data && data_size>0) { // only read data if needed if (NULL != data && data_size > 0) { // only read data if needed
rc = i2c_master_read(i2c, data, data_size); rc = i2c_master_read(i2c, data, data_size);
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
} }
@ -580,22 +580,22 @@ error:
enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size) enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
rc = i2c_master_start(i2c); // send (re-)start condition rc = i2c_master_start(i2c); // send (re-)start condition
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
return rc; return rc;
} }
rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
if (NULL!=data && data_size>0) { // write data only is some is available if (NULL != data && data_size > 0) { // write data only is some is available
rc = i2c_master_write(i2c, data, data_size); // write data rc = i2c_master_write(i2c, data, data_size); // write data
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
} }
@ -609,39 +609,39 @@ error:
enum i2c_master_rc i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size) enum i2c_master_rc i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
rc = i2c_master_start(i2c); // send (re-)start condition rc = i2c_master_start(i2c); // send (re-)start condition
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
return rc; return rc;
} }
rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
// write address // write address
if (NULL!=address && address_size>0) { if (NULL != address && address_size > 0) {
rc = i2c_master_write(i2c, address, address_size); // send memory address rc = i2c_master_write(i2c, address, address_size); // send memory address
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
} }
// read data // read data
if (NULL!=data && data_size>0) { if (NULL != data && data_size > 0) {
rc = i2c_master_start(i2c); // send re-start condition rc = i2c_master_start(i2c); // send re-start condition
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
return rc; return rc;
} }
rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
rc = i2c_master_read(i2c, data, data_size); // read memory rc = i2c_master_read(i2c, data, data_size); // read memory
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
} }
@ -655,31 +655,31 @@ error:
enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size) enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
{ {
// check I2C peripheral // check I2C peripheral
if (I2C1!=i2c && I2C2!=i2c) { if (I2C1 != i2c && I2C2 != i2c) {
while (true); while (true);
} }
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
rc = i2c_master_start(i2c); // send (re-)start condition rc = i2c_master_start(i2c); // send (re-)start condition
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
return rc; return rc;
} }
rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
// write address // write address
if (NULL!=address && address_size>0) { if (NULL != address && address_size > 0) {
rc = i2c_master_write(i2c, address, address_size); // send memory address rc = i2c_master_write(i2c, address, address_size); // send memory address
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
} }
// read data // read data
if (NULL!=data && data_size>0) { if (NULL != data && data_size > 0) {
rc = i2c_master_write(i2c, data, data_size); // write memory rc = i2c_master_write(i2c, data, data_size); // write memory
if (I2C_MASTER_RC_NONE!=rc) { if (I2C_MASTER_RC_NONE != rc) {
goto error; goto error;
} }
} }