i2c_master: improve sending stop and integrated it into read function
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parent
f1168608c7
commit
29226246f6
129
lib/i2c_master.c
129
lib/i2c_master.c
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@ -345,6 +345,76 @@ try:
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return to_return;
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}
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/** wait until stop is sent and bus is released
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* @param[in] i2c I²C base address
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* @return I²C return code
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*/
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static enum i2c_master_rc i2c_master_wait_stop(uint32_t i2c)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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enum i2c_master_rc to_return = I2C_MASTER_RC_NONE; // return code
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// prepare timer in case the peripheral hangs on sending stop condition (see errata 2.14.4 Wrong behavior of I²C peripheral in master mode after a misplaced Stop)
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systick_counter_disable(); // disable SysTick to reconfigure it
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systick_set_frequency(500, rcc_ahb_frequency); // set timer to 2 ms (that should be long enough to send a stop condition)
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systick_clear(); // reset SysTick (set to 0)
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systick_interrupt_disable(); // disable interrupt to prevent ISR to read the flag
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systick_get_countflag(); // reset flag (set when counter is going for 1 to 0)
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bool timeout = false; // remember if the timeout has been reached
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systick_counter_enable(); // start timer
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while ((I2C_CR1(i2c) & I2C_CR1_STOP) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until stop condition is accepted and cleared
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = I2C_MASTER_RC_BUS_ERROR;
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}
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while ((I2C_SR2(i2c) & I2C_SR2_MSL) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until bus released (non master mode)
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = I2C_MASTER_RC_BUS_ERROR;
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}
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while ((I2C_SR2(i2c) & I2C_SR2_BUSY) && !(I2C_SR1(i2c) & (I2C_SR1_BERR)) && !timeout) { // wait until peripheral is not busy anymore
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = I2C_MASTER_RC_BUS_ERROR;
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}
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while ((0 == gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)) || 0 == gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))) && !timeout) { // wait until lines are really high again
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (timeout) { // I2C_CR1_STOP could also be used to detect a timeout, but I'm not sure when
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if (I2C_MASTER_RC_NONE == to_return) {
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to_return = I2C_MASTER_RC_TIMEOUT; // indicate timeout only when no more specific error has occurred
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}
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I2C_CR1(i2c) |= I2C_CR1_SWRST; // assert peripheral reset
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I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // release peripheral reset
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}
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systick_counter_disable(); // we don't need to timer anymore
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return to_return;
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}
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enum i2c_master_rc i2c_master_stop(uint32_t i2c)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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// sanity check
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if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // release is not busy
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return I2C_MASTER_RC_NONE; // bus has probably already been released
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}
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if (I2C_CR1(i2c) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
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return I2C_MASTER_RC_START_STOP_IN_PROGESS;
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}
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if (!((I2C_SR2(i2c) & I2C_SR2_TRA))) { // if we are in receiver mode
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i2c_disable_ack(i2c); // disable ACK to be able to close the communication
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}
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i2c_send_stop(i2c); // send stop to release bus
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return i2c_master_wait_stop(i2c);
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}
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enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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@ -467,7 +537,7 @@ enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size
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data[i] = i2c_get_data(i2c); // read received byte
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}
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return I2C_MASTER_RC_NONE;
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return i2c_master_wait_stop(i2c);
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}
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enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
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@ -513,54 +583,6 @@ enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t da
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return I2C_MASTER_RC_NONE;
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}
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enum i2c_master_rc i2c_master_stop(uint32_t i2c)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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// sanity check
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if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // release is not busy
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return I2C_MASTER_RC_NONE; // bus has probably already been released
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}
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if (I2C_CR1(i2c) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
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return I2C_MASTER_RC_START_STOP_IN_PROGESS;
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}
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if (!((I2C_SR2(i2c) & I2C_SR2_TRA))) { // if we are in receiver mode
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i2c_disable_ack(i2c); // disable ACK to be able to close the communication
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}
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enum i2c_master_rc to_return = I2C_MASTER_RC_NONE;
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// prepare timer in case the peripheral hangs on sending stop condition (see errata 2.14.4 Wrong behavior of I²C peripheral in master mode after a misplaced Stop)
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systick_counter_disable(); // disable SysTick to reconfigure it
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systick_set_frequency(500, rcc_ahb_frequency); // set timer to 2 ms (that should be long enough to send a stop condition)
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systick_clear(); // reset SysTick (set to 0)
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systick_interrupt_disable(); // disable interrupt to prevent ISR to read the flag
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systick_get_countflag(); // reset flag (set when counter is going for 1 to 0)
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bool timeout = false; // remember if the timeout has been reached
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i2c_send_stop(i2c); // send stop to release bus
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systick_counter_enable(); // start timer
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i2c_send_stop(i2c); // send stop to release bus
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while ((I2C_CR1(i2c) & I2C_CR1_STOP) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until stop condition is accepted and cleared
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = I2C_MASTER_RC_BUS_ERROR;
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}
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while ((I2C_SR2(i2c) & I2C_SR2_MSL) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until bus released (non master mode)
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = I2C_MASTER_RC_BUS_ERROR;
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}
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if (timeout) {
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I2C_CR1(i2c) |= I2C_CR1_SWRST; // assert peripheral reset
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I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // release peripheral reset
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}
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systick_counter_disable(); // we don't need to timer anymore
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return to_return;
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}
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enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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@ -575,15 +597,19 @@ enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool addr
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goto error;
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}
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if (NULL != data && data_size > 0) { // only read data if needed
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rc = i2c_master_read(i2c, data, data_size);
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rc = i2c_master_read(i2c, data, data_size); // read data (includes stop)
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if (I2C_MASTER_RC_NONE != rc) {
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goto error;
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}
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} else {
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i2c_master_stop(i2c); // sent stop condition
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}
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rc = I2C_MASTER_RC_NONE; // all went well
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error:
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if (I2C_MASTER_RC_NONE != rc) {
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i2c_master_stop(i2c); // sent stop condition
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}
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return rc;
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}
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@ -685,8 +711,7 @@ enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool a
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}
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}
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rc = I2C_MASTER_RC_NONE; // all went well
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error:
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i2c_master_stop(i2c); // sent stop condition
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rc = i2c_master_stop(i2c); // sent stop condition
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return rc;
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}
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@ -30,6 +30,8 @@ enum i2c_master_rc {
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I2C_MASTER_RC_NOT_READY, /**< slave is not read (previous operations has been NACKed) */
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I2C_MASTER_RC_NAK, /**< not acknowledge received */
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I2C_MASTER_RC_BUS_ERROR, /**< an error on the I²C bus occurred */
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I2C_MASTER_RC_TIMEOUT, /**< a timeout has occurred because an operation has not completed in the expected time */
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I2C_MASTER_RC_OTHER, /** any other error (does not have to be I²C related) */
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};
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/** setup I²C peripheral
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