83 lines
1.4 KiB
YAML
83 lines
1.4 KiB
YAML
name: SN74HC02
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alias: SN54HC02
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variations: SOIC, SSOP, PDIP, SO, TSSOP, CDIP
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# variant W (ceramic dual flatpack) is too exotic (body goes through the board)
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# there is also a FK (20 pin LCCC) variant, but since the pin 1 is not QFN standard, QEDA does not support it
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description: quadruple 2-input positive-NOR gates
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datasheet: https://www.ti.com/lit/ds/symlink/sn74hc02.pdf
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pinout:
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1:
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1Y: 1
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1A: 2
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1B: 3
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2:
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2Y: 4
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2A: 5
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2B: 6
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3:
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3Y: 10
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3A: 8
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3B: 9
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4:
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4Y: 13
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4A: 11
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4B: 12
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GND: 7
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VCC: 14
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properties:
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power: VCC
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ground: GND
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input: 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B
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output: 1Y, 2Y, 3Y, 4Y
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schematic:
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symbol: ic
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left: 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B
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right: 1Y, 2Y, 3Y, 4Y
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top: VCC
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bottom: GND
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housing@SOIC:
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suffix: D
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outline: JEDEC MS-012 AB
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housing@SSOP:
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suffix: DB
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outline: JEDEC MO-150
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housing@PDIP:
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suffix: N
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outline: JEDEC MS-001 AA
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housing@SO:
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suffix: NS
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pattern: SOP
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leadCount: 14
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pitch: 1.27
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bodyWidth: 5.0-5.6
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bodyLength: 9.9-10.50
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height: 2.0
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leadWidth: 0.31-0.51
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leadLength: 0.55-1.05
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leadHeight: 0.25
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leadSpan: 7.4-8.2
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housing@TSSOP:
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suffix: PW
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outline: JEDEC MO-153 AB-1
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housing@CDIP:
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suffix: J
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pattern: DIP
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leadCount: 14
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pitch: 2.54 # e
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bodyWidth: 6.22-7.19 # B
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bodyLength: 19.15-19.94 # A
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height: 5.08 # C
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leadWidth: 0.36-0.66
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leadLength: 3.3
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leadHeight: 0.2-0.36
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leadSpan: 7.83-7.97
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