name: SN74HC02
alias: SN54HC02
variations: SOIC, SSOP, PDIP, SO, TSSOP, CDIP 
# variant W (ceramic dual flatpack) is too exotic (body goes through the board)
# there is also a FK (20 pin LCCC) variant, but since the pin 1 is not QFN standard, QEDA does not support it
description: quadruple 2-input positive-NOR gates
datasheet: https://www.ti.com/lit/ds/symlink/sn74hc02.pdf

pinout:
  1:
    1Y: 1
    1A: 2
    1B: 3
  2:
    2Y: 4
    2A: 5
    2B: 6
  3:
    3Y: 10
    3A: 8
    3B: 9
  4:
    4Y: 13
    4A: 11
    4B: 12
  GND: 7
  VCC: 14

properties:
  power: VCC
  ground: GND
  input: 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B
  output: 1Y, 2Y, 3Y, 4Y

schematic:
  symbol: ic
  left: 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B
  right: 1Y, 2Y, 3Y, 4Y
  top: VCC
  bottom: GND

housing@SOIC:
  suffix: D
  outline: JEDEC MS-012 AB

housing@SSOP:
  suffix: DB
  outline: JEDEC MO-150

housing@PDIP:
  suffix: N
  outline: JEDEC MS-001 AA

housing@SO:
  suffix: NS
  pattern: SOP
  leadCount: 14
  pitch: 1.27
  bodyWidth: 5.0-5.6
  bodyLength: 9.9-10.50
  height: 2.0
  leadWidth: 0.31-0.51
  leadLength: 0.55-1.05
  leadHeight: 0.25
  leadSpan: 7.4-8.2

housing@TSSOP:
  suffix: PW
  outline: JEDEC MO-153 AB-1

housing@CDIP:
  suffix: J
  pattern: DIP
  leadCount: 14
  pitch: 2.54 # e
  bodyWidth: 6.22-7.19 # B
  bodyLength: 19.15-19.94 # A
  height: 5.08 # C
  leadWidth: 0.36-0.66
  leadLength: 3.3
  leadHeight: 0.2-0.36
  leadSpan: 7.83-7.97