391 lines
12 KiB
C
391 lines
12 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "sam.h"
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#include "bsp/board_api.h"
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#include "board.h"
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// Suppress warning caused by mcu driver
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#ifdef __GNUC__
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wcast-qual"
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#endif
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#include "hal/include/hal_gpio.h"
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#include "hal/include/hal_init.h"
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#include "hpl/gclk/hpl_gclk_base.h"
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#include "hpl_mclk_config.h"
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#ifdef __GNUC__
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#pragma GCC diagnostic pop
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#endif
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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/* Referenced GCLKs, should be initialized firstly */
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#define _GCLK_INIT_1ST 0xFFFFFFFF
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/* Not referenced GCLKs, initialized last */
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#define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
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//--------------------------------------------------------------------+
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// Forward USB interrupt events to TinyUSB IRQ Handler
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//--------------------------------------------------------------------+
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void USB_0_Handler(void) {
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tud_int_handler(0);
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}
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void USB_1_Handler(void) {
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tud_int_handler(0);
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}
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void USB_2_Handler(void) {
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tud_int_handler(0);
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}
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void USB_3_Handler(void) {
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tud_int_handler(0);
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}
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//--------------------------------------------------------------------+
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// Implementation
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//--------------------------------------------------------------------+
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#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
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#define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
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#define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler)
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static void max3421_init(void);
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#endif
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void board_init(void) {
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// Clock init ( follow hpl_init.c )
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hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, 0);
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_osc32kctrl_init_sources();
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_oscctrl_init_sources();
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_mclk_init();
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#if _GCLK_INIT_1ST
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_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
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#endif
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_oscctrl_init_referenced_generators();
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_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
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// Update SystemCoreClock since it is hard coded with asf4 and not correct
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// Init 1ms tick timer (samd SystemCoreClock may not correct)
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SystemCoreClock = CONF_CPU_FREQUENCY;
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SysTick_Config(CONF_CPU_FREQUENCY / 1000);
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// Led init
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gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
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gpio_set_pin_level(LED_PIN, 0);
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// Button init
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gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
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gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
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#if CFG_TUSB_OS == OPT_OS_FREERTOS
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// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
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NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
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NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
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NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
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NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
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#endif
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/* USB Clock init
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* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
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* for low speed and full speed operation. */
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hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
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hri_mclk_set_AHBMASK_USB_bit(MCLK);
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hri_mclk_set_APBBMASK_USB_bit(MCLK);
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// USB Pin Init
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gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
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gpio_set_pin_level(PIN_PA24, false);
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gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
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gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
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gpio_set_pin_level(PIN_PA25, false);
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gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
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gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
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gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
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#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
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max3421_init();
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#endif
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}
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void board_init_after_tusb(void) {
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}
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//--------------------------------------------------------------------+
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// Board porting API
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//--------------------------------------------------------------------+
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void board_led_write(bool state) {
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gpio_set_pin_level(LED_PIN, state);
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}
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uint32_t board_button_read(void) {
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// button is active low
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return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
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}
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size_t board_get_unique_id(uint8_t id[], size_t max_len) {
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(void) max_len;
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uint32_t did_addr[4] = {0x008061FC, 0x00806010, 0x00806014, 0x00806018};
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for (int i = 0; i < 4; i++) {
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uint32_t did = *((uint32_t const*) did_addr[i]);
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did = TU_BSWAP32(did); // swap endian to match samd51 uf2 bootloader
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memcpy(id + i * 4, &did, 4);
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}
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return 16;
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}
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int board_uart_read(uint8_t* buf, int len) {
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(void) buf;
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(void) len;
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return 0;
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}
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int board_uart_write(void const* buf, int len) {
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(void) buf;
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(void) len;
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return 0;
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}
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#if CFG_TUSB_OS == OPT_OS_NONE
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volatile uint32_t system_ticks = 0;
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void SysTick_Handler(void) {
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system_ticks++;
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}
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uint32_t board_millis(void) {
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return system_ticks;
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}
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#endif
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//--------------------------------------------------------------------+
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// API: SPI transfer with MAX3421E, must be implemented by application
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//--------------------------------------------------------------------+
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#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
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static void max3421_init(void) {
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//------------- SPI Init -------------//
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// MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz
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uint32_t const baudrate = 12000000u;
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struct {
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volatile uint32_t* mck_apb;
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uint32_t mask;
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uint8_t gclk_id_core;
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uint8_t gclk_id_slow;
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} const sercom_clock[] = {
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{ &MCLK->APBAMASK.reg, MCLK_APBAMASK_SERCOM0, SERCOM0_GCLK_ID_CORE, SERCOM0_GCLK_ID_SLOW },
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{ &MCLK->APBAMASK.reg, MCLK_APBAMASK_SERCOM1, SERCOM1_GCLK_ID_CORE, SERCOM1_GCLK_ID_SLOW },
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{ &MCLK->APBBMASK.reg, MCLK_APBBMASK_SERCOM2, SERCOM2_GCLK_ID_CORE, SERCOM2_GCLK_ID_SLOW },
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{ &MCLK->APBBMASK.reg, MCLK_APBBMASK_SERCOM3, SERCOM3_GCLK_ID_CORE, SERCOM3_GCLK_ID_SLOW },
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{ &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM4, SERCOM4_GCLK_ID_CORE, SERCOM4_GCLK_ID_SLOW },
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{ &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM5, SERCOM5_GCLK_ID_CORE, SERCOM5_GCLK_ID_SLOW },
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#ifdef SERCOM6_GCLK_ID_CORE
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{ &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM6, SERCOM6_GCLK_ID_CORE, SERCOM6_GCLK_ID_SLOW },
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#endif
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#ifdef SERCOM7_GCLK_ID_CORE
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{ &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM7, SERCOM7_GCLK_ID_CORE, SERCOM7_GCLK_ID_SLOW },
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#endif
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};
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Sercom* sercom = MAX3421_SERCOM;
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// Enable the APB clock for SERCOM
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*sercom_clock[MAX3421_SERCOM_ID].mck_apb |= sercom_clock[MAX3421_SERCOM_ID].mask;
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// Configure GCLK for SERCOM
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GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg =
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GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
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GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg =
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GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
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// Disable the SPI module
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sercom->SPI.CTRLA.bit.ENABLE = 0;
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// Reset the SPI module
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sercom->SPI.CTRLA.bit.SWRST = 1;
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while (sercom->SPI.SYNCBUSY.bit.SWRST);
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// Set up SPI in master mode, MSB first, SPI mode 0
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sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
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SERCOM_SPI_CTRLA_MODE(3);
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sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
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while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
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// Set the baud rate
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uint8_t baud_reg = (uint8_t) (SystemCoreClock / (2 * baudrate));
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if (baud_reg) {
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baud_reg--;
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}
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sercom->SPI.BAUD.reg = baud_reg;
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// Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
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gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
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gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
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gpio_set_pin_function(MAX3421_SCK_PIN, MAX3421_SERCOM_FUNCTION);
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gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
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gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
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gpio_set_pin_function(MAX3421_MOSI_PIN, MAX3421_SERCOM_FUNCTION);
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gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
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gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
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gpio_set_pin_function(MAX3421_MISO_PIN, MAX3421_SERCOM_FUNCTION);
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// CS pin
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gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
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gpio_set_pin_level(MAX3421_CS_PIN, 1);
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// Enable the SPI module
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sercom->SPI.CTRLA.bit.ENABLE = 1;
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while (sercom->SPI.SYNCBUSY.bit.ENABLE) {}
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//------------- External Interrupt -------------//
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// Enable the APB clock for EIC (External Interrupt Controller)
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MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
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// Configure GCLK for EIC
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GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
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// Configure PA20 as an input with function A (external interrupt)
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gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
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gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
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gpio_set_pin_function(MAX3421_INTR_PIN, 0);
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// Disable EIC
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EIC->CTRLA.bit.ENABLE = 0;
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while (EIC->SYNCBUSY.bit.ENABLE);
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// Configure EIC to trigger on falling edge
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volatile uint32_t* eic_config;
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uint8_t sense_shift;
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if (MAX3421_INTR_EIC_ID < 8) {
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eic_config = &EIC->CONFIG[0].reg;
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sense_shift = MAX3421_INTR_EIC_ID * 4;
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} else {
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eic_config = &EIC->CONFIG[1].reg;
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sense_shift = (MAX3421_INTR_EIC_ID - 8) * 4;
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}
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*eic_config &= ~(7 << sense_shift);
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*eic_config |= 2 << sense_shift;
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#if CFG_TUSB_OS == OPT_OS_FREERTOS
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// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
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NVIC_SetPriority(EIC_0_IRQn + MAX3421_INTR_EIC_ID, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
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#endif
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// Enable External Interrupt
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EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
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// Enable EIC
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EIC->CTRLA.bit.ENABLE = 1;
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while (EIC->SYNCBUSY.bit.ENABLE);
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}
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void MAX3421_EIC_Handler(void) {
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// Clear the interrupt flag
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EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
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// Call the TinyUSB interrupt handler
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tuh_int_handler(1, true);
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}
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// API to enable/disable MAX3421 INTR pin interrupt
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void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
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(void) rhport;
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const IRQn_Type irq = EIC_0_IRQn + MAX3421_INTR_EIC_ID;
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if (enabled) {
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NVIC_EnableIRQ(irq);
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} else {
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NVIC_DisableIRQ(irq);
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}
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}
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// API to control MAX3421 SPI CS
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void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
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(void) rhport;
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gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
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}
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// API to transfer data with MAX3421 SPI
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// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
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bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
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(void) rhport;
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Sercom* sercom = MAX3421_SERCOM;
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for (size_t count = 0; count < xfer_bytes; count++) {
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// Wait for the transmit buffer to be empty
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while (!sercom->SPI.INTFLAG.bit.DRE);
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// Write data to be transmitted
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uint8_t data = 0x00;
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if (tx_buf) {
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data = tx_buf[count];
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}
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sercom->SPI.DATA.reg = (uint32_t) data;
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// Wait for the receive buffer to be filled
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while (!sercom->SPI.INTFLAG.bit.RXC);
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// Read received data
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data = (uint8_t) sercom->SPI.DATA.reg;
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if (rx_buf) {
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rx_buf[count] = data;
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}
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}
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// wait for bus idle and clear flags
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while (!(sercom->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
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sercom->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
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return true;
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}
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#endif
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