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passkey_fw
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correct setting trace clock

This commit is contained in:
hathach 2023-07-07 11:07:57 +07:00
parent c53acb1455
commit 4bbacb1008
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GPG Key ID: F5D50C6D51D17CBA
4 changed files with 7 additions and 19 deletions
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8
hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
View File

@ -8,14 +8,7 @@
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
#ifdef TRACE_ETM
// Due to ozone fixed trace clock div = 1, PLL is limited around 100Mhz. This use 128 Mhz
#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(16U,0U)) /* PLL Mul x16.0 */
#else
#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */
#endif
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */
@ -41,5 +34,4 @@
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
#endif /* BSP_CLOCK_CFG_H_ */

3
hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
View File

@ -29,9 +29,8 @@ void OnProjectLoad (void) {
**********************************************************************
*/
void BeforeTargetConnect (void) {
//
// Trace pin init is done by J-Link script file as J-Link script files are IDE independent
//
Project.SetJLinkScript("../../../debug.jlinkscript");
}
/*********************************************************************

11
hw/bsp/ra/family.c
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@ -49,8 +49,6 @@
/* Key code for writing PRCR register. */
#define BSP_PRV_PRCR_KEY (0xA500U)
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
static const ioport_cfg_t family_pin_cfg = {
.number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
@ -98,10 +96,13 @@ void board_init(void) {
R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
#ifdef TRACE_ETM
// Enable trace clock (max 100Mhz) = PLL / div
// Somehow ozone/jtrace always fixed trace div to 1 therefore for ETM tracing working reliably
// PLL is limited around 100Mhz
// TRCKCR is protected by PRCR bit0 register
R_SYSTEM->PRCR = (uint16_t) (BSP_PRV_PRCR_KEY | 0x01);
// Enable trace clock (max 100Mhz). Since PLL/CPU is 200Mhz, clock div = 2
R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01;
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_KEY;
#endif
#if CFG_TUSB_OS == OPT_OS_FREERTOS

4
hw/bsp/ra/family.cmake
View File

@ -37,10 +37,6 @@ function(add_board_target BOARD_TARGET)
${FSP_RA}/src/bsp/mcu/all/bsp_security.c
${FSP_RA}/src/r_ioport/r_ioport.c
)
# ETM Trace option
if (TRACE_ETM STREQUAL "1")
target_compile_definitions(${BOARD_TARGET} PUBLIC TRACE_ETM)
endif ()
target_compile_options(${BOARD_TARGET} PUBLIC
-ffreestanding