- correct tuh_max3421e_int_api() for nrf52
- hcd_int_disable/enable is software only to reduce interrupt lag
This commit is contained in:
hathach
parent
b31924e13e
commit
3740a3287a
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@ -31,6 +31,8 @@
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extern "C" {
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#endif
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#define _PINNUM(port, pin) ((port)*32 + (pin))
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// LED
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#define LED_PIN 13
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#define LED_STATE_ON 0
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@ -43,6 +45,13 @@
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#define UART_RX_PIN 8
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#define UART_TX_PIN 6
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// SPI for USB host shield
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#define MAX3421E_SCK_PIN _PINNUM(1, 15)
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#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
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#define MAX3421E_MISO_PIN _PINNUM(1, 14)
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#define MAX3421E_CS_PIN _PINNUM(1, 12)
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#define MAX3241E_INTR_PIN _PINNUM(1, 11)
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#ifdef __cplusplus
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}
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#endif
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@ -107,7 +107,12 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
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//--------------------------------------------------------------------+
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void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
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(void) rhport;
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nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, enabled);
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if (enabled) {
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nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
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}else {
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nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN);
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}
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}
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void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
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@ -217,6 +222,19 @@ void board_init(void) {
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#endif
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
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// MAX3421 need 3.3v signal
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if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
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NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3;
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
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NVIC_SystemReset();
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}
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// manually manage CS
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nrf_gpio_cfg_output(MAX3421E_CS_PIN);
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tuh_max3421_spi_cs_api(0, false);
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@ -184,8 +184,6 @@ typedef struct {
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} max3421_ep_t;
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typedef struct {
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atomic_flag busy; // busy transferring
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// cached register
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uint8_t sndbc;
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uint8_t hirq;
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@ -194,7 +192,10 @@ typedef struct {
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uint8_t peraddr;
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uint8_t hxfr;
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atomic_flag busy; // busy transferring
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volatile uint8_t intr_disable_count;
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volatile uint16_t frame_count;
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max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
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OSAL_MUTEX_DEF(spi_mutexdef);
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@ -220,8 +221,8 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
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static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
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// disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
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if (!in_isr) {
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tuh_max3421e_int_api(rhport, false);
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(void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
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tuh_max3421e_int_api(rhport, false);
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}
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// assert CS
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@ -294,6 +295,12 @@ static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
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return ret ? rx_buf[1] : 0;
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}
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static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
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reg_write(rhport, HIRQ_ADDR, data, in_isr);
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// HIRQ write 1 is clear
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_hcd_data.hirq &= ~data;
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}
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static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
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_hcd_data.hien = data;
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reg_write(rhport, HIEN_ADDR, data, in_isr);
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@ -440,13 +447,14 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
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bool hcd_init(uint8_t rhport) {
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(void) rhport;
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hcd_int_disable(rhport);
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tuh_max3421e_int_api(rhport, false);
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tuh_max3421_spi_cs_api(rhport, false);
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TU_LOG2_INT(sizeof(max3421_ep_t));
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TU_LOG2_INT(sizeof(max3421_data_t));
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tu_memclr(&_hcd_data, sizeof(_hcd_data));
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_hcd_data.peraddr = 0xff; // invalid
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#if OSAL_MUTEX_REQUIRED
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_hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef);
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@ -469,11 +477,13 @@ bool hcd_init(uint8_t rhport) {
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reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false);
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// clear all previously pending IRQ
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reg_write(rhport, HIRQ_ADDR, 0xff, false);
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hirq_write(rhport, 0xff, false);
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// Enable IRQ
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hien_write(rhport, DEFAULT_HIEN, false);
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tuh_max3421e_int_api(rhport, true);
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// Enable Interrupt pin
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reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
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@ -481,13 +491,21 @@ bool hcd_init(uint8_t rhport) {
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}
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// Enable USB interrupt
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// Not actually enable GPIO interrupt, just set variable to prevent handler to process
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void hcd_int_enable (uint8_t rhport) {
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tuh_max3421e_int_api(rhport, true);
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(void) rhport;
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// tuh_max3421e_int_api(rhport, true);
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if (_hcd_data.intr_disable_count) {
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_hcd_data.intr_disable_count--;
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}
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}
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// Disable USB interrupt
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// Not actually disable GPIO interrupt, just set variable to prevent handler to process
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void hcd_int_disable(uint8_t rhport) {
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tuh_max3421e_int_api(rhport, false);
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(void) rhport;
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//tuh_max3421e_int_api(rhport, false);
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_hcd_data.intr_disable_count++;
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}
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// Get frame number (1ms)
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@ -521,7 +539,7 @@ void hcd_port_reset_end(uint8_t rhport) {
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reg_write(rhport, HCTL_ADDR, 0, false);
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// Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
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reg_write(rhport, HIRQ_ADDR, HIRQ_CONDET_IRQ, false);
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hirq_write(rhport, HIRQ_CONDET_IRQ, false);
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hien_write(rhport, DEFAULT_HIEN, false);
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}
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@ -572,19 +590,23 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
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void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
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// Page 12: Programming BULK-OUT Transfers
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// TODO double buffered
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if (switch_ep) {
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peraddr_write(rhport, ep->daddr, in_isr);
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uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
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reg_write(rhport, HCTL_ADDR, hctl, in_isr);
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}
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uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
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if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
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// Control ZLP status use HS
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hxfr |= HXFR_HS;
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} else {
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}
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if (switch_ep) {
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peraddr_write(rhport, ep->daddr, in_isr);
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if ( 0 == (hxfr & HXFR_HS) ) {
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uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
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reg_write(rhport, HCTL_ADDR, hctl, in_isr);
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}
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}
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if ( 0 == (hxfr & HXFR_HS) ) {
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uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
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TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
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if (xact_len) {
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@ -598,12 +620,6 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
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void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
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// Page 13: Programming BULK-IN Transfers
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if (switch_ep) {
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peraddr_write(rhport, ep->daddr, in_isr);
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uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
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reg_write(rhport, HCTL_ADDR, hctl, in_isr);
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}
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uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
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if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
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@ -611,6 +627,15 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
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hxfr |= HXFR_HS;
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}
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if (switch_ep) {
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peraddr_write(rhport, ep->daddr, in_isr);
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if ( 0 == (hxfr & HXFR_HS) ) {
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uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
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reg_write(rhport, HCTL_ADDR, hctl, in_isr);
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}
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}
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hxfr_write(rhport, hxfr, in_isr);
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}
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@ -721,7 +746,7 @@ static void handle_xfer_done(uint8_t rhport) {
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xfer_result_t xfer_result;
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//TU_LOG3("HRSL: %02X\r\n", hrsl);
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// TU_LOG3("HRSL: %02X\r\n", hrsl);
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switch(hresult) {
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case HRSL_SUCCESS:
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xfer_result = XFER_RESULT_SUCCESS;
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@ -821,13 +846,20 @@ void print_hirq(uint8_t hirq) {
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void hcd_int_handler(uint8_t rhport) {
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uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
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if (!hirq) return;
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// print_hirq(hirq);
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if (hirq & HIRQ_FRAME_IRQ) {
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_hcd_data.frame_count++;
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}
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// interrupt is disabled, only ack FRAME IRQ and skip the rest
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if (_hcd_data.intr_disable_count) {
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if (hirq & HIRQ_FRAME_IRQ) {
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hirq_write(rhport, HIRQ_FRAME_IRQ, true);
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}
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return;
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}
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if (hirq & HIRQ_CONDET_IRQ) {
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tusb_speed_t speed = handle_connect_irq(rhport);
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@ -861,7 +893,7 @@ void hcd_int_handler(uint8_t rhport) {
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}
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// ack RCVDVAV IRQ
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reg_write(rhport, HIRQ_ADDR, HIRQ_RCVDAV_IRQ, true);
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hirq_write(rhport, HIRQ_RCVDAV_IRQ, true);
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hirq = reg_read(rhport, HIRQ_ADDR, true);
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}
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@ -871,7 +903,7 @@ void hcd_int_handler(uint8_t rhport) {
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}
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if ( hirq & HIRQ_HXFRDN_IRQ ) {
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reg_write(rhport, HIRQ_ADDR, HIRQ_HXFRDN_IRQ, true);
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hirq_write(rhport, HIRQ_HXFRDN_IRQ, true);
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handle_xfer_done(rhport);
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}
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@ -881,7 +913,7 @@ void hcd_int_handler(uint8_t rhport) {
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// clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
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hirq &= ~HIRQ_SNDBAV_IRQ;
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if ( hirq ) {
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reg_write(rhport, HIRQ_ADDR, hirq, true);
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hirq_write(rhport, hirq, true);
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}
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}
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