528 lines
19 KiB
C
528 lines
19 KiB
C
/**************************************************************************/
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/*!
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@file dcd_lpc175x_6x.c
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@author hathach (tinyusb.org)
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@section LICENSE
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Software License Agreement (BSD License)
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Copyright (c) 2013, hathach (tinyusb.org)
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holders nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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#include "tusb_option.h"
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#if MODE_DEVICE_SUPPORTED && (TUSB_CFG_MCU == MCU_LPC175X_6X)
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#define _TINY_USB_SOURCE_FILE_
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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#include "dcd.h"
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#include "dcd_lpc175x_6x.h"
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#include "usbd_dcd.h"
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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#define DCD_QHD_MAX 32
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#define DCD_QTD_MAX 32 // TODO scale with configure
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typedef struct {
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volatile dcd_dma_descriptor_t* udca[DCD_QHD_MAX]; // must be 128 byte aligned
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dcd_dma_descriptor_t dd[DCD_QTD_MAX][2]; // each endpoints can have up to 2 DD queued at a time TODO 0-1 are not used, offset to reduce memory
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uint8_t class_code[DCD_QHD_MAX];
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struct {
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uint8_t* p_data;
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uint16_t remaining_bytes;
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uint8_t int_on_complete;
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}control_dma;
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}dcd_data_t;
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TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(128) STATIC_ dcd_data_t dcd_data;
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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static void bus_reset(void);
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static tusb_error_t pipe_control_read(void * buffer, uint16_t length);
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static tusb_error_t pipe_control_write(void const * buffer, uint16_t length);
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static tusb_error_t pipe_control_xfer(uint8_t ep_id, uint8_t* p_buffer, uint16_t length);
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//--------------------------------------------------------------------+
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// PIPE HELPER
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//--------------------------------------------------------------------+
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static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr) ATTR_CONST ATTR_ALWAYS_INLINE;
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static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
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{
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return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 1 : 0);
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}
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static inline void edpt_set_max_packet_size(uint8_t ep_id, uint16_t max_packet_size) ATTR_ALWAYS_INLINE;
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static inline void edpt_set_max_packet_size(uint8_t ep_id, uint16_t max_packet_size)
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{ // follows example in 11.10.4.2
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LPC_USB->USBReEp |= BIT_(ep_id);
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LPC_USB->USBEpInd = ep_id; // select index before setting packet size
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LPC_USB->USBMaxPSize = max_packet_size;
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#ifndef _TEST_
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while ((LPC_USB->USBDevIntSt & DEV_INT_ENDPOINT_REALIZED_MASK) == 0) {} // TODO can be omitted
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LPC_USB->USBDevIntClr = DEV_INT_ENDPOINT_REALIZED_MASK;
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#endif
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}
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//--------------------------------------------------------------------+
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// USBD-DCD API
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//--------------------------------------------------------------------+
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static void bus_reset(void)
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{
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// step 7 : slave mode set up
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LPC_USB->USBEpIntClr = 0xFFFFFFFF; // clear all pending interrupt
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LPC_USB->USBDevIntClr = 0xFFFFFFFF; // clear all pending interrupt
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LPC_USB->USBEpIntEn = (uint32_t) BIN8(11); // control endpoint cannot use DMA, non-control all use DMA
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LPC_USB->USBEpIntPri = 0; // same priority for all endpoint
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// step 8 : DMA set up
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LPC_USB->USBEpDMADis = 0xFFFFFFFF; // firstly disable all dma
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LPC_USB->USBDMARClr = 0xFFFFFFFF; // clear all pending interrupt
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LPC_USB->USBEoTIntClr = 0xFFFFFFFF;
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LPC_USB->USBNDDRIntClr = 0xFFFFFFFF;
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LPC_USB->USBSysErrIntClr = 0xFFFFFFFF;
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memclr_(&dcd_data, sizeof(dcd_data_t));
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}
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tusb_error_t dcd_init(void)
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{
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//------------- user manual 11.13 usb device controller initialization -------------// LPC_USB->USBEpInd = 0;
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// step 6 : set up control endpoint
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edpt_set_max_packet_size(0, TUSB_CFG_DEVICE_CONTROL_ENDOINT_SIZE);
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edpt_set_max_packet_size(1, TUSB_CFG_DEVICE_CONTROL_ENDOINT_SIZE);
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bus_reset();
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LPC_USB->USBDevIntEn = (DEV_INT_DEVICE_STATUS_MASK | DEV_INT_ENDPOINT_SLOW_MASK | DEV_INT_ERROR_MASK);
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LPC_USB->USBUDCAH = (uint32_t) dcd_data.udca;
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LPC_USB->USBDMAIntEn = (DMA_INT_END_OF_XFER_MASK | DMA_INT_ERROR_MASK );
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sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1); // connect
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return TUSB_ERROR_NONE;
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}
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static void endpoint_non_control_isr(uint32_t eot_int)
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{
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for(uint8_t ep_id = 2; ep_id < DCD_QHD_MAX; ep_id++ )
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{
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if ( BIT_TEST_(eot_int, ep_id) )
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{
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dcd_dma_descriptor_t* const p_first_dd = &dcd_data.dd[ep_id][0];
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dcd_dma_descriptor_t* const p_last_dd = dcd_data.dd[ep_id] + (p_first_dd->is_next_valid ? 1 : 0); // Maximum is 2 QTD are queued in an endpoint
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// only handle when Controller already finished the last DD
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if ( dcd_data.udca[ep_id] == p_last_dd )
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{
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dcd_data.udca[ep_id] = p_first_dd; // UDCA currently points to the last DD, change to the fixed DD
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p_first_dd->buffer_length = 0; // buffer length is used to determined if first dd is queued in pipe xfer function
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if ( p_last_dd->int_on_complete )
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{
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endpoint_handle_t edpt_hdl =
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{
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.coreid = 0,
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.index = ep_id,
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.class_code = dcd_data.class_code[ep_id]
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};
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tusb_event_t event = (p_last_dd->status == DD_STATUS_NORMAL || p_last_dd->status == DD_STATUS_DATA_UNDERUN) ? TUSB_EVENT_XFER_COMPLETE : TUSB_EVENT_XFER_ERROR;
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usbd_xfer_isr(edpt_hdl, event, p_last_dd->present_count); // report only xferred bytes in the IOC qtd
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}
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}
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}
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}
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}
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static void endpoint_control_isr(void)
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{
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uint32_t const endpoint_int_status = LPC_USB->USBEpIntSt & LPC_USB->USBEpIntEn;
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// LPC_USB->USBEpIntClr = endpoint_int_status; // acknowledge interrupt TODO cannot immediately acknowledge setup packet
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//------------- Setup Recieved-------------//
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if ( (endpoint_int_status & BIT_(0)) &&
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(sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0, 1) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK) )
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{
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(void) sie_read(SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT+0, 1); // clear setup bit
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tusb_control_request_t control_request;
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pipe_control_read(&control_request, 8); // TODO read before clear setup above
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usbd_setup_received_isr(0, &control_request);
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}
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else if (endpoint_int_status & 0x03)
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{
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uint8_t const ep_id = ( endpoint_int_status & BIT_(0) ) ? 0 : 1;
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if ( dcd_data.control_dma.remaining_bytes > 0 )
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{ // there are still data to transfer
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pipe_control_xfer(ep_id, dcd_data.control_dma.p_data, dcd_data.control_dma.remaining_bytes);
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}
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else
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{
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dcd_data.control_dma.remaining_bytes = 0;
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if ( BIT_TEST_(dcd_data.control_dma.int_on_complete, ep_id) )
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{
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endpoint_handle_t edpt_hdl = { .coreid = 0, .class_code = 0 };
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dcd_data.control_dma.int_on_complete = 0;
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// FIXME xferred_byte for control xfer is not needed now !!!
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usbd_xfer_isr(edpt_hdl, TUSB_EVENT_XFER_COMPLETE, 0);
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}
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}
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}
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LPC_USB->USBEpIntClr = endpoint_int_status; // acknowledge interrupt TODO cannot immediately acknowledge setup packet
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}
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void dcd_isr(uint8_t coreid)
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{
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(void) coreid;
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uint32_t const device_int_status = LPC_USB->USBDevIntSt & LPC_USB->USBDevIntEn;
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LPC_USB->USBDevIntClr = device_int_status;// Acknowledge handled interrupt
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//------------- usb bus event -------------//
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if (device_int_status & DEV_INT_DEVICE_STATUS_MASK)
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{
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uint8_t const dev_status_reg = sie_read(SIE_CMDCODE_DEVICE_STATUS, 1);
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if (dev_status_reg & SIE_DEV_STATUS_RESET_MASK)
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{
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bus_reset();
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usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_RESET);
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}
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if (dev_status_reg & SIE_DEV_STATUS_CONNECT_CHANGE_MASK)
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{ // device is disconnected, require using VBUS (P1_30)
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usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_UNPLUGGED);
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}
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if (dev_status_reg & SIE_DEV_STATUS_SUSPEND_CHANGE_MASK)
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{
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if (dev_status_reg & SIE_DEV_STATUS_SUSPEND_MASK)
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{
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usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_SUSPENDED);
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}
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// else
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// {
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// usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_RESUME);
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// }
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}
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}
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//------------- Control Endpoint (Slave Mode) -------------//
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if (device_int_status & DEV_INT_ENDPOINT_SLOW_MASK)
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{
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endpoint_control_isr();
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}
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//------------- Non-Control Endpoint (DMA Mode) -------------//
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uint32_t dma_int_status = LPC_USB->USBDMAIntSt & LPC_USB->USBDMAIntEn;
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if (dma_int_status & DMA_INT_END_OF_XFER_MASK)
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{
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uint32_t eot_int = LPC_USB->USBEoTIntSt;
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LPC_USB->USBEoTIntClr = eot_int; // acknowledge interrupt source
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endpoint_non_control_isr(eot_int);
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}
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if (device_int_status & DEV_INT_ERROR_MASK || dma_int_status & DMA_INT_ERROR_MASK)
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{
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uint32_t error_status = sie_read(SIE_CMDCODE_READ_ERROR_STATUS, 1);
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(void) error_status;
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// ASSERT(false, (void) 0);
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}
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}
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//--------------------------------------------------------------------+
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// USBD API - CONTROLLER
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//--------------------------------------------------------------------+
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void dcd_controller_connect(uint8_t coreid)
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{
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(void) coreid;
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sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);
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}
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void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr)
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{
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(void) coreid;
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sie_write(SIE_CMDCODE_SET_ADDRESS, 1, 0x80 | dev_addr); // 7th bit is : device_enable
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}
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void dcd_controller_set_configuration(uint8_t coreid)
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{
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(void) coreid;
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sie_write(SIE_CMDCODE_CONFIGURE_DEVICE, 1, 1);
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}
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//--------------------------------------------------------------------+
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// PIPE CONTROL HELPER
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//--------------------------------------------------------------------+
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static inline uint16_t length_byte2dword(uint16_t length_in_bytes) ATTR_ALWAYS_INLINE ATTR_CONST;
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static inline uint16_t length_byte2dword(uint16_t length_in_bytes)
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{
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return (length_in_bytes + 3) / 4; // length_in_dword
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}
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static tusb_error_t pipe_control_xfer(uint8_t ep_id, uint8_t* p_buffer, uint16_t length)
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{
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uint16_t const packet_len = min16_of(length, TUSB_CFG_DEVICE_CONTROL_ENDOINT_SIZE);
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if (ep_id)
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{
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ASSERT_STATUS ( pipe_control_write(p_buffer, packet_len) );
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}else
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{
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ASSERT_STATUS ( pipe_control_read(p_buffer, packet_len) );
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}
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dcd_data.control_dma.remaining_bytes -= packet_len;
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dcd_data.control_dma.p_data += packet_len;
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return TUSB_ERROR_NONE;
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}
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static tusb_error_t pipe_control_write(void const * buffer, uint16_t length)
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{
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uint32_t const * p_write_data = (uint32_t const *) buffer;
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LPC_USB->USBCtrl = USBCTRL_WRITE_ENABLE_MASK; // logical endpoint = 0
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LPC_USB->USBTxPLen = length;
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for (uint16_t count = 0; count < length_byte2dword(length); count++)
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{
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LPC_USB->USBTxData = *p_write_data; // NOTE: cortex M3 have no problem with alignment
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p_write_data++;
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}
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LPC_USB->USBCtrl = 0;
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// select control IN & validate the endpoint
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sie_write(SIE_CMDCODE_ENDPOINT_SELECT+1, 0, 0);
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sie_write(SIE_CMDCODE_BUFFER_VALIDATE , 0, 0);
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return TUSB_ERROR_NONE;
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}
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static tusb_error_t pipe_control_read(void * buffer, uint16_t length)
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{
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LPC_USB->USBCtrl = USBCTRL_READ_ENABLE_MASK; // logical endpoint = 0
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while ((LPC_USB->USBRxPLen & USBRXPLEN_PACKET_READY_MASK) == 0) {} // TODO blocking, should have timeout
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uint16_t actual_length = min16_of(length, (uint16_t) (LPC_USB->USBRxPLen & USBRXPLEN_PACKET_LENGTH_MASK) );
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uint32_t *p_read_data = (uint32_t*) buffer;
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for( uint16_t count=0; count < length_byte2dword(actual_length); count++)
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{
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*p_read_data = LPC_USB->USBRxData;
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p_read_data++; // increase by 4 ( sizeof(uint32_t) )
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}
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LPC_USB->USBCtrl = 0;
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// select control OUT & clear the endpoint
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sie_write(SIE_CMDCODE_ENDPOINT_SELECT+0, 0, 0);
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sie_write(SIE_CMDCODE_BUFFER_CLEAR , 0, 0);
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return TUSB_ERROR_NONE;
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}
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//--------------------------------------------------------------------+
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// CONTROL PIPE API
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//--------------------------------------------------------------------+
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void dcd_pipe_control_stall(uint8_t coreid)
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{
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sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+0, 1, SIE_SET_ENDPOINT_STALLED_MASK | SIE_SET_ENDPOINT_CONDITION_STALLED_MASK);
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}
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
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{
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(void) coreid;
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ASSERT( !(length != 0 && p_buffer == NULL), TUSB_ERROR_INVALID_PARA);
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// determine Endpoint where Data & Status phase occurred (IN or OUT)
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uint8_t const ep_data = (dir == TUSB_DIR_DEV_TO_HOST) ? 1 : 0;
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uint8_t const ep_status = 1 - ep_data;
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dcd_data.control_dma.int_on_complete = int_on_complete ? BIT_(ep_status) : 0;
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//------------- Data Phase -------------//
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if ( length )
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{
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dcd_data.control_dma.p_data = (uint8_t*) p_buffer;
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dcd_data.control_dma.remaining_bytes = length;
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// lpc17xx already received the first DATA OUT packet by now
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ASSERT_STATUS ( pipe_control_xfer(ep_data, p_buffer, length) );
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}
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//------------- Status Phase (opposite direct to Data) -------------//
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if (dir == TUSB_DIR_HOST_TO_DEV)
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{ // only write for CONTROL OUT, CONTROL IN data will be retrieved in dcd_isr // TODO ????
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ASSERT_STATUS ( pipe_control_write(NULL, 0) );
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}
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return TUSB_ERROR_NONE;
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}
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//--------------------------------------------------------------------+
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// BULK/INTERRUPT/ISO PIPE API
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//--------------------------------------------------------------------+
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endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, uint8_t class_code)
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{
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(void) coreid;
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endpoint_handle_t const null_handle = { 0 };
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// TODO refractor to universal pipe open validation function
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if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return null_handle; // TODO not support ISO yet
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ASSERT (p_endpoint_desc->wMaxPacketSize.size <= 64, null_handle); // TODO ISO can be 1023, but ISO not supported now
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uint8_t ep_id = edpt_addr2phy( p_endpoint_desc->bEndpointAddress );
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//------------- Realize Endpoint with Max Packet Size -------------//
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edpt_set_max_packet_size(ep_id, p_endpoint_desc->wMaxPacketSize.size);
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dcd_data.class_code[ep_id] = class_code;
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//------------- first DD prepare -------------//
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dcd_dma_descriptor_t* const p_dd = &dcd_data.dd[ep_id][0];
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memclr_(p_dd, sizeof(dcd_dma_descriptor_t));
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p_dd->is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
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p_dd->max_packet_size = p_endpoint_desc->wMaxPacketSize.size;
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p_dd->is_retired = 1; // inactive at first
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dcd_data.udca[ ep_id ] = p_dd; // hook to UDCA
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sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+ep_id, 1, 0); // clear all endpoint status
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return (endpoint_handle_t)
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{
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.coreid = 0,
|
|
.index = ep_id,
|
|
.class_code = class_code
|
|
};
|
|
}
|
|
|
|
bool dcd_pipe_is_busy(endpoint_handle_t edpt_hdl)
|
|
{
|
|
return (dcd_data.udca[edpt_hdl.index] != NULL && !dcd_data.udca[edpt_hdl.index]->is_retired);
|
|
}
|
|
|
|
tusb_error_t dcd_pipe_stall(endpoint_handle_t edpt_hdl)
|
|
{
|
|
sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+edpt_hdl.index, 1, SIE_SET_ENDPOINT_STALLED_MASK);
|
|
return TUSB_ERROR_NONE;
|
|
}
|
|
|
|
tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
|
|
{
|
|
uint8_t ep_id = edpt_addr2phy(edpt_addr);
|
|
|
|
sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+ep_id, 1, 0);
|
|
|
|
return TUSB_ERROR_FAILED;
|
|
}
|
|
|
|
void dd_xfer_init(dcd_dma_descriptor_t* p_dd, void* buffer, uint16_t total_bytes)
|
|
{
|
|
p_dd->next = 0;
|
|
p_dd->is_next_valid = 0;
|
|
p_dd->buffer_addr = (uint32_t) buffer;
|
|
p_dd->buffer_length = total_bytes;
|
|
p_dd->status = DD_STATUS_NOT_SERVICED;
|
|
p_dd->iso_last_packet_valid = 0;
|
|
p_dd->present_count = 0;
|
|
}
|
|
|
|
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
|
|
{ // NOTE for sure the qhd has no dds
|
|
dcd_dma_descriptor_t* const p_fixed_dd = &dcd_data.dd[edpt_hdl.index][0]; // always queue with the fixed DD
|
|
|
|
dd_xfer_init(p_fixed_dd, buffer, total_bytes);
|
|
p_fixed_dd->is_retired = 1;
|
|
p_fixed_dd->int_on_complete = 0;
|
|
|
|
return TUSB_ERROR_NONE;
|
|
}
|
|
|
|
tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
|
|
{
|
|
dcd_dma_descriptor_t* const p_first_dd = &dcd_data.dd[edpt_hdl.index][0];
|
|
|
|
//------------- fixed DD is already queued a xfer -------------//
|
|
if ( p_first_dd->buffer_length )
|
|
{
|
|
// setup new dd
|
|
dcd_dma_descriptor_t* const p_dd = &dcd_data.dd[ edpt_hdl.index ][1];
|
|
memclr_(p_dd, sizeof(dcd_dma_descriptor_t));
|
|
|
|
dd_xfer_init(p_dd, buffer, total_bytes);
|
|
|
|
p_dd->max_packet_size = p_first_dd->max_packet_size;
|
|
p_dd->is_isochronous = p_first_dd->is_isochronous;
|
|
p_dd->int_on_complete = int_on_complete;
|
|
|
|
// hook to fixed dd
|
|
p_first_dd->next = (uint32_t) p_dd;
|
|
p_first_dd->is_next_valid = 1;
|
|
}
|
|
//------------- fixed DD is free -------------//
|
|
else
|
|
{
|
|
dd_xfer_init(p_first_dd, buffer, total_bytes);
|
|
p_first_dd->int_on_complete = int_on_complete;
|
|
}
|
|
|
|
p_first_dd->is_retired = 0; // activate xfer
|
|
dcd_data.udca[edpt_hdl.index] = p_first_dd;
|
|
LPC_USB->USBEpDMAEn = BIT_(edpt_hdl.index);
|
|
|
|
if ( edpt_hdl.index % 2 )
|
|
{ // endpoint IN need to actively raise DMA request
|
|
LPC_USB->USBDMARSet = BIT_(edpt_hdl.index);
|
|
}
|
|
|
|
return TUSB_ERROR_NONE;
|
|
}
|
|
|
|
#endif
|