125 lines
2.9 KiB
C
125 lines
2.9 KiB
C
/*
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* sys-clock.c
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*
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* Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
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* Official site: http://xboot.org
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* Mobile phone: +86-18665388956
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* QQ: 8192542
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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//#include <xboot.h>
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#include <stdint.h>
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#include <f1c100s/reg-ccu.h>
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#include <io.h>
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static inline void sdelay(int loops)
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{
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__asm__ __volatile__ ("1:\n" "subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0"(loops));
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}
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static void wait_pll_stable(uint32_t base)
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{
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uint32_t rval = 0;
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uint32_t time = 0xfff;
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do {
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rval = read32(base);
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time--;
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} while(time && !(rval & (1 << 28)));
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}
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static void clock_set_pll_cpu(uint32_t clk)
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{
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uint32_t n, k, m, p;
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uint32_t rval = 0;
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uint32_t div = 0;
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if(clk > 720000000)
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clk = 720000000;
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if((clk % 24000000) == 0)
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{
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div = clk / 24000000;
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n = div - 1;
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k = 0;
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m = 0;
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p = 0;
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}
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else if((clk % 12000000) == 0)
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{
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m = 1;
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div = clk / 12000000;
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if((div % 3) == 0)
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k = 2;
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else if((div % 4) == 0)
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k = 3;
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else
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k = 1;
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n = (div / (k + 1)) - 1;
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p = 0;
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}
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else
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{
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div = clk / 24000000;
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n = div - 1;
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k = 0;
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m = 0;
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p = 0;
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}
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rval = read32(F1C100S_CCU_BASE + CCU_PLL_CPU_CTRL);
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rval &= ~((0x3 << 16) | (0x1f << 8) | (0x3 << 4) | (0x3 << 0));
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rval |= (1U << 31) | (p << 16) | (n << 8) | (k << 4) | m;
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write32(F1C100S_CCU_BASE + CCU_PLL_CPU_CTRL, rval);
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wait_pll_stable(F1C100S_CCU_BASE + CCU_PLL_CPU_CTRL);
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}
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void sys_clock_init(void)
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{
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uint32_t val;
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write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME0, 0x1ff);
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write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME1, 0x1ff);
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val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
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val &= ~(0x3 << 16);
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val |= (0x1 << 16);
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write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
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sdelay(100);
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write32(F1C100S_CCU_BASE + CCU_PLL_VIDEO_CTRL, 0x81004107);
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sdelay(100);
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write32(F1C100S_CCU_BASE + CCU_PLL_PERIPH_CTRL, 0x80041800);
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sdelay(100);
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write32(F1C100S_CCU_BASE + CCU_AHB_APB_CFG, 0x00003180);
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sdelay(100);
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val = read32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE);
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val |= (0x1 << 26) | (0x1 << 24);
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write32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE, val);
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sdelay(100);
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clock_set_pll_cpu(408000000);
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val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
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val &= ~(0x3 << 16);
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val |= (0x2 << 16);
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write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
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sdelay(100);
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}
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