360 lines
20 KiB
C
360 lines
20 KiB
C
/**********************************************************************
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* $Id$ lpc43xx_mac.h 2011-06-02
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*//**
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* @file lpc43xx_mac.h
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* @brief Contains all functions support for the MAC peripheral
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* @version 1.0
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* @date 02. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors<72>
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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#ifndef __lpc18xx_lpc43xx_mac_regs_H_
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#define __lpc18xx_lpc43xx_mac_regs_H_
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @defgroup lwip18xx_43xx_emac_regs lpc18xx/43xx EMAC registers
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* @ingroup lwip18xx_43xx_emac_DRIVER
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*
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* Variants of these constants and macros exist in the lpc18xx or
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* lpc43xx files. These are signficantly shorter and make the code
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* easier to read.
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*
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* @{
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*/
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/* MAC_CONFIG register bit defines */
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#define MAC_CFG_RE (1 << 2) /*!< Receiver enable */
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#define MAC_CFG_TE (1 << 3) /*!< Transmitter Enable */
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#define MAC_CFG_DF (1 << 4) /*!< Deferral Check */
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#define MAC_CFG_BL(n) ((n) << 5) /*!< Back-Off Limit */
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#define MAC_CFG_ACS (1 << 7) /*!< Automatic Pad/CRC Stripping */
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#define MAC_CFG_LUD (1 << 8) /*!< Link Up/Down, 1 = up */
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#define MAC_CFG_DR (1 << 9) /*!< Disable Retry */
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#define MAC_CFG_IPC (1 << 10) /*!< Checksum Offload */
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#define MAC_CFG_DM (1 << 11) /*!< Duplex Mode, 1 = full, 0 = half */
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#define MAC_CFG_LM (1 << 12) /*!< Loopback Mode */
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#define MAC_CFG_DO (1 << 13) /*!< Disable Receive Own */
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#define MAC_CFG_FES (1 << 14) /*!< Speed, 1 = 100Mbps, 0 = 10Mbos */
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#define MAC_CFG_PS (1 << 15) /*!< Port select, must always be 1 */
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#define MAC_CFG_DCRS (1 << 16) /*!< Disable carrier sense during transmission */
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#define MAC_CFG_IFG(n) ((n) << 17) /*!< Inter-frame gap, 40..96, n incs by 8 */
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#define MAC_CFG_JE (1 << 20) /*!< Jumbo Frame Enable */
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#define MAC_CFG_JD (1 << 22) /*!< Jabber Disable */
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#define MAC_CFG_WD (1 << 23) /*!< Watchdog Disable */
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/* MAC_FRAME_FILTER register bit defines */
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#define MAC_FF_PR (1 << 0) /*!< Promiscuous Mode */
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#define MAC_FF_DAIF (1 << 3) /*!< DA Inverse Filtering */
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#define MAC_FF_PM (1 << 4) /*!< Pass All Multicast */
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#define MAC_FF_DBF (1 << 5) /*!< Disable Broadcast Frames */
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#define MAC_FF_PCF(n) ((n) << 6) /*!< Pass Control Frames, n = see user manual */
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#define MAC_FF_SAIF (1 << 8) /*!< SA Inverse Filtering */
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#define MAC_FF_SAF (1 << 9) /*!< Source Address Filter Enable */
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#define MAC_FF_RA (1UL << 31) /*!< Receive all */
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/* MAC_MII_ADDR register bit defines */
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#define MAC_MIIA_GB (1 << 0) /*!< MII busy */
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#define MAC_MIIA_W (1 << 1) /*!< MII write */
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#define MAC_MIIA_CR(n) ((n) << 2) /*!< CSR clock range, n = see manual */
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#define MAC_MIIA_GR(n) ((n) << 6) /*!< MII register. n = 0..31 */
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#define MAC_MIIA_PA(n) ((n) << 11) /*!< Physical layer address, n = 0..31 */
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/* MAC_MII_DATA register bit defines */
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#define MAC_MIID_GDMSK (0xFFFF) /*!< MII data mask */
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/* MAC_FLOW_CONTROL register bit defines */
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#define MAC_FC_FCB (1 << 0) /*!< Flow Control Busy/Backpressure Activate */
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#define MAC_FC_TFE (1 << 1) /*!< Transmit Flow Control Enable */
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#define MAC_FC_RFE (1 << 2) /*!< Receive Flow Control Enable */
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#define MAC_FC_UP (1 << 3) /*!< Unicast Pause Frame Detect */
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#define MAC_FC_PLT(n) ((n) << 4) /*!< Pause Low Threshold, n = see manual */
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#define MAC_FC_DZPQ (1 << 7) /*!< Disable Zero-Quanta Pause */
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#define MAC_FC_PT(n) ((n) << 16) /*!< Pause time */
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/* MAC_VLAN_TAG register bit defines */
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#define MAC_VT_VL(n) ((n) << 0) /*!< VLAN Tag Identifier for Receive Frames */
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#define MAC_VT_ETC (1 << 7) /*!< Enable 12-Bit VLAN Tag Comparison */
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/* MAC_DEBUG register bit defines */
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/* MAC_PMT_CTRL_STAT register bit defines */
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#define MAC_PMT_PD (1 << 0) /*!< Power-down */
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#define MAC_PMT_MPE (1 << 1) /*!< Magic packet enable */
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#define MAC_PMT_WFE (1 << 2) /*!< Wake-up frame enable */
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#define MAC_PMT_MPR (1 << 5) /*!< Magic Packet Received */
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#define MAC_PMT_WFR (1 << 6) /*!< Wake-up Frame Received */
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#define MAC_PMT_GU (1 << 9) /*!< Global Unicast */
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#define MAC_PMT_WFFRPR (1UL << 31) /*!< Wake-up Frame Filter Register Pointer Reset */
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/* MAC_INTR_MASK register bit defines */
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#define MAC_IM_PMT (1 << 3) /*!< PMT Interrupt Mask */
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/* MAC_ADDR0_HIGH register bit defines */
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#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */
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/* MAC_ADDR0_HIGH register bit defines */
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#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */
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/* MAC_TIMESTAMP register bit defines */
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#define MAC_TS_TSENA (1 << 0) /*!< Time Stamp Enable */
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#define MAC_TS_TSCFUP (1 << 1) /*!< Time Stamp Fine or Coarse Update */
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#define MAC_TS_TSINIT (1 << 2) /*!< Time Stamp Initialize */
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#define MAC_TS_TSUPDT (1 << 3) /*!< Time Stamp Update */
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#define MAC_TS_TSTRIG (1 << 4) /*!< Time Stamp Interrupt Trigger Enable */
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#define MAC_TS_TSADDR (1 << 5) /*!< Addend Reg Update */
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#define MAC_TS_TSENAL (1 << 8) /*!< Enable Time Stamp for All Frames */
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#define MAC_TS_TSCTRL (1 << 9) /*!< Time Stamp Digital or Binary rollover control */
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#define MAC_TS_TSVER2 (1 << 10) /*!< Enable PTP packet snooping for version 2 format */
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#define MAC_TS_TSIPENA (1 << 11) /*!< Enable Time Stamp Snapshot for PTP over Ethernet frames */
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#define MAC_TS_TSIPV6E (1 << 12) /*!< Enable Time Stamp Snapshot for IPv6 frames */
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#define MAC_TS_TSIPV4E (1 << 13) /*!< Enable Time Stamp Snapshot for IPv4 frames */
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#define MAC_TS_TSEVNT (1 << 14) /*!< Enable Time Stamp Snapshot for Event Messages */
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#define MAC_TS_TSMSTR (1 << 15) /*!< Enable Snapshot for Messages Relevant to Master */
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#define MAC_TS_TSCLKT(n) ((n) << 16) /*!< Select the type of clock node, n = see menual */
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#define MAC_TS_TSENMA (1 << 18) /*!< Enable MAC address for PTP frame filtering */
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/* DMA_BUS_MODE register bit defines */
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#define DMA_BM_SWR (1 << 0) /*!< Software reset */
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#define DMA_BM_DA (1 << 1) /*!< DMA arbitration scheme, 1 = TX has priority over TX */
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#define DMA_BM_DSL(n) ((n) << 2) /*!< Descriptor skip length, n = see manual */
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#define DMA_BM_ATDS (1 << 7) /*!< Alternate (Enhanced) descriptor size */
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#define DMA_BM_PBL(n) ((n) << 8) /*!< Programmable burst length, n = see manual */
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#define DMA_BM_PR(n) ((n) << 14) /*!< Rx-to-Tx priority ratio, n = see manual */
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#define DMA_BM_FB (1 << 16) /*!< Fixed burst */
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#define DMA_BM_RPBL(n) ((n) << 17) /*!< RxDMA PBL, n = see manual */
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#define DMA_BM_USP (1 << 23) /*!< Use separate PBL */
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#define DMA_BM_PBL8X (1 << 24) /*!< 8 x PBL mode */
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#define DMA_BM_AAL (1 << 25) /*!< Address-aligned beats */
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#define DMA_BM_MB (1 << 26) /*!< Mixed burst */
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#define DMA_BM_TXPR (1 << 27) /*!< Transmit DMA has higher priority than receive DMA */
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/* DMA_STAT register bit defines */
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#define DMA_ST_TI (1 << 0) /*!< Transmit interrupt */
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#define DMA_ST_TPS (1 << 1) /*!< Transmit process stopped */
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#define DMA_ST_TU (1 << 2) /*!< Transmit buffer unavailable */
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#define DMA_ST_TJT (1 << 3) /*!< Transmit jabber timeout */
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#define DMA_ST_OVF (1 << 4) /*!< Receive overflow */
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#define DMA_ST_UNF (1 << 5) /*!< Transmit underflow */
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#define DMA_ST_RI (1 << 6) /*!< Receive interrupt */
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#define DMA_ST_RU (1 << 7) /*!< Receive buffer unavailable */
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#define DMA_ST_RPS (1 << 8) /*!< Received process stopped */
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#define DMA_ST_RWT (1 << 9) /*!< Receive watchdog timeout */
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#define DMA_ST_ETI (1 << 10) /*!< Early transmit interrupt */
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#define DMA_ST_FBI (1 << 13) /*!< Fatal bus error interrupt */
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#define DMA_ST_ERI (1 << 14) /*!< Early receive interrupt */
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#define DMA_ST_AIE (1 << 15) /*!< Abnormal interrupt summary */
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#define DMA_ST_NIS (1 << 16) /*!< Normal interrupt summary */
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#define DMA_ST_ALL (0x1E7FF) /*!< All interrupts */
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/* DMA_OP_MODE register bit defines */
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#define DMA_OM_SR (1 << 1) /*!< Start/stop receive */
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#define DMA_OM_OSF (1 << 2) /*!< Operate on second frame */
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#define DMA_OM_RTC(n) ((n) << 3) /*!< Receive threshold control, n = see manual */
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#define DMA_OM_FUF (1 << 6) /*!< Forward undersized good frames */
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#define DMA_OM_FEF (1 << 7) /*!< Forward error frames */
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#define DMA_OM_ST (1 << 13) /*!< Start/Stop Transmission Command */
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#define DMA_OM_TTC(n) ((n) << 14) /*!< Transmit threshold control, n = see manual */
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#define DMA_OM_FTF (1 << 20) /*!< Flush transmit FIFO */
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#define DMA_OM_TSF (1 << 21) /*!< Transmit store and forward */
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#define DMA_OM_DFF (1 << 24) /*!< Disable flushing of received frames */
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#define DMA_OM_RSF (1 << 25) /*!< Receive store and forward */
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#define DMA_OM_DT (1 << 26) /*!< Disable Dropping of TCP/IP Checksum Error Frames */
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/* DMA_INT_EN register bit defines */
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#define DMA_IE_TIE (1 << 0) /*!< Transmit interrupt enable */
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#define DMA_IE_TSE (1 << 1) /*!< Transmit stopped enable */
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#define DMA_IE_TUE (1 << 2) /*!< Transmit buffer unavailable enable */
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#define DMA_IE_TJE (1 << 3) /*!< Transmit jabber timeout enable */
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#define DMA_IE_OVE (1 << 4) /*!< Overflow interrupt enable */
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#define DMA_IE_UNE (1 << 5) /*!< Underflow interrupt enable */
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#define DMA_IE_RIE (1 << 6) /*!< Receive interrupt enable */
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#define DMA_IE_RUE (1 << 7) /*!< Receive buffer unavailable enable */
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#define DMA_IE_RSE (1 << 8) /*!< Received stopped enable */
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#define DMA_IE_RWE (1 << 9) /*!< Receive watchdog timeout enable */
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#define DMA_IE_ETE (1 << 10) /*!< Early transmit interrupt enable */
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#define DMA_IE_FBE (1 << 13) /*!< Fatal bus error enable */
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#define DMA_IE_ERE (1 << 14) /*!< Early receive interrupt enable */
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#define DMA_IE_AIE (1 << 15) /*!< Abnormal interrupt summary enable */
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#define DMA_IE_NIE (1 << 16) /*!< Normal interrupt summary enable */
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/* DMA_MFRM_BUFOF register bit defines */
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#define DMA_MFRM_FMCMSK (0xFFFF) /*!< Number of frames missed mask */
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#define DMA_MFRM_OC (1 << 16) /*!< Overflow bit for missed frame counter */
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#define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17) /*!< Number of frames missed by the application mask/shift */
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#define DMA_MFRM_OF (1 << 28) /*!< Overflow bit for FIFO overflow counter */
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/* Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines */
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#define TDES_DB (1 << 0) /*!< Deferred Bit */
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#define TDES_UF (1 << 1) /*!< Underflow Error */
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#define TDES_ED (1 << 2) /*!< Excessive Deferral */
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#define TDES_CCMSK(n) (((n) & 0x000000F0) >> 3) /*!< CC: Collision Count (Status field) mask and shift */
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#define TDES_VF (1 << 7) /*!< VLAN Frame */
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#define TDES_EC (1 << 8) /*!< Excessive Collision */
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#define TDES_LC (1 << 9) /*!< Late Collision */
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#define TDES_NC (1 << 10) /*!< No Carrier */
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#define TDES_LCAR (1 << 11) /*!< Loss of Carrier */
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#define TDES_IPE (1 << 12) /*!< IP Payload Error */
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#define TDES_FF (1 << 13) /*!< Frame Flushed */
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#define TDES_JT (1 << 14) /*!< Jabber Timeout */
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#define TDES_ES (1 << 15) /*!< Error Summary */
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#define TDES_IHE (1 << 16) /*!< IP Header Error */
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#define TDES_TTSS (1 << 17) /*!< Transmit Timestamp Status */
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#define TDES_OWN (1UL << 31) /*!< Own Bit */
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/* TRAN_DESC_ENH_T only CTRLSTAT field bit defines */
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#define TDES_ENH_IC (1UL << 30) /*!< Interrupt on Completion, enhanced descriptor */
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#define TDES_ENH_LS (1 << 29) /*!< Last Segment, enhanced descriptor */
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#define TDES_ENH_FS (1 << 28) /*!< First Segment, enhanced descriptor */
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#define TDES_ENH_DC (1 << 27) /*!< Disable CRC, enhanced descriptor */
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#define TDES_ENH_DP (1 << 26) /*!< Disable Pad, enhanced descriptor */
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#define TDES_ENH_TTSE (1 << 25) /*!< Transmit Timestamp Enable, enhanced descriptor */
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#define TDES_ENH_CIC(n) ((n) << 22) /*!< Checksum Insertion Control, enhanced descriptor */
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#define TDES_ENH_TER (1 << 21) /*!< Transmit End of Ring, enhanced descriptor */
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#define TDES_ENH_TCH (1 << 20) /*!< Second Address Chained, enhanced descriptor */
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/* TRAN_DESC_T only BSIZE field bit defines */
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#define TDES_NORM_IC (1UL << 31) /*!< Interrupt on Completion, normal descriptor */
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#define TDES_NORM_FS (1 << 30) /*!< First Segment, normal descriptor */
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#define TDES_NORM_LS (1 << 29) /*!< Last Segment, normal descriptor */
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#define TDES_NORM_CIC(n) ((n) << 27) /*!< Checksum Insertion Control, normal descriptor */
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#define TDES_NORM_DC (1 << 26) /*!< Disable CRC, normal descriptor */
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#define TDES_NORM_TER (1 << 25) /*!< Transmit End of Ring, normal descriptor */
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#define TDES_NORM_TCH (1 << 24) /*!< Second Address Chained, normal descriptor */
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#define TDES_NORM_DP (1 << 23) /*!< Disable Pad, normal descriptor */
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#define TDES_NORM_TTSE (1 << 22) /*!< Transmit Timestamp Enable, normal descriptor */
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#define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */
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#define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */
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/* TRAN_DESC_ENH_T only BSIZE field bit defines */
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#define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */
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#define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */
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/* Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines */
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#define RDES_ESA (1 << 0) /*!< Extended Status Available/Rx MAC Address */
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#define RDES_CE (1 << 1) /*!< CRC Error */
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#define RDES_DRE (1 << 2) /*!< Dribble Bit Error */
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#define RDES_RE (1 << 3) /*!< Receive Error */
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#define RDES_RWT (1 << 4) /*!< Receive Watchdog Timeout */
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#define RDES_FT (1 << 5) /*!< Frame Type */
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#define RDES_LC (1 << 6) /*!< Late Collision */
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#define RDES_TSA (1 << 7) /*!< Timestamp Available/IP Checksum Error (Type1) /Giant Frame */
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#define RDES_LS (1 << 8) /*!< Last Descriptor */
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#define RDES_FS (1 << 9) /*!< First Descriptor */
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#define RDES_VLAN (1 << 10) /*!< VLAN Tag */
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#define RDES_OE (1 << 11) /*!< Overflow Error */
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#define RDES_LE (1 << 12) /*!< Length Error */
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#define RDES_SAF (1 << 13) /*!< Source Address Filter Fail */
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#define RDES_DE (1 << 14) /*!< Descriptor Error */
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#define RDES_ES (1 << 15) /*!< ES: Error Summary */
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#define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16) /*!< Frame Length mask and shift */
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#define RDES_AFM (1 << 30) /*!< Destination Address Filter Fail */
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#define RDES_OWN (1UL << 31) /*!< Own Bit */
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/* Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines */
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#define RDES_DINT (1UL << 31) /*!< Disable interrupt on completion */
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/* REC_DESC_T pnly CTRL field bit defines */
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#define RDES_NORM_RER (1 << 25) /*!< Receive End of Ring, normal descriptor */
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#define RDES_NORM_RCH (1 << 24) /*!< Second Address Chained, normal descriptor */
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#define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */
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#define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */
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/* REC_DESC_ENH_T only CTRL field bit defines */
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#define RDES_ENH_RER (1 << 15) /*!< Receive End of Ring, enhanced descriptor */
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#define RDES_ENH_RCH (1 << 14) /*!< Second Address Chained, enhanced descriptor */
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#define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */
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#define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */
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/* REC_DESC_ENH_T only EXTSTAT field bit defines */
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#define RDES_ENH_IPPL(n) (((n) & 0x7) >> 2) /*!< IP Payload Type mask and shift, enhanced descripto */
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#define RDES_ENH_IPHE (1 << 3) /*!< IP Header Error, enhanced descripto */
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#define RDES_ENH_IPPLE (1 << 4) /*!< IP Payload Error, enhanced descripto */
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#define RDES_ENH_IPCSB (1 << 5) /*!< IP Checksum Bypassed, enhanced descripto */
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#define RDES_ENH_IPV4 (1 << 6) /*!< IPv4 Packet Received, enhanced descripto */
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#define RDES_ENH_IPV6 (1 << 7) /*!< IPv6 Packet Received, enhanced descripto */
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#define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8) /*!< Message Type mask and shift, enhanced descripto */
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/* Maximum size of an ethernet buffer */
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#define EMAC_ETH_MAX_FLEN (1536)
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/* Structure of a transmit descriptor (without timestamp) */
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typedef struct
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{
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__IO uint32_t CTRLSTAT; /*!< TDES control and status word */
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__IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */
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__IO uint32_t B1ADD; /*!< Buffer 1 address */
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__IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
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} TRAN_DESC_T;
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/* Structure of a enhanced transmit descriptor (with timestamp) */
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typedef struct
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{
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__IO uint32_t CTRLSTAT; /*!< TDES control and status word */
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__IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */
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__IO uint32_t B1ADD; /*!< Buffer 1 address */
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__IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
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__IO uint32_t TDES4; /*!< Reserved */
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__IO uint32_t TDES5; /*!< Reserved */
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__IO uint32_t TTSL; /*!< Timestamp value low */
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__IO uint32_t TTSH; /*!< Timestamp value high */
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} TRAN_DESC_ENH_T;
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/* Structure of a receive descriptor (without timestamp) */
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typedef struct
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{
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__IO uint32_t STATUS; /*!< RDES status word */
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__IO uint32_t CTRL; /*!< Buffer 1/2 byte counts and control */
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__IO uint32_t B1ADD; /*!< Buffer 1 address */
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__IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
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} REC_DESC_T;
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/* Structure of a enhanced receive descriptor (with timestamp) */
|
||
typedef struct
|
||
{
|
||
__IO uint32_t STATUS; /*!< RDES status word */
|
||
__IO uint32_t CTRL; /*!< Buffer 1/2 byte counts */
|
||
__IO uint32_t B1ADD; /*!< Buffer 1 address */
|
||
__IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
|
||
__IO uint32_t EXTSTAT; /*!< Extended Status */
|
||
__IO uint32_t RDES5; /*!< Reserved */
|
||
__IO uint32_t RTSL; /*!< Timestamp value low */
|
||
__IO uint32_t RTSH; /*!< Timestamp value high */
|
||
} REC_DESC_ENH_T;
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif
|
||
|
||
#endif /* __lpc18xx_lpc43xx_mac_regs_H_ */
|