410 lines
16 KiB
C
410 lines
16 KiB
C
/**************************************************************************/
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/*!
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@file dcd_lpc43xx.c
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@author hathach (tinyusb.org)
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@section LICENSE
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Software License Agreement (BSD License)
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Copyright (c) 2013, hathach (tinyusb.org)
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holders nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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#include "tusb_option.h"
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#if MODE_DEVICE_SUPPORTED && MCU == MCU_LPC43XX
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#define _TINY_USB_SOURCE_FILE_
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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#include "common/common.h"
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#include "hal/hal.h"
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#include "osal/osal.h"
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#include "common/timeout_timer.h"
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#include "dcd.h"
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#include "usbd_dcd.h"
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#include "dcd_lpc43xx.h"
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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#define DCD_QHD_MAX 12
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#define QTD_INVALID 0x01
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#define CONTROL_ENDOINT_SIZE 64
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typedef struct {
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// Word 0: Next QTD Pointer
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uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
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// Word 1: qTQ Token
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uint32_t : 3 ;
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volatile uint32_t xact_err : 1 ;
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uint32_t : 1 ;
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volatile uint32_t buffer_err : 1 ;
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volatile uint32_t halted : 1 ;
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volatile uint32_t active : 1 ;
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uint32_t : 2 ;
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uint32_t mult_override : 2 ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
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uint32_t : 3 ;
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uint32_t int_on_complete : 1 ;
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volatile uint32_t total_bytes : 15 ;
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uint32_t : 0 ;
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// Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
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uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
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//------------- -------------//
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uint32_t reserved;
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} dcd_qtd_t;
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STATIC_ASSERT( sizeof(dcd_qtd_t) == 32, "size is not correct");
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typedef struct {
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// Word 0: Capabilities and Characteristics
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uint32_t : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
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uint32_t int_on_setup : 1 ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
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uint32_t max_package_size : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
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uint32_t : 2 ;
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uint32_t zero_length_termination : 1 ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
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uint32_t mult : 2 ; ///<
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uint32_t : 0 ;
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// Word 1: Current qTD Pointer
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volatile uint32_t qtd_addr;
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// Word 2-9: Transfer Overlay
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volatile dcd_qtd_t qtd_overlay;
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// Word 10-11: Setup request (control OUT only)
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volatile tusb_control_request_t setup_request;
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//--------------------------------------------------------------------+
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/// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
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/// thus there are 16 bytes padding free that we can make use of.
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//--------------------------------------------------------------------+
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uint8_t reserved[16];
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} ATTR_ALIGNED(64) dcd_qhd_t;
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STATIC_ASSERT( sizeof(dcd_qhd_t) == 64, "size is not correct");
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typedef struct {
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dcd_qhd_t qhd[DCD_QHD_MAX]; ///< Must be at 2K alignment
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dcd_qtd_t qtd[DCD_QHD_MAX] ATTR_ALIGNED(32);
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}dcd_data_t;
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ATTR_ALIGNED(2048) dcd_data_t dcd_data;
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// USBD-DCD API
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//--------------------------------------------------------------------+
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tusb_error_t dcd_controller_reset(uint8_t coreid)
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{
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volatile uint32_t * p_reg_usbcmd;
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p_reg_usbcmd = (coreid ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
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// NXP chip powered with non-host mode --> sts bit is not correctly reflected
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(*p_reg_usbcmd) |= BIT_(1); // TODO refractor reset controller
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// timeout_timer_t timeout;
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// timeout_set(&timeout, 2); // should not take longer the time to stop controller
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while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !timeout_expired(&timeout)*/) {}
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//
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// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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return TUSB_ERROR_NONE;
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}
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void dcd_controller_connect(uint8_t coreid)
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{
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volatile uint32_t * p_reg_usbcmd = (coreid ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
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(*p_reg_usbcmd) |= BIT_(0);
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}
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/*---------- ENDPTCTRL ----------*/
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enum {
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ENDPTCTRL_MASK_STALL = BIT_(0),
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ENDPTCTRL_MASK_TOGGLE_INHIBIT = BIT_(5), ///< used for test only
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ENDPTCTRL_MASK_TOGGLE_RESET = BIT_(6),
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ENDPTCTRL_MASK_ENABLE = BIT_(7)
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};
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/*---------- USBCMD ----------*/
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enum {
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USBCMD_MASK_RUN_STOP = BIT_(0),
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USBCMD_MASK_RESET = BIT_(1),
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USBCMD_MASK_SETUP_TRIPWIRE = BIT_(13),
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USBCMD_MASK_ADD_QTD_TRIPWIRE = BIT_(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
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};
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// Interrupt Threshold bit 23:16
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/*---------- USBSTS, USBINTR ----------*/
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enum {
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INT_MASK_USB = BIT_(0),
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INT_MASK_ERROR = BIT_(1),
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INT_MASK_PORT_CHANGE = BIT_(2),
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INT_MASK_RESET = BIT_(6),
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INT_MASK_SOF = BIT_(7),
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INT_MASK_SUSPEND = BIT_(8),
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INT_MASK_NAK = BIT_(16)
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};
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//--------------------------------------------------------------------+
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// CONTROLLER API
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//--------------------------------------------------------------------+
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void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr)
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{
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LPC_USB0->DEVICEADDR = (dev_addr << 25) | BIT_(24);
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}
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void dcd_controller_set_configuration(uint8_t coreid, uint8_t config_num)
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{
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}
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/// follows LPC43xx User Manual 23.10.3
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void bus_reset(uint8_t coreid)
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{
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// TODO mutliple core id support
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//------------- Clear All Registers -------------//
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LPC_USB0->ENDPTNAK = LPC_USB0->ENDPTNAK;
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LPC_USB0->ENDPTNAKEN = 0;
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LPC_USB0->USBSTS_D = LPC_USB0->USBSTS_D;
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LPC_USB0->ENDPTSETUPSTAT = LPC_USB0->ENDPTSETUPSTAT;
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LPC_USB0->ENDPTCOMPLETE = LPC_USB0->ENDPTCOMPLETE;
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while (LPC_USB0->ENDPTPRIME);
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LPC_USB0->ENDPTFLUSH = 0xFFFFFFFF;
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while (LPC_USB0->ENDPTFLUSH);
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// read reset bit in portsc
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//------------- Queue Head & Queue TD -------------//
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memclr_(&dcd_data, sizeof(dcd_data_t));
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//------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
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dcd_data.qhd[0].zero_length_termination = dcd_data.qhd[1].zero_length_termination = 1;
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dcd_data.qhd[0].max_package_size = dcd_data.qhd[1].max_package_size = CONTROL_ENDOINT_SIZE;
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dcd_data.qhd[0].qtd_overlay.next = dcd_data.qhd[1].qtd_overlay.next = QTD_INVALID;
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dcd_data.qhd[0].int_on_setup = 1; // OUT only
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}
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tusb_error_t dcd_init(void)
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{
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/* Set the interrupt Threshold control interval to 0 */
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LPC_USB0->USBCMD_D &= ~0x00FF0000;
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/* Configure the Endpoint List Address */ /* make sure it in on 2K boundary !!! */
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LPC_USB0->ENDPOINTLISTADDR = (uint32_t) dcd_data.qhd;
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/* Enable interrupts: USB interrupt, error, port change, reset, suspend, NAK interrupt */
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LPC_USB0->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND; // | INT_MASK_SOF| INT_MASK_NAK;
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return TUSB_ERROR_NONE;
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}
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//--------------------------------------------------------------------+
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// PIPE API
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//--------------------------------------------------------------------+
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static inline uint8_t endpoint_to_pos(uint8_t logical_endpoint, tusb_direction_t dir) ATTR_CONST ATTR_ALWAYS_INLINE;
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static inline uint8_t endpoint_to_pos(uint8_t logical_endpoint, tusb_direction_t dir)
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{
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return logical_endpoint + (dir == TUSB_DIR_HOST_TO_DEV ? 0 : 16);
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}
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static inline uint8_t endpoint_phy2pos(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
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static inline uint8_t endpoint_phy2pos(uint8_t physical_endpoint)
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{
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return physical_endpoint/2 + ( (physical_endpoint%2) ? 16 : 0);
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}
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static inline uint8_t endpoint_log2phy(uint8_t logical_endpoint, tusb_direction_t dir) ATTR_CONST ATTR_ALWAYS_INLINE;
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static inline uint8_t endpoint_log2phy(uint8_t logical_endpoint, tusb_direction_t dir)
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{
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return 2*logical_endpoint + (dir == TUSB_DIR_DEV_TO_HOST ? 1 : 0);
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}
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static inline uint8_t endpoint_addr2phy(uint8_t endpoint_addr) ATTR_CONST ATTR_ALWAYS_INLINE;
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static inline uint8_t endpoint_addr2phy(uint8_t endpoint_addr)
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{
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return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 1 : 0);
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}
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static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
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{
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memclr_(p_qtd, sizeof(dcd_qtd_t));
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p_qtd->next = QTD_INVALID;
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p_qtd->active = 1;
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p_qtd->total_bytes = total_bytes;
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if (data_ptr != NULL)
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{
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p_qtd->buffer[0] = (uint32_t) data_ptr;
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for(uint8_t i=1; i<5; i++)
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{
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p_qtd->buffer[i] |= align4k( p_qtd->buffer[i-1] ) + 4096;
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}
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}
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}
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * buffer, uint16_t length)
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{
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uint8_t const endpoint_data = (dir == TUSB_DIR_DEV_TO_HOST) ? 1 : 0; // IN xfer --> data phase on Control IN, other Control OUT
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//------------- Data Phase -------------//
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if (length)
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{
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dcd_qtd_t* p_data = &dcd_data.qtd[0];
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qtd_init(p_data, buffer, length);
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dcd_data.qhd[endpoint_data].qtd_overlay.next = (uint32_t) p_data;
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LPC_USB0->ENDPTPRIME |= BIT_( endpoint_phy2pos(endpoint_data) );
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}
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//------------- Status Phase (other endpoint, opposite direction) -------------//
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dcd_qtd_t* p_status = &dcd_data.qtd[1];
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qtd_init(p_status, NULL, 0); // zero length xfer
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dcd_data.qhd[1 - endpoint_data].qtd_overlay.next = (uint32_t) p_status;
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LPC_USB0->ENDPTPRIME |= BIT_( endpoint_phy2pos(1 - endpoint_data) );
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return TUSB_ERROR_NONE;
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}
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endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc)
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{
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// TODO USB1 only has 4 non-control enpoint (USB0 has 5)
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endpoint_handle_t const null_handle = { .coreid = 0, .xfer_type = 0, .index = 0 };
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if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
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return null_handle; // TODO not support ISO yet
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//------------- Prepare Queue Head -------------//
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uint8_t ep_idx = endpoint_addr2phy(p_endpoint_desc->bEndpointAddress);
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dcd_qhd_t * p_qhd = &dcd_data.qhd[ep_idx];
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memclr_(p_qhd, sizeof(dcd_qhd_t));
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p_qhd->zero_length_termination = 1;
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p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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p_qhd->qtd_overlay.next = QTD_INVALID;
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//------------- Endpoint Control Register -------------//
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volatile uint32_t * reg_control = (&LPC_USB0->ENDPTCTRL0) + (p_endpoint_desc->bEndpointAddress & 0x0f);
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(*reg_control) = ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << ((p_endpoint_desc->bEndpointAddress & TUSB_DIR_DEV_TO_HOST_MASK) ? 16 : 0);
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return (endpoint_handle_t) { .coreid = coreid, .xfer_type = p_endpoint_desc->bmAttributes.xfer, .index = ep_idx };
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}
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STATIC_ INLINE_ dcd_qhd_t* qhd_get_from_endpoint_handle(endpoint_handle_t edpt_hdl) ATTR_PURE ATTR_ALWAYS_INLINE;
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STATIC_ INLINE_ dcd_qhd_t* qhd_get_from_endpoint_handle(endpoint_handle_t edpt_hdl)
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{
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return &dcd_data.qhd[edpt_hdl.index];
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}
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bool dcd_pipe_is_busy(endpoint_handle_t edpt_hdl)
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{
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dcd_qhd_t* p_qhd = qhd_get_from_endpoint_handle(edpt_hdl);
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// LPC_USB0->ENDPTSTAT & endpoint_phy2pos(edpt_hdl.index)
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return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
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}
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tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
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{
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dcd_qhd_t* p_qhd = qhd_get_from_endpoint_handle(edpt_hdl);
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dcd_qtd_t* p_qtd = &dcd_data.qtd[edpt_hdl.index]; // TODO allocate qtd
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ASSERT(edpt_hdl.xfer_type != TUSB_XFER_ISOCHRONOUS, TUSB_ERROR_NOT_SUPPORTED_YET);
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//------------- Prepare qtd -------------//
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qtd_init(p_qtd, buffer, total_bytes);
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p_qtd->int_on_complete = int_on_complete;
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd;
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LPC_USB0->ENDPTPRIME |= BIT_( endpoint_phy2pos(edpt_hdl.index) ) ;
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return TUSB_ERROR_NONE;
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}
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//------------- Device Controller Driver's Interrupt Handler -------------//
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void dcd_isr(uint8_t coreid)
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{
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uint32_t int_status = LPC_USB0->USBSTS_D;
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int_status &= LPC_USB0->USBINTR_D;
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LPC_USB0->USBSTS_D = int_status; // Acknowledge handled interrupt
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if (int_status == 0) return;
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if (int_status & INT_MASK_RESET)
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{
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bus_reset(coreid);
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usbd_bus_reset(coreid);
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}
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if (int_status & INT_MASK_USB)
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{
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if (LPC_USB0->ENDPTSETUPSTAT)
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{
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tusb_control_request_t control_request = dcd_data.qhd[0].setup_request;
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LPC_USB0->ENDPTSETUPSTAT = LPC_USB0->ENDPTSETUPSTAT;
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usbd_setup_received_isr(coreid, &control_request);
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}
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if (LPC_USB0->ENDPTCOMPLETE)
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{
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// TransferCompleteISR(DeviceID);
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}
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}
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if (int_status & INT_MASK_SOF) { }
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if (int_status & INT_MASK_SUSPEND) { }
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if (int_status & INT_MASK_PORT_CHANGE) { }
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if (int_status & INT_MASK_NAK) { }
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if (int_status & INT_MASK_ERROR) ASSERT(false, VOID_RETURN);
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}
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//--------------------------------------------------------------------+
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// HELPER
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//--------------------------------------------------------------------+
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#endif
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