11059 lines
1.4 MiB
11059 lines
1.4 MiB
<!DOCTYPE Register_Definition_File>
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<Processor name="LPC176x5x" description="LPC176x/LPC175x M3">
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<RegisterGroup name="WDT" start="0x40000000" description="Watchdog Timer (WDT) ">
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<Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
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<Enum name="STOP" start="0" description="The watchdog timer is stopped." />
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<Enum name="RUN" start="1" description="The watchdog timer is running." />
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</BitField>
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<BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652.">
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<Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." />
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<Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." />
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</BitField>
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<BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, cleared by software." />
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<BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Cleared by software." />
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<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
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</Register>
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<Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="Count" description="Watchdog time-out interval." />
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</Register>
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<Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
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</Register>
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<Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="Count" description="Counter timer value." />
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</Register>
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<Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="2" name="CLKSEL" description="Selects source of WDT clock">
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<Enum name="IRC" start="0x0" description="IRC" />
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<Enum name="PCLK" start="0x1" description="Peripheral clock" />
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<Enum name="RTCOSC" start="0x2" description="RTC oscillator" />
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</BitField>
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<BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.">
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<Enum name="UNLOCKED" start="0" description="This bit is set to 0 on any reset. It cannot be cleared by software." />
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<Enum name="LOCKED" start="1" description="Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register
										cannot be modified." />
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</BitField>
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</Register>
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</RegisterGroup>
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<RegisterGroup name="TIMER0" start="0x40004000" description="Timer0/1/2/3 ">
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<Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
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<BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
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<BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
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<BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
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<BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
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<BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
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<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
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</Register>
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<Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
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<BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
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<BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
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</Register>
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<Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="TC" description="Timer counter value." />
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</Register>
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<Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
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</Register>
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<Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="PC" description="Prescale counter value." />
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</Register>
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<Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
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<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
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<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
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</BitField>
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<BitField start="1" size="1" name="MR0R" description="Reset on MR0">
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<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
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<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
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</BitField>
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<BitField start="2" size="1" name="MR0S" description="Stop on MR0">
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<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
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<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
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</BitField>
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<BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
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<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
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<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
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</BitField>
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<BitField start="4" size="1" name="MR1R" description="Reset on MR1">
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<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
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<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
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</BitField>
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<BitField start="5" size="1" name="MR1S" description="Stop on MR1">
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<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
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<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
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</BitField>
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<BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
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<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
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<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
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</BitField>
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<BitField start="7" size="1" name="MR2R" description="Reset on MR2">
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<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
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<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
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</BitField>
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<BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
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<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
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<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
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</BitField>
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<BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
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<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
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<Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
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</BitField>
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<BitField start="10" size="1" name="MR3R" description="Reset on MR3">
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<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
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<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
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</BitField>
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<BitField start="11" size="1" name="MR3S" description="Stop on MR3">
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<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
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<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
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</BitField>
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<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
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</Register>
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<Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
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</Register>
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<Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
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</Register>
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<Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
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</Register>
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<Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
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<Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
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<Enum name="DISABLE" start="0" description="This feature is disabled." />
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</BitField>
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<BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
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<Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
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<Enum name="DISABLE" start="0" description="This feature is disabled." />
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</BitField>
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<BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
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<Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
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<Enum name="DISABLE" start="0" description="This feature is disabled." />
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</BitField>
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<BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
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<Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
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<Enum name="DISABLE" start="0" description="This feature is disabled." />
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</BitField>
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<BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
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<Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
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<Enum name="DISABLE" start="0" description="This feature is disabled." />
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</BitField>
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<BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
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<Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
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<Enum name="DISABLE" start="0" description="This feature is disabled." />
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</BitField>
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<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
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</Register>
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<Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
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</Register>
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<Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
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</Register>
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<Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
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<BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
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<BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
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<BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
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<BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
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<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
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<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
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<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
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<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
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</BitField>
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<BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
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<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
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<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
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<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
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<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
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</BitField>
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<BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
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<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
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<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
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<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
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<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
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</BitField>
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<BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
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<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
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<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
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<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
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<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
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</BitField>
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<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
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<Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
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<Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
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<Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
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<Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
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</BitField>
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<BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
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<Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
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<Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
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</BitField>
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<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
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</Register>
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</RegisterGroup>
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<RegisterGroup name="TIMER1" start="0x40008000" description="Timer0/1/2/3 ">
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<Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
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<BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
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<BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
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<BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
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<BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
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<BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
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<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
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</Register>
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<Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
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<BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
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<BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
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|
</Register>
|
|
<Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="TC" description="Timer counter value." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PC" description="Prescale counter value." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
|
|
<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MR0R" description="Reset on MR0">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MR0S" description="Stop on MR0">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
|
|
<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="MR1R" description="Reset on MR1">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="MR1S" description="Stop on MR1">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
|
|
<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MR2R" description="Reset on MR2">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
|
|
<Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="MR3R" description="Reset on MR3">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="MR3S" description="Stop on MR3">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
|
|
<Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
|
|
<Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
|
|
<Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
|
|
<Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
|
|
<Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
|
|
<Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3 ">
|
|
<Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
|
|
<Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
|
|
<Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
|
|
<Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
|
|
<Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
|
|
<Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
|
|
<Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
|
|
</BitField>
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
|
|
<Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
|
|
<Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
|
|
<Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
|
|
<Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
|
|
<Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
|
|
<Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
|
|
</BitField>
|
|
<BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
|
|
<Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." />
|
|
<Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
|
|
<Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
|
|
<Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
|
|
<BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
|
|
<BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
|
|
<Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
|
|
<Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
|
|
<Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
|
|
<Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
|
|
<Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
|
|
<Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
|
|
<Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
|
|
<Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
|
|
<Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
|
|
<Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="WLS" description="Word Length Select.">
|
|
<Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
|
|
<Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
|
|
<Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
|
|
<Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SBS" description="Stop Bit Select">
|
|
<Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
|
|
<Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PE" description="Parity Enable.">
|
|
<Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
|
|
<Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PS" description="Parity Select">
|
|
<Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
|
|
<Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
|
|
<Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
|
|
<Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="BC" description="Break Control">
|
|
<Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
|
|
<Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
|
|
<Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
|
|
<Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
|
|
<Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
|
|
<Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
|
|
<Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Overrun error status is active." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Parity error status is active." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Framing error status is active." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
|
|
<Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
|
|
<Enum name="EMPTY" start="1" description="UnTHR is empty." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
|
|
<Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
|
|
<Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
|
|
<Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
|
|
<Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
|
|
<Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
|
|
<Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
|
|
<Enum name="MODE_0_" start="0" description="Mode 0." />
|
|
<Enum name="MODE_1_" start="1" description="Mode 1." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
|
|
<Enum name="NO_RESTART_" start="0" description="No restart." />
|
|
<Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
|
|
</BitField>
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
|
|
<Enum name="NO_IMPACT_" start="0" description="No impact." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
|
|
<Enum name="NO_IMPACT_" start="0" description="No impact." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
|
|
<BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="NMMEN" description="NMM enable.">
|
|
<Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
|
|
<Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
|
|
<Enum name="ENABLED" start="0" description="The receiver is enabled." />
|
|
<Enum name="DISABLED" start="1" description="The receiver is disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AADEN" description="AAD enable.">
|
|
<Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
|
|
<Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
|
|
<Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
|
|
<Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
|
|
<Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
|
|
<Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="UART1" start="0x40010000" description="UART1 ">
|
|
<Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
|
|
<Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
|
|
<Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
|
|
<Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
|
|
<Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
|
|
<Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
|
|
<Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
|
|
<Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." />
|
|
<Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." />
|
|
</BitField>
|
|
<BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
|
|
<Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." />
|
|
<Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
|
|
<Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
|
|
<Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
|
|
<Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
|
|
<Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
|
|
<Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
|
|
<Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
|
|
</BitField>
|
|
<BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
|
|
<Enum name="RLS" start="0x3" description="1 - Receive Line Status (RLS)." />
|
|
<Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." />
|
|
<Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
|
|
<Enum name="THRE" start="0x1" description="3 - THRE Interrupt." />
|
|
<Enum name="MODEM" start="0x0" description="4 - Modem Interrupt." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
|
|
<BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
|
|
<BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
|
|
<Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." />
|
|
<Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
|
|
<Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
|
|
<Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
|
|
<Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
|
|
<Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." />
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
|
|
<Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
|
|
<Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
|
|
<Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
|
|
<Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="WLS" description="Word Length Select.">
|
|
<Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
|
|
<Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
|
|
<Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
|
|
<Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
|
|
<Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
|
|
<Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PE" description="Parity Enable.">
|
|
<Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
|
|
<Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PS" description="Parity Select.">
|
|
<Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
|
|
<Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
|
|
<Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." />
|
|
<Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="BC" description="Break Control.">
|
|
<Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
|
|
<Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
|
|
<Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
|
|
<Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DTRCTRL" description="DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
|
|
<BitField start="1" size="1" name="RTSCTRL" description="RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
|
|
<Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
|
|
<Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="6" size="1" name="RTSEN" description="RTS enable.">
|
|
<Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
|
|
<Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CTSEN" description="CTS enable.">
|
|
<Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
|
|
<Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
|
|
<Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." />
|
|
<Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
|
|
<Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Overrun error status is active." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Parity error status is active." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Framing error status is active." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
|
|
<Enum name="VALID" start="0" description="THR contains valid data." />
|
|
<Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
|
|
<Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." />
|
|
<Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
|
|
<Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." />
|
|
<Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
|
|
<Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
|
|
<Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
|
|
<Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
|
|
<Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
|
|
<Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
|
|
<Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
|
|
<Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
|
|
<Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
|
|
<BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
|
|
<BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
|
|
<BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
|
|
<Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." />
|
|
<Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
|
|
<Enum name="MODE_0_" start="0" description="Mode 0." />
|
|
<Enum name="MODE_1_" start="1" description="Mode 1." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
|
|
<Enum name="NO_RESTART" start="0" description="No restart" />
|
|
<Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
|
|
</BitField>
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
|
|
<Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
|
|
<Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
|
|
<Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
|
|
<Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." />
|
|
<BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXDIS" description="Receive enable.">
|
|
<Enum name="ENABLED_" start="0" description="Enabled." />
|
|
<Enum name="DISABLED_" start="1" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable.">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="ENABLED_" start="1" description="Enabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="SEL" description="Direction control.">
|
|
<Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
|
|
<Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
|
|
<Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
|
|
<Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
|
|
<Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
|
|
<Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM1) ">
|
|
<Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
|
|
<BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
|
|
<BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
|
|
<BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
|
|
<BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
|
|
<BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
|
|
<BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
|
|
<BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CE" description="Counter Enable">
|
|
<Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
|
|
<Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CR" description="Counter Reset">
|
|
<Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
|
|
<Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="3" size="1" name="PWMEN" description="PWM Enable">
|
|
<Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
|
|
<Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1).">
|
|
<Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
|
|
<Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
|
|
</BitField>
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="TC" description="Timer counter value." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PC" description="Prescale counter value." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
|
|
</BitField>
|
|
<BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
|
|
</BitField>
|
|
<BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
|
|
</BitField>
|
|
<BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
|
|
</BitField>
|
|
<BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
|
|
<Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
|
|
<Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
|
|
<Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
|
|
<Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
|
|
<Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
|
|
<Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
|
|
<Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
|
|
<Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
|
|
<Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
|
|
<Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
|
|
<Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
|
|
<Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
|
|
</Register>
|
|
<Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
|
|
</Register>
|
|
<Register start="+0x040+0" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x040+4" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x040+8" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers
are continuously compared to the PWM counter in order to control PWM
output edges." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
|
|
<Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
|
|
<Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
|
|
</BitField>
|
|
<BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
|
|
<Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
|
|
<Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
|
|
</BitField>
|
|
<BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
|
|
<BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
|
|
<BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
|
|
<BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
|
|
<BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
|
|
<BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
|
|
<BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="MOD" description="Counter/ Timer Mode">
|
|
<Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
|
|
<Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
|
|
<Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
|
|
<Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
|
|
<Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface">
|
|
<Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
|
|
<BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
|
|
<BitField start="4" size="1" name="STO" description="STOP flag." />
|
|
<BitField start="5" size="1" name="STA" description="START flag." />
|
|
<BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
|
|
<BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
|
|
<BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
|
|
<BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
|
|
<Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
|
|
<Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
|
|
<Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
|
|
<Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
|
|
<Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." />
|
|
<Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SPI" start="0x40020000" description="SPI ">
|
|
<Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer.">
|
|
<Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.">
|
|
<Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." />
|
|
<Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CPOL" description="Clock polarity control.">
|
|
<Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." />
|
|
<Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="MSTR" description="Master mode select.">
|
|
<Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." />
|
|
<Enum name="MASTER" start="1" description="The SPI operates in Master mode." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred.">
|
|
<Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." />
|
|
<Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable.">
|
|
<Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." />
|
|
<Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." />
|
|
</BitField>
|
|
<BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:">
|
|
<Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" />
|
|
<Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" />
|
|
<Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" />
|
|
<Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" />
|
|
<Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" />
|
|
<Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" />
|
|
<Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" />
|
|
<Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" />
|
|
<Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." />
|
|
<BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." />
|
|
<BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." />
|
|
<BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." />
|
|
<BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." />
|
|
<BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." />
|
|
<BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC) ">
|
|
<Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
|
|
<BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
|
|
<BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
|
|
<Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." />
|
|
<Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
|
|
<Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
|
|
<Enum name="NO_EFFECT_" start="0" description="No effect." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
|
|
<BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
|
|
<Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." />
|
|
<Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5." />
|
|
</BitField>
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
|
|
<BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
|
|
<BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
|
|
<BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
|
|
<BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
|
|
<BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
|
|
<BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
|
|
<BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
|
|
<BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
|
|
<BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
|
|
<BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
|
|
<BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
|
|
<BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
|
|
<BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
|
|
<BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
|
|
<BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
|
|
<BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
|
|
<BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
|
|
<BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
|
|
<BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
|
|
<BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
|
|
<BitField start="17" size="1" name="CALDIR" description="Calibration direction">
|
|
<Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
|
|
<Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="GP" description="General purpose storage." />
|
|
</Register>
|
|
<Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="GP" description="General purpose storage." />
|
|
</Register>
|
|
<Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="GP" description="General purpose storage." />
|
|
</Register>
|
|
<Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="GP" description="General purpose storage." />
|
|
</Register>
|
|
<Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="GP" description="General purpose storage." />
|
|
</Register>
|
|
<Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." />
|
|
<BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO">
|
|
<Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P0INT" description="Port 0 GPIO interrupt pending.">
|
|
<Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." />
|
|
<Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="P2INT" description="Port 2 GPIO interrupt pending.">
|
|
<Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." />
|
|
<Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="31" size="1" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="31" size="1" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="31" size="1" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="31" size="1" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="31" size="1" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="PINCONNECT" start="0x4002C000" description="Pin connect block">
|
|
<Register start="+0x000" size="4" name="PINSEL0" access="Read/Write" description="Pin function select register 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P0_0" description="Pin function select P0.0.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.0" />
|
|
<Enum name="RD1" start="0x1" description="RD1" />
|
|
<Enum name="TXD3" start="0x2" description="TXD3" />
|
|
<Enum name="SDA1" start="0x3" description="SDA1" />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P0_1" description="Pin function select P0.1.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.1" />
|
|
<Enum name="TD1" start="0x1" description="TD1" />
|
|
<Enum name="RXD3" start="0x2" description="RXD3" />
|
|
<Enum name="SCL1" start="0x3" description="SCL1" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="P0_2" description="Pin function select P0.2.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.2" />
|
|
<Enum name="TXD0" start="0x1" description="TXD0" />
|
|
<Enum name="AD0" start="0x2" description="AD0.7" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="P0_3" description="Pin function select P0.3.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.3." />
|
|
<Enum name="RXD0" start="0x1" description="RXD0" />
|
|
<Enum name="AD0" start="0x2" description="AD0.6" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="P0_4" description="Pin function select P0.4.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.4." />
|
|
<Enum name="I2SRX_CLK" start="0x1" description="I2SRX_CLK" />
|
|
<Enum name="RD2" start="0x2" description="RD2" />
|
|
<Enum name="CAP2" start="0x3" description="CAP2.0" />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="P0_5" description="Pin function select P0.5.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.5." />
|
|
<Enum name="I2SRX_WS" start="0x1" description="I2SRX_WS" />
|
|
<Enum name="TD2" start="0x2" description="TD2" />
|
|
<Enum name="CAP2" start="0x3" description="CAP2.1" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="P0_6" description="Pin function select P0.6.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.6." />
|
|
<Enum name="I2SRX_SDA" start="0x1" description="I2SRX_SDA" />
|
|
<Enum name="SSEL1" start="0x2" description="SSEL1" />
|
|
<Enum name="MAT2" start="0x3" description="MAT2.0" />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="P0_7" description="Pin function select P0.7.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.7." />
|
|
<Enum name="I2STX_CLK" start="0x1" description="I2STX_CLK" />
|
|
<Enum name="SCK1" start="0x2" description="SCK1" />
|
|
<Enum name="MAT2" start="0x3" description="MAT2.1" />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="P0_8" description="Pin function select P0.8.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.8." />
|
|
<Enum name="I2STX_WS" start="0x1" description="I2STX_WS" />
|
|
<Enum name="MISO1" start="0x2" description="MISO1" />
|
|
<Enum name="MAT2" start="0x3" description="MAT2.2" />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P0_9" description="Pin function select P0.9.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.9" />
|
|
<Enum name="I2STX_SDA" start="0x1" description="I2STX_SDA" />
|
|
<Enum name="MOSI1" start="0x2" description="MOSI1" />
|
|
<Enum name="MAT2" start="0x3" description="MAT2.3" />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P0_10" description="Pin function select P0.10.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.10" />
|
|
<Enum name="TXD2" start="0x1" description="TXD2" />
|
|
<Enum name="SDA2" start="0x2" description="SDA2" />
|
|
<Enum name="MAT3" start="0x3" description="MAT3.0" />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="P0_11" description="Pin function select P0.11.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.11" />
|
|
<Enum name="RXD2" start="0x1" description="RXD2" />
|
|
<Enum name="SCL2" start="0x2" description="SCL2" />
|
|
<Enum name="MAT3" start="0x3" description="MAT3.1" />
|
|
</BitField>
|
|
<BitField start="24" size="6" name="RESERVED" description="Reserved." />
|
|
<BitField start="30" size="2" name="P0_15" description="Pin function select P0.15.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.15" />
|
|
<Enum name="TXD1" start="0x1" description="TXD1" />
|
|
<Enum name="SCK0" start="0x2" description="SCK0" />
|
|
<Enum name="SCK" start="0x3" description="SCK" />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="PINSEL1" access="Read/Write" description="Pin function select register 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P0_16" description="Pin function select P0.16.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.16" />
|
|
<Enum name="RXD1" start="0x1" description="RXD1" />
|
|
<Enum name="SSEL0" start="0x2" description="SSEL0" />
|
|
<Enum name="SSEL" start="0x3" description="SSEL" />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P0_17" description="Pin function select P0.17.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.17" />
|
|
<Enum name="CTS1" start="0x1" description="CTS1" />
|
|
<Enum name="MISO0" start="0x2" description="MISO0" />
|
|
<Enum name="MISO" start="0x3" description="MISO" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="P0_18" description="Pin function select P0.18.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.18" />
|
|
<Enum name="DCD1" start="0x1" description="DCD1" />
|
|
<Enum name="MOSI0" start="0x2" description="MOSI0" />
|
|
<Enum name="MOSI" start="0x3" description="MOSI" />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="P0_19" description="Pin function select P019.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.19." />
|
|
<Enum name="DSR1" start="0x1" description="DSR1" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="SDA1" start="0x3" description="SDA1" />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="P0_20" description="Pin function select P0.20.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.20." />
|
|
<Enum name="DTR1" start="0x1" description="DTR1" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="SCL1" start="0x3" description="SCL1" />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="P0_21" description="Pin function select P0.21.">
|
|
<Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0.21." />
|
|
<Enum name="RI1" start="0x1" description="RI1" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RD1" start="0x3" description="RD1" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="P0_22" description="Pin function select P022">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.22." />
|
|
<Enum name="RTS1" start="0x1" description="RTS1" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="TD1" start="0x3" description="TD1" />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="P0_23" description="Pin function select P023.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.23." />
|
|
<Enum name="AD0" start="0x1" description="AD0.0" />
|
|
<Enum name="I2SRX_CLK" start="0x2" description="I2SRX_CLK" />
|
|
<Enum name="CAP3" start="0x3" description="CAP3.0" />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="P0_24" description="Pin function select P0.24.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.24." />
|
|
<Enum name="AD0" start="0x1" description="AD0.1" />
|
|
<Enum name="I2SRX_WS" start="0x2" description="I2SRX_WS" />
|
|
<Enum name="CAP3" start="0x3" description="CAP3.1" />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P0_25" description="Pin function select P0.25.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.25" />
|
|
<Enum name="AD0" start="0x1" description="AD0.2" />
|
|
<Enum name="I2SRX_SDA" start="0x2" description="I2SRX_SDA" />
|
|
<Enum name="TXD3" start="0x3" description="TXD3" />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P0_26" description="Pin function select P0.26.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.26" />
|
|
<Enum name="AD0" start="0x1" description="AD0.3" />
|
|
<Enum name="AOUT" start="0x2" description="AOUT" />
|
|
<Enum name="RXD3" start="0x3" description="RXD3" />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="P0_27" description="Pin function select P0.27.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.27" />
|
|
<Enum name="SDA0" start="0x1" description="SDA0" />
|
|
<Enum name="USB_SDA" start="0x2" description="USB_SDA" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="24" size="2" name="P0_28" description="Pin function select P0.28.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.28" />
|
|
<Enum name="SCL0" start="0x1" description="SCL0" />
|
|
<Enum name="USB_SCL" start="0x2" description="USB_SCL" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="26" size="2" name="P0_29" description="Pin function select P0.29">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.29" />
|
|
<Enum name="USB_DP" start="0x1" description="USB_D+" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="28" size="2" name="P0_30" description="Pin function select P0.30.">
|
|
<Enum name="GPIO_P0" start="0x0" description="GPIO P0.30" />
|
|
<Enum name="USB_DM" start="0x1" description="USB_D-" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="30" size="2" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="PINSEL2" access="Read/Write" description="Pin function select register 2." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P1_0" description="Pin function select P1.0.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.0" />
|
|
<Enum name="ENET_TXD0" start="0x1" description="ENET_TXD0" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P1_1" description="Pin function select P1.1.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.1" />
|
|
<Enum name="ENET_TXD1" start="0x1" description="ENET_TXD1" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="4" size="4" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="2" name="P1_4" description="Pin function select P1.4.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.4." />
|
|
<Enum name="ENET_TX_EN" start="0x1" description="ENET_TX_EN" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="10" size="6" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="2" name="P1_8" description="Pin function select P1.8.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.8." />
|
|
<Enum name="ENET_CRS" start="0x1" description="ENET_CRS" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P1_9" description="Pin function select P1.9.">
|
|
<Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.9" />
|
|
<Enum name="ENET_RXD0" start="0x1" description="ENET_RXD0" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P1_10" description="Pin function select P1.10.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.10" />
|
|
<Enum name="ENET_RXD1" start="0x1" description="ENET_RXD1" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="24" size="6" name="RESERVED" description="Reserved." />
|
|
<BitField start="22" size="2" name="P1_14" description="Pin function select P1.14.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.14" />
|
|
<Enum name="ENET_RX_ER" start="0x1" description="ENET_RX_ER" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="24" size="6" name="RESERVED" description="Reserved." />
|
|
<BitField start="30" size="2" name="P1_15" description="Pin function select P1.15.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.15" />
|
|
<Enum name="ENET_REF_CLK" start="0x1" description="ENET_REF_CLK" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="PINSEL3" access="Read/Write" description="Pin function select register 3." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P1_16" description="Pin function select P1.16.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.16" />
|
|
<Enum name="ENET_MDC" start="0x1" description="ENET_MDC" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P1_17" description="Pin function select P1.17.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.17" />
|
|
<Enum name="ENET_MDIO" start="0x1" description="ENET_MDIO" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="P1_18" description="Pin function select P1.18.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.18" />
|
|
<Enum name="USB_UP_LED" start="0x1" description="USB_UP_LED" />
|
|
<Enum name="PWM1" start="0x2" description="PWM1.1" />
|
|
<Enum name="CAP1" start="0x3" description="CAP1.0" />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="P1_19" description="Pin function select P1.19.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.19." />
|
|
<Enum name="MCOA0" start="0x1" description="MCOA0" />
|
|
<Enum name="USB_PPWR" start="0x2" description="USB_PPWR" />
|
|
<Enum name="CAP1" start="0x3" description="CAP1.1" />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="P1_20" description="Pin function select P1.20.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.20." />
|
|
<Enum name="MCI0" start="0x1" description="MCI0" />
|
|
<Enum name="PWM1" start="0x2" description="PWM1.2" />
|
|
<Enum name="SCK0" start="0x3" description="SCK0" />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="P1_21" description="Pin function select P1.21.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.21." />
|
|
<Enum name="MCABORT" start="0x1" description="MCABORT" />
|
|
<Enum name="PWM1" start="0x2" description="PWM1.3" />
|
|
<Enum name="SSEL0" start="0x3" description="SSEL0" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="P1_22" description="Pin function select P1.22">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.22." />
|
|
<Enum name="MCOB0" start="0x1" description="MCOB0" />
|
|
<Enum name="USB_PWRD" start="0x2" description="USB_PWRD" />
|
|
<Enum name="MAT1" start="0x3" description="MAT1.0" />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="P1_23" description="Pin function select P1.23.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.23." />
|
|
<Enum name="MCI1" start="0x1" description="MCI1" />
|
|
<Enum name="PWM1" start="0x2" description="PWM1.4" />
|
|
<Enum name="MISO0" start="0x3" description="MISO0" />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="P1_24" description="Pin function select P1.24.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.24." />
|
|
<Enum name="MCI2" start="0x1" description="MCI2" />
|
|
<Enum name="PWM1" start="0x2" description="PWM1.5" />
|
|
<Enum name="MOSI0" start="0x3" description="MOSI0" />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P1_25" description="Pin function select P1.25.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.25" />
|
|
<Enum name="MCOA1" start="0x1" description="MCOA1" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="MAT1" start="0x3" description="MAT1.1" />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P1_26" description="Pin function select P1.26.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.26" />
|
|
<Enum name="MCOB1" start="0x1" description="MCOB1" />
|
|
<Enum name="PWM1" start="0x2" description="PWM1.6" />
|
|
<Enum name="CAP0" start="0x3" description="CAP0.0" />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="P1_27" description="Pin function select P1.27.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.27" />
|
|
<Enum name="CLKOUT" start="0x1" description="CLKOUT" />
|
|
<Enum name="USB_OVRCR" start="0x2" description="USB_OVRCR" />
|
|
<Enum name="CAP0" start="0x3" description="CAP0.1" />
|
|
</BitField>
|
|
<BitField start="24" size="2" name="P1_28" description="Pin function select P1.28.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.28" />
|
|
<Enum name="MCOA2" start="0x1" description="MCOA2" />
|
|
<Enum name="PCAP1" start="0x2" description="PCAP1.0" />
|
|
<Enum name="MAT0" start="0x3" description="MAT0.0" />
|
|
</BitField>
|
|
<BitField start="26" size="2" name="P1_29" description="Pin function select P1.29">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.29" />
|
|
<Enum name="MCOB2" start="0x1" description="MCOB2" />
|
|
<Enum name="PCAP1" start="0x2" description="PCAP1.1" />
|
|
<Enum name="MAT0" start="0x3" description="MAT0.1" />
|
|
</BitField>
|
|
<BitField start="28" size="2" name="P1_30" description="Pin function select P1.30.">
|
|
<Enum name="GPIO_P1" start="0x0" description="GPIO P1.30" />
|
|
<Enum name="RESERVED" start="0x1" description="Reserved" />
|
|
<Enum name="VBUS" start="0x2" description="VBUS" />
|
|
<Enum name="AD0" start="0x3" description="AD0.4" />
|
|
</BitField>
|
|
<BitField start="30" size="2" name="P1_31" description="Pin function select P1.31.">
|
|
<Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.31" />
|
|
<Enum name="RESERVED" start="0x1" description="Reserved" />
|
|
<Enum name="SCK1" start="0x2" description="SCK1" />
|
|
<Enum name="AD0" start="0x3" description="AD0.5" />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PINSEL4" access="Read/Write" description="Pin function select register 4" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P2_0" description="Pin function select P2.0.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.0" />
|
|
<Enum name="PWM1" start="0x1" description="PWM1.1" />
|
|
<Enum name="TXD1" start="0x2" description="TXD1" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P2_1" description="Pin function select P2.1.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.1" />
|
|
<Enum name="PWM1" start="0x1" description="PWM1.2" />
|
|
<Enum name="RXD1" start="0x2" description="RXD1" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="P2_2" description="Pin function select P2.2.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.2" />
|
|
<Enum name="PWM1" start="0x1" description="PWM1.3" />
|
|
<Enum name="CTS1" start="0x2" description="CTS1" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="P2_3" description="Pin function select P2.3.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.3." />
|
|
<Enum name="PWM1" start="0x1" description="PWM1.4" />
|
|
<Enum name="DCD1" start="0x2" description="DCD1" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="P2_4" description="Pin function select P2.4.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.4." />
|
|
<Enum name="PWM1" start="0x1" description="PWM1.5" />
|
|
<Enum name="DSR1" start="0x2" description="DSR1" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="P2_5" description="Pin function select P2.5.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.5." />
|
|
<Enum name="PWM1" start="0x1" description="PWM1.6" />
|
|
<Enum name="DTR1" start="0x2" description="DTR1" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="P2_6" description="Pin function select P2.6.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.6." />
|
|
<Enum name="PCAP1" start="0x1" description="PCAP1.0" />
|
|
<Enum name="RI1" start="0x2" description="RI1" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="P2_7" description="Pin function select P2.7.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.7." />
|
|
<Enum name="RD2" start="0x1" description="RD2" />
|
|
<Enum name="RTS1" start="0x2" description="RTS1" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="P2_8" description="Pin function select P2.8.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.8." />
|
|
<Enum name="TD2" start="0x1" description="TD2" />
|
|
<Enum name="TXD2" start="0x2" description="TXD2" />
|
|
<Enum name="ENET_MDC" start="0x3" description="ENET_MDC" />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P2_9" description="Pin function select P2.9.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.9" />
|
|
<Enum name="USB_CONNECT" start="0x1" description="USB_CONNECT" />
|
|
<Enum name="RXD2" start="0x2" description="RXD2" />
|
|
<Enum name="ENET_MDIO" start="0x3" description="ENET_MDIO" />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P2_10" description="Pin function select P2.10.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.10" />
|
|
<Enum name="EINT0" start="0x1" description="EINT0" />
|
|
<Enum name="NMI" start="0x2" description="NMI" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="P2_11" description="Pin function select P2.11.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.11" />
|
|
<Enum name="EINT1" start="0x1" description="EINT1" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="I2STX_CLK" start="0x3" description="I2STX_CLK" />
|
|
</BitField>
|
|
<BitField start="24" size="2" name="P2_12" description="Pin function select P2.12.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.12" />
|
|
<Enum name="EINT2" start="0x1" description="EINT2" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="I2STX_WS" start="0x3" description="I2STX_WS" />
|
|
</BitField>
|
|
<BitField start="26" size="2" name="P2_13" description="Pin function select P2.13.">
|
|
<Enum name="GPIO_P2" start="0x0" description="GPIO P2.13" />
|
|
<Enum name="EINT3" start="0x1" description="EINT3" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="I2STX_SDA" start="0x3" description="I2STX_SDA" />
|
|
</BitField>
|
|
<BitField start="28" size="4" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="PINSEL7" access="Read/Write" description="Pin function select register 7" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="18" name="RESERVED" description="Reserved." />
|
|
<BitField start="18" size="2" name="P3_25" description="Pin function select P3.25.">
|
|
<Enum name="GPIO_P3" start="0x0" description="GPIO P3.25" />
|
|
<Enum name="RESERVED" start="0x1" description="Reserved" />
|
|
<Enum name="MAT0" start="0x2" description="MAT0.0" />
|
|
<Enum name="PWM1" start="0x3" description="PWM1.2" />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P3_26" description="Pin function select P3.26.">
|
|
<Enum name="GPIO_P3" start="0x0" description="GPIO P3.26" />
|
|
<Enum name="STCLK" start="0x1" description="STCLK" />
|
|
<Enum name="MAT0" start="0x2" description="MAT0.1" />
|
|
<Enum name="PWM1" start="0x3" description="PWM1.3" />
|
|
</BitField>
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="PINSEL9" access="Read/Write" description="Pin function select register 9" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="24" name="RESERVED" description="Reserved." />
|
|
<BitField start="24" size="2" name="P4_28" description="Pin function select P4.28.">
|
|
<Enum name="GPIO_P4" start="0x0" description="GPIO P4.28" />
|
|
<Enum name="RX_MCLK" start="0x1" description="RX_MCLK" />
|
|
<Enum name="MAT2" start="0x2" description="MAT2.0" />
|
|
<Enum name="TXD3" start="0x3" description="TXD3" />
|
|
</BitField>
|
|
<BitField start="26" size="2" name="P4_29" description="Pin function select P4.29.">
|
|
<Enum name="GPIO_P4" start="0x0" description="GPIO P4.29" />
|
|
<Enum name="TX_MCLK" start="0x1" description="TX_MCLK" />
|
|
<Enum name="MAT2" start="0x2" description="MAT2.1" />
|
|
<Enum name="RXD3" start="0x3" description="RXD3" />
|
|
</BitField>
|
|
<BitField start="28" size="4" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="PINSEL10" access="Read/Write" description="Pin function select register 10" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="RESERVED" description="Reserved. Software should not write 1 to these bits." />
|
|
<BitField start="3" size="1" name="TPIUCTRL" description="TPIU interface pins control.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. TPIU interface is disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Software should not write 1 to these bits." />
|
|
</Register>
|
|
<Register start="+0x040" size="4" name="PINMODE0" access="Read/Write" description="Pin mode select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P0_00MODE" description="Port 0 pin 0 on-chip pull-up/down resistor control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.0 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.0 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.0 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.0 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P0_01MODE" description="Port 0 pin 1 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.1 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.1 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.1 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.1 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="P0_02MODE" description="Port 0 pin 2 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.2 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.2 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.2 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.2 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="P0_03MODE" description="Port 0 pin 3 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.3 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.3 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.3 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.3 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="P0_04MODE" description="Port 0 pin 4 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.4 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.4 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.4 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.4 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="P0_05MODE" description="Port 0 pin 5 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.5 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.5 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.5 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.5 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="P0_06MODE" description="Port 0 pin 6 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.6 pin has a pull-up resistor enabled." />
|
|
<Enum name="DISABLED" start="0x1" description="Disabled. Repeater. P0.6 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.6 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.6 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="P0_07MODE" description="Port 0 pin 7 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.7 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.7 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.7 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.7 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="P0_08MODE" description="Port 0 pin 8 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.8 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.8 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.8 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.8 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P0_09MODE" description="Port 0 pin 9 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.9 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.9 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.9 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.9 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P0_10MODE" description="Port 0 pin 10 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.10 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.10 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.10 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.10 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="P0_11MODE" description="Port 0 pin 11 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.11 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.11 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.11 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.11 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="24" size="6" name="RESERVED" description="Reserved." />
|
|
<BitField start="30" size="2" name="P0_15MODE" description="Port 0 pin 15 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.15 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.15 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.15 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.15 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x044" size="4" name="PINMODE1" access="Read/Write" description="Pin mode select register 1" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P0_16MODE" description="Port 1 pin 16 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.16 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.16 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.16 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.16 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P0_17MODE" description="Port 1 pin 17 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.17 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.17 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.17 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.17 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="P0_18MODE" description="Port 1 pin 18 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.18 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.18 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.18 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.18 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="P0_19MODE" description="Port 1 pin 19 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.19 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.19 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.19 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.19 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="P0_20MODE" description="Port 1 pin 20 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.20 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.20 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.20 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.20 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="P0_21MODE" description="Port 1 pin 21 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.21 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.21 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.21 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.21 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="P0_22MODE" description="Port 1 pin 22 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.22 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.22 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.22 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.22 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="P0_23MODE" description="Port 1 pin 23 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.23 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.23 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.23 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.23 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="P0_24MODE" description="Port 1 pin 24 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.24 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.24 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.24 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.24 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P0_25MODE" description="Port 1 pin 25 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.25 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.25 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.25 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.25 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P0_26MODE" description="Port 1 pin 26 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P0.26 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P0.26 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P0.26 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.26 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="22" size="8" name="RESERVED" description="Reserved." />
|
|
<BitField start="30" size="2" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x048" size="4" name="PINMODE2" access="Read/Write" description="Pin mode select register 2" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P1_00MODE" description="Port 1 pin 0 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.0 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.0 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.0 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.0 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P1_01MODE" description="Port 1 pin 1 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.1 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.1 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.1 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.1 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="4" size="4" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="2" name="P1_04MODE" description="Port 1 pin 4 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.4 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.4 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.4 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.4 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="10" size="6" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="2" name="P1_08MODE" description="Port 1 pin 8 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.8 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.8 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.8 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.8 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P1_09MODE" description="Port 1 pin 9 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.9 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.9 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.9 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.9 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P1_10MODE" description="Port 1 pin 10 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.10 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.10 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.10 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.10 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="22" size="6" name="RESERVED" description="Reserved." />
|
|
<BitField start="28" size="2" name="P1_14MODE" description="Port 1 pin 14 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.14 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.14 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.14 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.14 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="30" size="2" name="P1_15MODE" description="Port 1 pin 15 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.15 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.15 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.15 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.15 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="PINMODE3" access="Read/Write" description="Pin mode select register 3." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P1_16MODE" description="Port 1 pin 16 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.16 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.16 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.16 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.16 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P1_17MODE" description="Port 1 pin 17 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.17 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.17 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.17 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.17 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="P1_18MODE" description="Port 1 pin 18 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.18 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.18 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.18 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.18 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="P1_19MODE" description="Port 1 pin 19 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.19 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.19 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.19 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.19 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="P1_20MODE" description="Port 1 pin 20 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.20 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.20 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.20 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.20 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="P1_21MODE" description="Port 1 pin 21 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.21 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.21 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.21 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.21 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="P1_22MODE" description="Port 1 pin 22 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.22 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.22 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.22 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.22 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="P1_23MODE" description="Port 1 pin 23 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.23 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.23 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.23 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.23 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="P1_24MODE" description="Port 1 pin 24 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.24 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.24 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.24 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.24 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P1_25MODE" description="Port 1 pin 25 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.25 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.25 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.25 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.25 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P1_26MODE" description="Port 1 pin 26 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.26 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.26 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.26 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.26 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="P1_27MODE" description="Port 1 pin 27 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.27 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.27 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.27 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.27 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="24" size="2" name="P1_28MODE" description="Port 1 pin 28 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.28 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.28 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.28 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.28 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="26" size="2" name="P1_29MODE" description="Port 1 pin 29 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.29 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.29 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.29 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.29 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="28" size="2" name="P1_30MODE" description="Port 1 pin 30 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.30 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.30 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.30 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.30 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="30" size="2" name="P1_31MODE" description="Port 1 pin 31 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P1.31 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P1.31 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P1.31 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.31 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="PINMODE4" access="Read/Write" description="Pin mode select register 4" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="P2_00MODE" description="Port 2 pin 0 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.0 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.0 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.0 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.0 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="P2_01MODE" description="Port 2 pin 1 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.1 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.1 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.1 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.1 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="P2_02MODE" description="Port 2 pin 2 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.2 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.2 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.2 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.2 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="P2_03MODE" description="Port 2 pin 3 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.3 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.3 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.3 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.3 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="P2_04MODE" description="Port 2 pin 4 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.4 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.4 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.4 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.4 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="P2_05MODE" description="Port 2 pin 5 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.5 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.5 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.5 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.5 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="P2_06MODE" description="Port 2 pin 6 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.6 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.6 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.6 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.6 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="P2_07MODE" description="Port 2 pin 7 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.7 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.7 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.7 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.7 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="P2_08MODE" description="Port 2 pin 8 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.8 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.8 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.8 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.8 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="P2_09MODE" description="Port 2 pin 9 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.9 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.9 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.9 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.9 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P2_10MODE" description="Port 2 pin 10 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.10 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.10 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.10 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.10 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="P2_11MODE" description="Port 2 pin 11 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.11 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.11 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.11 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.11 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="24" size="2" name="P2_12MODE" description="Port 2 pin 12 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.12 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.12 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.12 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.12 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="26" size="2" name="P2_13MODE" description="Port 2 pin 13 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P2.13 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P2.13 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P2.13 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.13 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="28" size="4" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x05C" size="4" name="PINMODE7" access="Read/Write" description="Pin mode select register 7" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="18" name="RESERVED" description="Reserved" />
|
|
<BitField start="18" size="2" name="P3_25MODE" description="Port 3 pin 25 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P3.25 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P3.25 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P3.25 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.25 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="P3_26MODE" description="Port 3 pin 26 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P3.26 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P3.26 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P3.26 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.26 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x064" size="4" name="PINMODE9" access="Read/Write" description="Pin mode select register 9" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="24" name="RESERVED" description="Reserved." />
|
|
<BitField start="24" size="2" name="P4_28MODE" description="Port 4 pin 28 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P4.28 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P4.28 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P4.28 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.28 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="26" size="2" name="P4_29MODE" description="Port 4 pin 29 control.">
|
|
<Enum name="PULL_UP" start="0x0" description="Pull-up. P4.29 pin has a pull-up resistor enabled." />
|
|
<Enum name="REPEATER" start="0x1" description="Repeater. P4.29 pin has repeater mode enabled." />
|
|
<Enum name="DISABLED" start="0x2" description="Disabled. P4.29 pin has neither pull-up nor pull-down." />
|
|
<Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.29 has a pull-down resistor enabled." />
|
|
</BitField>
|
|
<BitField start="28" size="4" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x068" size="4" name="PINMODE_OD0" access="Read/Write" description="Open drain mode control register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P0_00OD" description="Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.0 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.0 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="P0_01OD" description="Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.1 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.1 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="P0_02OD" description="Port 0 pin 2 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.2 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.2 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="P0_03OD" description="Port 0 pin 3 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.3 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.3 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="P0_04OD" description="Port 0 pin 4 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.4 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.4 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="P0_05OD" description="Port 0 pin 5 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.5 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.5 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="P0_06OD" description="Port 0 pin 6 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.6 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.6 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="P0_07OD" description="Port 0 pin 7 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.7 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.7 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="P0_08OD" description="Port 0 pin 8 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.8 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.8 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="P0_09OD" description="Port 0 pin 9 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.9 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.9 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="P0_10OD" description="Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.10 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.10 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="P0_11OD" description="Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.11 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.11 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="12" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="15" size="1" name="P0_15OD" description="Port 0 pin 15 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.15 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.15 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="16" size="1" name="P0_16OD" description="Port 0 pin 16 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.16 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.16 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="17" size="1" name="P0_17OD" description="Port 0 pin 17 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.17 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.17 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="18" size="1" name="P0_18OD" description="Port 0 pin 18 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.18 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.18 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="P0_19OD" description="Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.19 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.19 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="P0_20OD" description="Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.20 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.20 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="21" size="1" name="P0_21OD" description="Port 0 pin 21 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.21 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.21 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="P0_22OD" description="Port 0 pin 22 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.22 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.22 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="23" size="1" name="P0_23OD" description="Port 0 pin 23 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="24" size="1" name="P0_24OD" description="Port 0 pin 24open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="25" size="1" name="P0_25OD" description="Port 0 pin 25 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.25 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.25 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="26" size="1" name="P0_26OD" description="Port 0 pin 26 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.26 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.26 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="27" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="29" size="1" name="P0_29OD" description="Port 0 pin 29 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.29 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.29 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="30" size="1" name="P0_30OD" description="Port 0 pin 30 open drain mode control">
|
|
<Enum name="NORMAL" start="0" description="Normal. P0.30 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.30 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="31" size="1" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x06C" size="4" name="PINMODE_OD1" access="Read/Write" description="Open drain mode control register 1" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P1_00OD" description="Port 1 pin 0 open drain mode control.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.0 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.0 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="P1_01OD" description="Port 1 pin 1 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.1 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.1 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="4" size="1" name="P1_04OD" description="Port 1 pin 4 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.4 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.4 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="5" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="1" name="P1_08OD" description="Port 1 pin 8 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.8 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.8 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="P1_09OD" description="Port 1 pin 9 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.9 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.9 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="P1_10OD" description="Port 1 pin 10 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.10 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.10 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="14" size="1" name="P1_14OD" description="Port 1 pin 14 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.14 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.14 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="P1_15OD" description="Port 1 pin 15 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.15 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.15 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="16" size="1" name="P1_16OD" description="Port 1 pin 16 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.16 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.16 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="17" size="1" name="P1_17OD" description="Port 1 pin 17 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.17 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.17 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="18" size="1" name="P1_18OD" description="Port 1 pin 18 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.18 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.18 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="P1_19OD" description="Port 1 pin 19 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.19 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.19 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="P1_20OD" description="Port 1 pin 20open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.20 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.20 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="21" size="1" name="P1_21OD" description="Port 1 pin 21 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.21 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.21 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="P1_22OD" description="Port 1 pin 22 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.22 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.22 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="23" size="1" name="P1_23OD" description="Port 1 pin 23 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.23 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.23 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="24" size="1" name="P1_24OD" description="Port 1 pin 24open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.24 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.24 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="25" size="1" name="P1_25OD" description="Port 1 pin 25 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.25 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.25 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="26" size="1" name="P1_26OD" description="Port 1 pin 26 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.26 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.26 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="27" size="1" name="P1_27OD" description="Port 1 pin 27 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.27 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.27 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="28" size="1" name="P1_28OD" description="Port 1 pin 28 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.28 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.28 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="29" size="1" name="P1_29OD" description="Port 1 pin 29 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.29 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.29 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="30" size="1" name="P1_30OD" description="Port 1 pin 30 open drain mode control, see P1.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.30 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.30 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="31" size="1" name="P1_31OD" description="Port 1 pin 31 open drain mode control.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P1.31 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.31 pin is in the open drain mode." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="PINMODE_OD2" access="Read/Write" description="Open drain mode control register 2" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="P2_00OD" description="Port 2 pin 0 open drain mode control.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.0 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.0 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="P2_01OD" description="Port 2 pin 1 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.1 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.1p in is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="P2_02OD" description="Port 2 pin 2 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.2 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.2 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="P2_03OD" description="Port 2 pin 3 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.3 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.3 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="P2_04OD" description="Port 2 pin 4 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.4 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.4 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="P2_05OD" description="Port 2 pin 5 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.5 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.5 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="P2_06OD" description="Port 2 pin 6 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.6 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.6 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="P2_07OD" description="Port 2 pin 7 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.7 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.7 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="P2_08OD" description="Port 2 pin 8 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.8 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.8 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="P2_09OD" description="Port 2 pin 9 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.9 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.9 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="P2_10OD" description="Port 2 pin 10 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.10 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.10 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="P2_11OD" description="Port 2 pin 11 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.11 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.11 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="P2_12OD" description="Port 2 pin 12 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.12 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.12 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="P2_13OD" description="Port 2 pin 13 open drain mode control, see P2.00OD">
|
|
<Enum name="NORMAL" start="0" description="Normal. P2.13 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.13 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="14" size="18" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x074" size="4" name="PINMODE_OD3" access="Read/Write" description="Open drain mode control register 3" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="25" name="RESERVED" description="Reserved." />
|
|
<BitField start="25" size="1" name="P3_25OD" description="Port 3 pin 25 open drain mode control.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P3.25 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P3.25 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="26" size="1" name="P3_26OD" description="Port 3 pin 26 open drain mode control, see P3.25OD" />
|
|
<BitField start="27" size="5" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x078" size="4" name="PINMODE_OD4" access="Read/Write" description="Open drain mode control register 4" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="28" name="RESERVED" description="Reserved." />
|
|
<BitField start="28" size="1" name="P4_28OD" description="Port 4 pin 28 open drain mode control.">
|
|
<Enum name="NORMAL" start="0" description="Normal. P4.28 pin is in the normal (not open drain) mode." />
|
|
<Enum name="OPEN_DRAIN" start="1" description="Open-drain. P4.28 pin is in the open drain mode." />
|
|
</BitField>
|
|
<BitField start="29" size="1" name="P4_29OD" description="Port 4 pin 29 open drain mode control, see P4.28OD" />
|
|
<BitField start="30" size="2" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x07C" size="4" name="I2CPADCFG" access="Read/Write" description="I2C Pin Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SDADRV0" description="Drive mode control for the SDA0 pin, P0.27.">
|
|
<Enum name="STANDARD" start="0" description="Standard. The SDA0 pin is in the standard drive mode." />
|
|
<Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="SDAI2C0" description="I 2C filter mode control for the SDA0 pin, P0.27.">
|
|
<Enum name="ENABLED" start="0" description="Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled." />
|
|
<Enum name="DISABLED" start="1" description="Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SCLDRV0" description="Drive mode control for the SCL0 pin, P0.28.">
|
|
<Enum name="STANDARD" start="0" description="Standard. The SCL0 pin is in the standard drive mode." />
|
|
<Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="SCLI2C0" description="I 2C filter mode control for the SCL0 pin, P0.28.">
|
|
<Enum name="ENABLED" start="0" description="Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled." />
|
|
<Enum name="DISABLED" start="1" description="Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller">
|
|
<Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
|
|
<Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
|
|
<Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
|
|
<Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
|
|
<Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
|
|
<Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
|
|
<Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
|
|
<Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
|
|
<Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
|
|
<Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
|
|
<Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
|
|
<Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
|
|
<Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
|
|
<Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="FRF" description="Frame Format.">
|
|
<Enum name="SPI" start="0x0" description="SPI" />
|
|
<Enum name="TI" start="0x1" description="TI" />
|
|
<Enum name="MICROWIRE" start="0x2" description="Microwire" />
|
|
<Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
|
|
<Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
|
|
<Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
|
|
<Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
|
|
<Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
|
|
</BitField>
|
|
<BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
|
|
<Enum name="NORMAL" start="0" description="During normal operation." />
|
|
<Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="SSE" description="SSP Enable.">
|
|
<Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
|
|
<Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
|
|
<Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
|
|
<Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
|
|
<BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
|
|
<BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
|
|
<BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
|
|
<BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
|
|
<BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
|
|
<BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
|
|
<BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
|
|
<BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
|
|
<BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
|
|
<BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
|
|
<BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
|
|
<BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC) ">
|
|
<Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." />
|
|
<BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
|
|
<BitField start="16" size="1" name="BURST" description="Burst mode">
|
|
<Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." />
|
|
<Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." />
|
|
</BitField>
|
|
<BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="21" size="1" name="PDN" description="Power down mode">
|
|
<Enum name="POWERED" start="1" description="The A/D converter is operational." />
|
|
<Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:">
|
|
<Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
|
|
<Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
|
|
<Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." />
|
|
<Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." />
|
|
<Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." />
|
|
<Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." />
|
|
<Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." />
|
|
<Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." />
|
|
</BitField>
|
|
<BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:">
|
|
<Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." />
|
|
<Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." />
|
|
</BitField>
|
|
<BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." />
|
|
<BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." />
|
|
<BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable">
|
|
<Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." />
|
|
<Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable">
|
|
<Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." />
|
|
<Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable">
|
|
<Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." />
|
|
<Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable">
|
|
<Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." />
|
|
<Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable">
|
|
<Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." />
|
|
<Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable">
|
|
<Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." />
|
|
<Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable">
|
|
<Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." />
|
|
<Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable">
|
|
<Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." />
|
|
<Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable">
|
|
<Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." />
|
|
<Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." />
|
|
</BitField>
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
|
|
<BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
|
|
</Register>
|
|
<Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
|
|
<BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
|
|
</Register>
|
|
<Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
|
|
<BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
|
|
</Register>
|
|
<Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
|
|
<BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
|
|
</Register>
|
|
<Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
|
|
<BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
|
|
</Register>
|
|
<Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
|
|
<BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
|
|
</Register>
|
|
<Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
|
|
<BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
|
|
</Register>
|
|
<Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
|
|
<BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." />
|
|
<BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." />
|
|
<BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." />
|
|
<BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." />
|
|
<BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." />
|
|
<BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." />
|
|
<BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." />
|
|
<BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." />
|
|
<BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." />
|
|
<BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." />
|
|
<BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." />
|
|
<BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." />
|
|
<BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." />
|
|
<BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." />
|
|
<BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." />
|
|
<BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." />
|
|
<BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." />
|
|
<BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." />
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM">
|
|
<Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
<Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CANAF" start="0x4003C000" description=" CAN controller acceptance filter ">
|
|
<Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." />
|
|
<BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." />
|
|
<BitField start="2" size="1" name="EFCAN" description="FullCAN mode">
|
|
<Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." />
|
|
<Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." />
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." />
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." />
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CCAN" start="0x40040000" description="Central CAN controller ">
|
|
<Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." />
|
|
<BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" />
|
|
<BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." />
|
|
<BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." />
|
|
<BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." />
|
|
<BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." />
|
|
<BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." />
|
|
<BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." />
|
|
<BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." />
|
|
<BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." />
|
|
<BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" />
|
|
<BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" />
|
|
<BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." />
|
|
<BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CAN1" start="0x40044000" description="CAN1 controller ">
|
|
<Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RM" description="Reset Mode.">
|
|
<Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
|
|
<Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
|
|
<Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
|
|
<Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="STM" description="Self Test Mode.">
|
|
<Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
|
|
<Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
|
|
<Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
|
|
<Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SM" description="Sleep Mode.">
|
|
<Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
|
|
<Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
|
|
<Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
|
|
<Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="7" size="1" name="TM" description="Test Mode.">
|
|
<Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
|
|
<Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TR" description="Transmission Request.">
|
|
<Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
|
|
<Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="AT" description="Abort Transmission.">
|
|
<Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
|
|
<Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
|
|
<Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
|
|
<Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
|
|
<Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
|
|
<Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SRR" description="Self Reception Request.">
|
|
<Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
|
|
<Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
|
|
<Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
|
|
<Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
|
|
<Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
|
|
<Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
|
|
<Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
|
|
<Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
|
|
<Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
|
|
<Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
|
|
<Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
|
|
<Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
|
|
<Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
|
|
<Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
|
|
<Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
|
|
<Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
|
|
<Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
|
|
<Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
|
|
<Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
|
|
<Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
|
|
<Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
|
|
<Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
|
|
<Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
|
|
<Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
|
|
</BitField>
|
|
<BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
|
|
<BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
|
|
<BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
|
|
<Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
|
|
<Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
|
|
<Enum name="BIT_ERROR" start="0x0" description="Bit error" />
|
|
<Enum name="FORM_ERROR" start="0x1" description="Form error" />
|
|
<Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
|
|
<Enum name="OTHER_ERROR" start="0x3" description="Other error" />
|
|
</BitField>
|
|
<BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
|
|
<BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
|
|
<BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
|
|
<BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
|
|
<BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
|
|
<BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
|
|
<BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
|
|
<BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
|
|
<BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
|
|
<BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
|
|
<BitField start="23" size="1" name="SAM" description="Sampling">
|
|
<Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
|
|
<Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
|
|
</BitField>
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
|
|
<BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
|
|
<BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
|
|
<Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
|
|
<Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
|
|
<Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
|
|
<Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
|
|
<BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
|
|
<Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
|
|
<Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
|
|
<BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
|
|
<BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
|
|
<BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
|
|
<BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
|
|
<Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
|
|
<Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
|
|
<Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
|
|
<Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
|
|
<BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
|
|
<Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
|
|
<Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
|
|
<BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
|
|
<BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
|
|
<BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
|
|
<BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
|
|
<Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
|
|
<Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
|
|
<Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
|
|
<Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
|
|
<BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
|
|
<Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
|
|
<Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
|
|
<BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
|
|
<BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
|
|
<BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
|
|
<BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
|
|
<BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message." />
|
|
<BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message." />
|
|
<BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message." />
|
|
<BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message." />
|
|
<BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message." />
|
|
<BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message." />
|
|
<BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message." />
|
|
</Register>
|
|
<Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
|
|
<BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
|
|
<BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
|
|
<BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
|
|
</Register>
|
|
<Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
|
|
<BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
|
|
<BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
|
|
<BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
|
|
</Register>
|
|
<Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
|
|
<BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
|
|
<BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
|
|
<BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
|
|
</Register>
|
|
<Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CAN2" start="0x40048000" description="CAN1 controller ">
|
|
<Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RM" description="Reset Mode.">
|
|
<Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
|
|
<Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
|
|
<Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
|
|
<Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="STM" description="Self Test Mode.">
|
|
<Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
|
|
<Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
|
|
<Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
|
|
<Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SM" description="Sleep Mode.">
|
|
<Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
|
|
<Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
|
|
<Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
|
|
<Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="7" size="1" name="TM" description="Test Mode.">
|
|
<Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
|
|
<Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TR" description="Transmission Request.">
|
|
<Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
|
|
<Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="AT" description="Abort Transmission.">
|
|
<Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
|
|
<Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
|
|
<Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
|
|
<Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
|
|
<Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
|
|
<Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SRR" description="Self Reception Request.">
|
|
<Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
|
|
<Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
|
|
<Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
|
|
<Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
|
|
<Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
|
|
<Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
|
|
<Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
|
|
<Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
|
|
<Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
|
|
<Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
|
|
<Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
|
|
<Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
|
|
<Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
|
|
<Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
|
|
<Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
|
|
<Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
|
|
<Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
|
|
<Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
|
|
<Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
|
|
<Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
|
|
<Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
|
|
<Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
|
|
<Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
|
|
<Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
|
|
</BitField>
|
|
<BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
|
|
<BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
|
|
<Enum name="RESET" start="0" description="Reset" />
|
|
<Enum name="SET" start="1" description="Set" />
|
|
</BitField>
|
|
<BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
|
|
<BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
|
|
<Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
|
|
<Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
|
|
<Enum name="BIT_ERROR" start="0x0" description="Bit error" />
|
|
<Enum name="FORM_ERROR" start="0x1" description="Form error" />
|
|
<Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
|
|
<Enum name="OTHER_ERROR" start="0x3" description="Other error" />
|
|
</BitField>
|
|
<BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
|
|
<BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
|
|
<BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
|
|
<BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
|
|
<BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
|
|
<BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
|
|
<BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
|
|
<BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
|
|
<BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
|
|
<BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
|
|
<BitField start="23" size="1" name="SAM" description="Sampling">
|
|
<Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
|
|
<Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
|
|
</BitField>
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
|
|
<BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
|
|
<BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
|
|
<Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
|
|
<Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
|
|
<Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
|
|
<Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
|
|
<BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
|
|
<Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
|
|
<Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
|
|
<BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
|
|
<BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
|
|
<BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
|
|
<BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
|
|
<Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
|
|
<Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
|
|
<Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
|
|
<Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
|
|
<BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
|
|
<Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
|
|
<Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
|
|
<BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
|
|
<BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
|
|
<BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
|
|
<BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
|
|
<Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
|
|
<Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
|
|
<Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
|
|
<Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
|
|
<BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
|
|
<Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
|
|
<Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
|
|
<BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
|
|
<BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
|
|
<BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
|
|
<BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
|
|
<BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message." />
|
|
<BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message." />
|
|
<BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message." />
|
|
<BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message." />
|
|
<BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message." />
|
|
<BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message." />
|
|
<BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message." />
|
|
</Register>
|
|
<Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
|
|
<BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
|
|
<BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
|
|
<BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
|
|
</Register>
|
|
<Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
|
|
<BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
|
|
<BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
|
|
<BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
|
|
</Register>
|
|
<Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit
frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
|
|
<BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
|
|
<BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
|
|
<BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
|
|
</Register>
|
|
<Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit
Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit
data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
|
|
</Register>
|
|
<Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit
data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
|
|
<BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
|
|
<BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
|
|
<BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface">
|
|
<Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
|
|
<BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
|
|
<BitField start="4" size="1" name="STO" description="STOP flag." />
|
|
<BitField start="5" size="1" name="STA" description="START flag." />
|
|
<BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
|
|
<BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
|
|
<BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
|
|
<BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
|
|
<Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
|
|
<Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
|
|
<Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
|
|
<Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
|
|
<Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." />
|
|
<Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SSP0" start="0x40088000" description="SSP controller">
|
|
<Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
|
|
<Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
|
|
<Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
|
|
<Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
|
|
<Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
|
|
<Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
|
|
<Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
|
|
<Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
|
|
<Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
|
|
<Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
|
|
<Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
|
|
<Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
|
|
<Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
|
|
<Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="FRF" description="Frame Format.">
|
|
<Enum name="SPI" start="0x0" description="SPI" />
|
|
<Enum name="TI" start="0x1" description="TI" />
|
|
<Enum name="MICROWIRE" start="0x2" description="Microwire" />
|
|
<Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
|
|
<Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
|
|
<Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
|
|
<Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
|
|
<Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
|
|
</BitField>
|
|
<BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
|
|
<Enum name="NORMAL" start="0" description="During normal operation." />
|
|
<Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="SSE" description="SSP Enable.">
|
|
<Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
|
|
<Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
|
|
<Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
|
|
<Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
|
|
<BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
|
|
<BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
|
|
<BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
|
|
<BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
|
|
<BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
|
|
<BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
|
|
<BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
|
|
<BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
|
|
<BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
|
|
<BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
|
|
<BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
|
|
<BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="DAC" start="0x4008C000" description=" Digital-to-Analog Converter (DAC) ">
|
|
<Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN." />
|
|
<BitField start="16" size="1" name="BIAS" description="Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.">
|
|
<Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." />
|
|
<Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." />
|
|
</BitField>
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request">
|
|
<Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." />
|
|
<Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DMA_ENA" description="DMA access">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="TIMER2" start="0x40090000" description="Timer0/1/2/3 ">
|
|
<Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
|
|
<BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
|
|
<BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
|
|
<BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
|
|
<BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
|
|
<BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
|
|
<BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="TC" description="Timer counter value." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PC" description="Prescale counter value." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
|
|
<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MR0R" description="Reset on MR0">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MR0S" description="Stop on MR0">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
|
|
<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="MR1R" description="Reset on MR1">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="MR1S" description="Stop on MR1">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
|
|
<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MR2R" description="Reset on MR2">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
|
|
<Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="MR3R" description="Reset on MR3">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="MR3S" description="Stop on MR3">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
|
|
<Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
|
|
<Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
|
|
<Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
|
|
<Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
|
|
<Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
|
|
<Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="TIMER3" start="0x40094000" description="Timer0/1/2/3 ">
|
|
<Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
|
|
<BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
|
|
<BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
|
|
<BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
|
|
<BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
|
|
<BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
|
|
<BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="TC" description="Timer counter value." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PC" description="Prescale counter value." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
|
|
<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MR0R" description="Reset on MR0">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MR0S" description="Stop on MR0">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
|
|
<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="MR1R" description="Reset on MR1">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="MR1S" description="Stop on MR1">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
|
|
<Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MR2R" description="Reset on MR2">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
|
|
<Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
|
|
<Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="MR3R" description="Reset on MR3">
|
|
<Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="MR3S" description="Stop on MR3">
|
|
<Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
|
|
<Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
|
|
<Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
|
|
<Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
|
|
<Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
|
|
<Enum name="DISABLE" start="0" description="This feature is disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
|
|
<BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
|
|
<Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
|
|
<Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
|
|
<Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
|
|
<Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
|
|
<Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
|
|
<Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3 ">
|
|
<Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
|
|
<Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
|
|
<Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
|
|
<Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
|
|
<Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
|
|
<Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
|
|
<Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
|
|
</BitField>
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
|
|
<Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
|
|
<Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
|
|
<Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
|
|
<Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
|
|
<Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
|
|
<Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
|
|
</BitField>
|
|
<BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
|
|
<Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." />
|
|
<Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
|
|
<Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
|
|
<Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
|
|
<BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
|
|
<BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
|
|
<Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
|
|
<Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
|
|
<Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
|
|
<Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
|
|
<Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
|
|
<Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
|
|
<Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
|
|
<Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
|
|
<Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
|
|
<Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="WLS" description="Word Length Select.">
|
|
<Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
|
|
<Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
|
|
<Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
|
|
<Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SBS" description="Stop Bit Select">
|
|
<Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
|
|
<Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PE" description="Parity Enable.">
|
|
<Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
|
|
<Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PS" description="Parity Select">
|
|
<Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
|
|
<Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
|
|
<Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
|
|
<Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="BC" description="Break Control">
|
|
<Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
|
|
<Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
|
|
<Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
|
|
<Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
|
|
<Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
|
|
<Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
|
|
<Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Overrun error status is active." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Parity error status is active." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Framing error status is active." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
|
|
<Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
|
|
<Enum name="EMPTY" start="1" description="UnTHR is empty." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
|
|
<Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
|
|
<Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
|
|
<Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
|
|
<Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
|
|
<Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
|
|
<Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
|
|
<Enum name="MODE_0_" start="0" description="Mode 0." />
|
|
<Enum name="MODE_1_" start="1" description="Mode 1." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
|
|
<Enum name="NO_RESTART_" start="0" description="No restart." />
|
|
<Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
|
|
</BitField>
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
|
|
<Enum name="NO_IMPACT_" start="0" description="No impact." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
|
|
<Enum name="NO_IMPACT_" start="0" description="No impact." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
|
|
<BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="NMMEN" description="NMM enable.">
|
|
<Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
|
|
<Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
|
|
<Enum name="ENABLED" start="0" description="The receiver is enabled." />
|
|
<Enum name="DISABLED" start="1" description="The receiver is disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AADEN" description="AAD enable.">
|
|
<Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
|
|
<Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
|
|
<Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
|
|
<Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
|
|
<Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
|
|
<Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3 ">
|
|
<Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
|
|
<Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
|
|
<Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
|
|
<Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
|
|
<Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
|
|
<Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
|
|
<Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
|
|
</BitField>
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
|
|
<Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
|
|
<Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
|
|
<Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
|
|
<Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
|
|
<Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
|
|
<Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
|
|
</BitField>
|
|
<BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
|
|
<Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." />
|
|
<Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
|
|
<Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
|
|
<Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
|
|
<BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
|
|
<BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
|
|
<Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
|
|
<Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
|
|
<Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
|
|
<Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
|
|
<Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
|
|
<Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
|
|
<Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
|
|
<Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
|
|
<Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
|
|
<Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="WLS" description="Word Length Select.">
|
|
<Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
|
|
<Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
|
|
<Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
|
|
<Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SBS" description="Stop Bit Select">
|
|
<Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
|
|
<Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PE" description="Parity Enable.">
|
|
<Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
|
|
<Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PS" description="Parity Select">
|
|
<Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
|
|
<Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
|
|
<Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
|
|
<Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="BC" description="Break Control">
|
|
<Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
|
|
<Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
|
|
<Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
|
|
<Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
|
|
<Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
|
|
<Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
|
|
<Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Overrun error status is active." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Parity error status is active." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Framing error status is active." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
|
|
<Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
|
|
<Enum name="EMPTY" start="1" description="UnTHR is empty." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
|
|
<Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
|
|
<Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
|
|
<Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
|
|
<Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
|
|
<Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
|
|
<Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
|
|
<Enum name="MODE_0_" start="0" description="Mode 0." />
|
|
<Enum name="MODE_1_" start="1" description="Mode 1." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
|
|
<Enum name="NO_RESTART_" start="0" description="No restart." />
|
|
<Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
|
|
</BitField>
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
|
|
<Enum name="NO_IMPACT_" start="0" description="No impact." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
|
|
<Enum name="NO_IMPACT_" start="0" description="No impact." />
|
|
<Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
|
|
<BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="NMMEN" description="NMM enable.">
|
|
<Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
|
|
<Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
|
|
<Enum name="ENABLED" start="0" description="The receiver is enabled." />
|
|
<Enum name="DISABLED" start="1" description="The receiver is disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AADEN" description="AAD enable.">
|
|
<Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
|
|
<Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
|
|
<Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
|
|
<Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
|
|
<Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
|
|
<Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface">
|
|
<Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
|
|
<BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
|
|
<BitField start="4" size="1" name="STO" description="STOP flag." />
|
|
<BitField start="5" size="1" name="STA" description="START flag." />
|
|
<BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
|
|
<BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
|
|
<BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
|
|
<BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
|
|
<Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
|
|
<Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
|
|
<Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
|
|
<Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
|
|
<Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." />
|
|
<Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="I2S" start="0x400A8000" description="I2S interface">
|
|
<Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
|
|
<Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
|
|
<Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
|
|
<Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
|
|
<BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
|
|
<BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
|
|
<BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
|
|
<BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." />
|
|
<BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
|
|
<Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
|
|
<Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
|
|
<Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
|
|
<BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
|
|
<BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
|
|
<BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
|
|
<BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." />
|
|
<BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
|
|
<BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
|
|
<BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
|
|
<BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
|
|
<BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
|
|
<BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
|
|
<BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
|
|
<BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
|
|
<BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
|
|
<BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
|
|
<BitField start="2" size="6" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
|
|
<BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
|
|
<BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
|
|
<BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
|
|
<BitField start="2" size="6" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
|
|
<BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
|
|
<BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
|
|
<BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
|
|
<BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
|
|
<Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
|
|
<Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
|
|
<BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
|
|
<Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
|
|
<Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
|
|
<BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="RITIMER" start="0x400B0000" description="Repetitive Interrupt Timer (RIT) ">
|
|
<Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RITINT" description="Interrupt flag">
|
|
<Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
|
|
<Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
|
|
<Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
|
|
<Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
|
|
<Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
|
|
<Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="RITEN" description="Timer enable.">
|
|
<Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
|
|
<Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM">
|
|
<Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
|
|
<Enum name="STOP_" start="0" description="Stop." />
|
|
<Enum name="RUN_" start="1" description="Run." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
|
|
<Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
|
|
<Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
|
|
<Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
|
|
<Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
|
|
<Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
|
|
<Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
|
|
<Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
|
|
<Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
|
|
</BitField>
|
|
<BitField start="5" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
|
|
<Enum name="STOP_" start="0" description="Stop." />
|
|
<Enum name="RUN_" start="1" description="Run." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
|
|
<Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
|
|
<Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
|
|
<Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
|
|
<Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
|
|
<Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
|
|
<Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
|
|
<Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
|
|
<Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
|
|
<Enum name="STOP_" start="0" description="Stop." />
|
|
<Enum name="RUN_" start="1" description="Run." />
|
|
</BitField>
|
|
<BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
|
|
<Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
|
|
<Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
|
|
</BitField>
|
|
<BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
|
|
<Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
|
|
<Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
|
|
<Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
|
|
<Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
|
|
<Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
|
|
<Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
|
|
</BitField>
|
|
<BitField start="21" size="8" name="RESERVED" description="Reserved." />
|
|
<BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
|
|
<Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
|
|
<Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
|
|
</BitField>
|
|
<BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
|
|
<Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
|
|
<Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
|
|
</BitField>
|
|
<BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
|
|
<Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
|
|
<Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
<BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
<BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
|
|
<BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
|
|
<BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
|
|
<BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
|
|
<BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
|
|
<BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
|
|
<BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
|
|
<BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
|
|
<BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
|
|
<BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
|
|
<BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
|
|
<BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
|
|
<BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
|
|
<BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
|
|
<BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
|
|
<BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
|
|
<BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
|
|
<BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
|
|
<BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
|
|
<BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
|
|
<BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
|
|
<BitField start="21" size="11" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
|
|
<BitField start="21" size="11" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
|
|
<BitField start="21" size="11" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
|
|
</Register>
|
|
<Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MCLIM" description="Limit value." />
|
|
</Register>
|
|
<Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MCLIM" description="Limit value." />
|
|
</Register>
|
|
<Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MCLIM" description="Limit value." />
|
|
</Register>
|
|
<Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MCMAT" description="Match value." />
|
|
</Register>
|
|
<Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MCMAT" description="Match value." />
|
|
</Register>
|
|
<Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MCMAT" description="Match value." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
|
|
<BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
|
|
<BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
|
|
<BitField start="30" size="2" name="RESERVED" description="reserved" />
|
|
</Register>
|
|
<Register start="+0x040" size="4" name="CP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
|
|
<Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
|
|
<Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
|
|
<Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
|
|
<Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
|
|
<Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
|
|
<Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
|
|
<Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
|
|
<Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
|
|
<Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
|
|
<Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
|
|
<Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
|
|
<Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
|
|
</Register>
|
|
<Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
|
|
</Register>
|
|
<Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="11" size="4" name="RESERVED" description="Reserved." />
|
|
<BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
|
|
<Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
|
|
<Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="12" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="11" size="4" name="RESERVED" description="Reserved." />
|
|
<BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="11" size="4" name="RESERVED" description="Reserved." />
|
|
<BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
|
|
<Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
|
|
<Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="11" size="4" name="RESERVED" description="Reserved." />
|
|
<BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
|
|
<BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
|
|
<Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
|
|
<Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
|
|
<Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
|
|
<Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
|
|
<Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." />
|
|
<Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
|
|
<Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." />
|
|
<Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
|
|
<Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
|
|
<Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
|
|
<Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
|
|
<Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
|
|
<Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." />
|
|
<Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
|
|
<Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
|
|
<Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
|
|
<Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." />
|
|
<Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
|
|
<Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
|
|
<Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
|
|
<Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." />
|
|
<Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
|
|
<Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." />
|
|
<Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
|
|
<Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." />
|
|
<Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
|
|
<Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." />
|
|
<Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
|
|
<Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." />
|
|
<Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
|
|
<Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." />
|
|
<Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
|
|
</BitField>
|
|
<BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
|
|
<Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." />
|
|
<Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
|
|
</BitField>
|
|
<BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
|
|
<Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." />
|
|
<Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
|
|
</BitField>
|
|
<BitField start="18" size="11" name="RESERVED" description="Reserved." />
|
|
<BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
|
|
<Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
|
|
<Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
|
|
</BitField>
|
|
<BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
|
|
<Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
|
|
<Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
|
|
</BitField>
|
|
<BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
|
|
<Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
|
|
<Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="18" size="11" name="RESERVED" description="Reserved." />
|
|
<BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
<BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
|
|
</Register>
|
|
<Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="18" size="11" name="RESERVED" description="Reserved." />
|
|
<BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
<BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
|
|
</Register>
|
|
<Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
|
|
<BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
|
|
<BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI) ">
|
|
<Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
|
|
<BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." />
|
|
<BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." />
|
|
<BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." />
|
|
<BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." />
|
|
<BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
|
|
<BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." />
|
|
<BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." />
|
|
<BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." />
|
|
<BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." />
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="POS" description="Current position value." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="ENCPOS" description="Current index counter value." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="ICMP0" description="Index compare value 0." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
|
|
</Register>
|
|
<Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="VELCAP" description="Last velocity capture." />
|
|
</Register>
|
|
<Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="FILTER" access="Read/Write" description="Digital filter register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay." />
|
|
</Register>
|
|
<Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." />
|
|
<BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" />
|
|
<BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." />
|
|
<BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." />
|
|
<BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." />
|
|
<BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." />
|
|
<BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." />
|
|
<BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." />
|
|
<BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." />
|
|
<BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." />
|
|
<BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." />
|
|
<BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." />
|
|
<BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." />
|
|
<BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." />
|
|
<BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." />
|
|
<BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." />
|
|
<BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." />
|
|
<BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." />
|
|
<BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." />
|
|
<BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." />
|
|
<BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." />
|
|
<BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." />
|
|
<BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." />
|
|
<BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." />
|
|
<BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." />
|
|
<BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." />
|
|
<BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." />
|
|
<BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." />
|
|
<BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." />
|
|
<BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." />
|
|
<BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." />
|
|
<BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." />
|
|
<BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." />
|
|
<BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." />
|
|
<BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." />
|
|
<BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." />
|
|
<BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." />
|
|
<BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." />
|
|
<BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." />
|
|
<BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." />
|
|
<BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." />
|
|
<BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." />
|
|
<BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." />
|
|
<BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." />
|
|
<BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." />
|
|
<BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." />
|
|
<BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." />
|
|
<BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." />
|
|
<BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." />
|
|
<BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." />
|
|
<BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." />
|
|
<BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." />
|
|
<BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." />
|
|
<BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." />
|
|
<BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." />
|
|
<BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." />
|
|
<BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." />
|
|
<BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." />
|
|
<BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." />
|
|
<BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." />
|
|
<BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." />
|
|
<BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." />
|
|
<BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." />
|
|
<BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." />
|
|
<BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." />
|
|
<BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." />
|
|
<BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." />
|
|
<BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." />
|
|
<BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." />
|
|
<BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." />
|
|
<BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." />
|
|
<BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." />
|
|
<BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." />
|
|
<BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." />
|
|
<BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." />
|
|
<BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." />
|
|
<BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." />
|
|
<BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." />
|
|
<BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." />
|
|
<BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." />
|
|
<BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." />
|
|
<BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." />
|
|
<BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." />
|
|
<BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." />
|
|
<BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." />
|
|
<BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." />
|
|
<BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." />
|
|
<BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." />
|
|
<BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." />
|
|
<BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." />
|
|
<BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SYSCON" start="0x400FC000" description="System and clock control">
|
|
<Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0x303A" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." />
|
|
<BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved.">
|
|
<Enum name="1CLK" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock." />
|
|
<Enum name="2CLK" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock." />
|
|
<Enum name="3CLK" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock." />
|
|
<Enum name="4CLK" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock." />
|
|
<Enum name="5CLK" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only." />
|
|
<Enum name="6CLK" start="0x5" description="Flash accesses use 6 CPU clocks. This safe setting will work under any conditions." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x080" size="4" name="PLL0CON" access="Read/Write" description="PLL0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PLLE0" description="PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register." />
|
|
<BitField start="1" size="1" name="PLLC0" description="PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x084" size="4" name="PLL0CFG" access="Read/Write" description="PLL0 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="15" name="MSEL0" description="PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware." />
|
|
<BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="8" name="NSEL0" description="PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32." />
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x088" size="4" name="PLL0STAT" access="ReadOnly" description="PLL0 Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="15" name="MSEL0" description="Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier." />
|
|
<BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="16" size="8" name="NSEL0" description="Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider." />
|
|
<BitField start="24" size="1" name="PLLE0_STAT" description="Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered." />
|
|
<BitField start="25" size="1" name="PLLC0_STAT" description="Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered." />
|
|
<BitField start="26" size="1" name="PLOCK0" description="Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details." />
|
|
<BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x08C" size="4" name="PLL0FEED" access="WriteOnly" description="PLL0 Feed Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="PLL0FEED" description="The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x0A0" size="4" name="PLL1CON" access="Read/Write" description="PLL1 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PLLE1" description="PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency." />
|
|
<BitField start="1" size="1" name="PLLC1" description="PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x0A4" size="4" name="PLL1CFG" access="Read/Write" description="PLL1 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="MSEL1" description="PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations." />
|
|
<BitField start="5" size="2" name="PSEL1" description="PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x0A8" size="4" name="PLL1STAT" access="ReadOnly" description="PLL1 Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="MSEL1" description="Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1." />
|
|
<BitField start="5" size="2" name="PSEL1" description="Read-back for the PLL1 Divider value. This is the value currently used by PLL1." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="1" name="PLLE1_STAT" description="Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated." />
|
|
<BitField start="9" size="1" name="PLLC1_STAT" description="Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated." />
|
|
<BitField start="10" size="1" name="PLOCK1" description="Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x0AC" size="4" name="PLL1FEED" access="WriteOnly" description="PLL1 Feed Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="PLL1FEED" description="The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode." />
|
|
<BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode." />
|
|
<BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." />
|
|
<BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit." />
|
|
<BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled." />
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
|
|
<BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
|
|
<BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
|
|
<BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x0C4" size="4" name="PCONP" access="Read/Write" description="Power Control for Peripherals Register" reset_value="0x03BE" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." />
|
|
<BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." />
|
|
<BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." />
|
|
<BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." />
|
|
<BitField start="5" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." />
|
|
<BitField start="7" size="1" name="PCI2C0" description="The I2C0 interface power/clock control bit." />
|
|
<BitField start="8" size="1" name="PCSPI" description="The SPI interface power/clock control bit." />
|
|
<BitField start="9" size="1" name="PCRTC" description="The RTC power/clock control bit." />
|
|
<BitField start="10" size="1" name="PCSSP1" description="The SSP 1 interface power/clock control bit." />
|
|
<BitField start="11" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN." />
|
|
<BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." />
|
|
<BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." />
|
|
<BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." />
|
|
<BitField start="16" size="1" name="PCRIT" description="Repetitive Interrupt Timer power/clock control bit." />
|
|
<BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM" />
|
|
<BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." />
|
|
<BitField start="19" size="1" name="PCI2C1" description="The I2C1 interface power/clock control bit." />
|
|
<BitField start="20" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="21" size="1" name="PCSSP0" description="The SSP0 interface power/clock control bit." />
|
|
<BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." />
|
|
<BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." />
|
|
<BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." />
|
|
<BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." />
|
|
<BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." />
|
|
<BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." />
|
|
<BitField start="28" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." />
|
|
<BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." />
|
|
<BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." />
|
|
</Register>
|
|
<Register start="+0x104" size="4" name="CCLKCFG" access="Read/Write" description="CPU Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="CCLKSEL" description="Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x108" size="4" name="USBCLKCFG" access="Read/Write" description="USB Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="USBSEL" description="Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="CLKSRC" description="Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device.">
|
|
<Enum name="SELECTS_THE_INTERNAL" start="0x0" description="Selects the Internal RC oscillator as the PLL0 clock source (default)." />
|
|
<Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s." />
|
|
<Enum name="SELECTS_THE_RTC_OSCI" start="0x2" description="Selects the RTC oscillator as the PLL0 clock source." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved, do not use this setting." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." />
|
|
<BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." />
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." />
|
|
<BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." />
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
|
|
<BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
|
|
<BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
|
|
<BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EXTMODE0" description="External interrupt 0 EINT0 mode.">
|
|
<Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT0." />
|
|
<Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT0 is edge sensitive." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="EXTMODE1" description="External interrupt 1 EINT1 mode.">
|
|
<Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT1." />
|
|
<Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT1 is edge sensitive." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="EXTMODE2" description="External interrupt 2 EINT2 mode.">
|
|
<Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT2." />
|
|
<Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT2 is edge sensitive." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="EXTMODE3" description="External interrupt 3 EINT3 mode.">
|
|
<Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT3." />
|
|
<Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT3 is edge sensitive." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt 0 EINT0 polarity.">
|
|
<Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0)." />
|
|
<Enum name="RISING_EDGE" start="1" description="Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0)." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt 1 EINT1 polarity.">
|
|
<Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1)." />
|
|
<Enum name="RISING_EDGE" start="1" description="Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1)." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt 2 EINT2 polarity.">
|
|
<Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2)." />
|
|
<Enum name="RISING_EDGE" start="1" description="Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2)." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt 3 EINT3 polarity.">
|
|
<Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3)." />
|
|
<Enum name="RISING_EDGE" start="1" description="Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3)." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." />
|
|
<BitField start="1" size="1" name="EXTR" description="Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR." />
|
|
<BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." />
|
|
<BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System control and status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="4" size="1" name="OSCRANGE" description="Main oscillator range select.">
|
|
<Enum name="LOW" start="0" description="Low. The frequency range of the main oscillator is 1 MHz to 20 MHz." />
|
|
<Enum name="HIGH" start="1" description="High. The frequency range of the main oscillator is 15 MHz to 25 MHz." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OSCEN" description="Main oscillator enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The main oscillator is disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status.">
|
|
<Enum name="NOT_READY" start="0" description="Not ready. The main oscillator is not ready to be used as a clock source." />
|
|
<Enum name="READY" start="1" description="Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." />
|
|
</BitField>
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x1A8" size="4" name="PCLKSEL0" access="Read/Write" description="Peripheral Clock Selection register 0." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="PCLK_WDT" description="Peripheral clock selection for WDT.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="PCLK_TIMER0" description="Peripheral clock selection for TIMER0.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PCLK_TIMER1" description="Peripheral clock selection for TIMER1.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="PCLK_UART0" description="Peripheral clock selection for UART0.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="PCLK_UART1" description="Peripheral clock selection for UART1.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="12" size="2" name="PCLK_PWM1" description="Peripheral clock selection for PWM1.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="PCLK_I2C0" description="Peripheral clock selection for I2C0.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="PCLK_SPI" description="Peripheral clock selection for SPI.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="20" size="2" name="PCLK_SSP1" description="Peripheral clock selection for SSP1.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="PCLK_DAC" description="Peripheral clock selection for DAC.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="24" size="2" name="PCLK_ADC" description="Peripheral clock selection for ADC.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="26" size="2" name="PCLK_CAN1" description="Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6." />
|
|
</BitField>
|
|
<BitField start="28" size="2" name="PCLK_CAN2" description="Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6," />
|
|
</BitField>
|
|
<BitField start="30" size="2" name="PCLK_ACF" description="Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6" />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x1AC" size="4" name="PCLKSEL1" access="Read/Write" description="Peripheral Clock Selection register 1." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="PCLK_QEI" description="Peripheral clock selection for the Quadrature Encoder Interface.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="PCLK_GPIOINT" description="Peripheral clock selection for GPIO interrupts.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PCLK_PCB" description="Peripheral clock selection for the Pin Connect block.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="PCLK_I2C1" description="Peripheral clock selection for I2C1.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="2" name="PCLK_SSP0" description="Peripheral clock selection for SSP0.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="PCLK_TIMER2" description="Peripheral clock selection for TIMER2.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="PCLK_TIMER3" description="Peripheral clock selection for TIMER3.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="PCLK_UART2" description="Peripheral clock selection for UART2.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="18" size="2" name="PCLK_UART3" description="Peripheral clock selection for UART3.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="20" size="2" name="PCLK_I2C2" description="Peripheral clock selection for I2C2.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="22" size="2" name="PCLK_I2S" description="Peripheral clock selection for I2S.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="24" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="26" size="2" name="PCLK_RIT" description="Peripheral clock selection for Repetitive Interrupt Timer.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="28" size="2" name="PCLK_SYSCON" description="Peripheral clock selection for the System Control block.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
<BitField start="30" size="2" name="PCLK_MC" description="Peripheral clock selection for the Motor Control PWM.">
|
|
<Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
|
|
<Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
|
|
<Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
|
|
<Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." />
|
|
<BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." />
|
|
<BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." />
|
|
<BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." />
|
|
<BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." />
|
|
<BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." />
|
|
<BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only." />
|
|
<BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." />
|
|
</Register>
|
|
<Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DMASEL08" description="Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected." />
|
|
<BitField start="1" size="1" name="DMASEL09" description="Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected." />
|
|
<BitField start="2" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected." />
|
|
<BitField start="3" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected." />
|
|
<BitField start="4" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected." />
|
|
<BitField start="5" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected." />
|
|
<BitField start="6" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected." />
|
|
<BitField start="7" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. Other values are reserved. Do not use.">
|
|
<Enum name="SELECTS_THE_CPU_CLOC" start="0x0" description="Selects the CPU clock as the CLKOUT source." />
|
|
<Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the CLKOUT source." />
|
|
<Enum name="SELECTS_THE_INTERNAL" start="0x2" description="Selects the Internal RC oscillator as the CLKOUT source." />
|
|
<Enum name="SELECTS_THE_USB_CLOC" start="0x3" description="Selects the USB clock as the CLKOUT source." />
|
|
<Enum name="SELECTS_THE_RTC_OSCI" start="0x4" description="Selects the RTC oscillator as the CLKOUT source." />
|
|
</BitField>
|
|
<BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16." />
|
|
<BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." />
|
|
<BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="EMAC" start="0x50000000" description="Ethernet">
|
|
<Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." />
|
|
<BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." />
|
|
<BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." />
|
|
<BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." />
|
|
<BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." />
|
|
<BitField start="5" size="3" name="RESERVED" description="Unused" />
|
|
<BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." />
|
|
<BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." />
|
|
<BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." />
|
|
<BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." />
|
|
<BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." />
|
|
<BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." />
|
|
<BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." />
|
|
<BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." />
|
|
<BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." />
|
|
<BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." />
|
|
<BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
|
|
<BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
|
|
<BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." />
|
|
<BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." />
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." />
|
|
<BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." />
|
|
<BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." />
|
|
<BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" />
|
|
<BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." />
|
|
<BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="RESERVED" description="Unused" />
|
|
<BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." />
|
|
<BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." />
|
|
<BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." />
|
|
<BitField start="3" size="29" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." />
|
|
<BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." />
|
|
<BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." />
|
|
<BitField start="6" size="9" name="RESERVED" description="Unused" />
|
|
<BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." />
|
|
<BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." />
|
|
<BitField start="5" size="3" name="RESERVED" description="Unused" />
|
|
<BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." />
|
|
<BitField start="13" size="19" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." />
|
|
<BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." />
|
|
<BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." />
|
|
<BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." />
|
|
<BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." />
|
|
<BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." />
|
|
<BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXENABLE" description="Enable receive." />
|
|
<BitField start="1" size="1" name="TXENABLE" description="Enable transmit." />
|
|
<BitField start="2" size="1" name="RESERVED" description="Unused" />
|
|
<BitField start="3" size="1" name="REGRESET" description="When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." />
|
|
<BitField start="4" size="1" name="TXRESET" description="When a 1 is written, the transmit datapath is reset." />
|
|
<BitField start="5" size="1" name="RXRESET" description="When a 1 is written, the receive datapath is reset." />
|
|
<BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." />
|
|
<BitField start="7" size="1" name="PASSRXFILTER" description="When set to 1 , disables receive filtering i.e. all frames received are written to memory." />
|
|
<BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." />
|
|
<BitField start="9" size="1" name="RMII" description="When set to 1 , RMII mode is selected; if 0, MII mode is selected." />
|
|
<BitField start="10" size="1" name="FULLDUPLEX" description="When set to 1 , indicates full duplex operation." />
|
|
<BitField start="11" size="21" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." />
|
|
<BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
|
|
<BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." />
|
|
</Register>
|
|
<Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="RESERVED" description="Fixed to 000" />
|
|
<BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." />
|
|
</Register>
|
|
<Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
|
|
<BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." />
|
|
</Register>
|
|
<Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
|
|
<BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." />
|
|
</Register>
|
|
<Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
|
|
<BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
|
|
<BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
|
|
<BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." />
|
|
<BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." />
|
|
<BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." />
|
|
<BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." />
|
|
<BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." />
|
|
<BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." />
|
|
<BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." />
|
|
<BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." />
|
|
<BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." />
|
|
<BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." />
|
|
<BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
|
|
<BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
|
|
<BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." />
|
|
<BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
|
|
</Register>
|
|
<Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." />
|
|
<BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." />
|
|
<BitField start="20" size="12" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." />
|
|
<BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." />
|
|
<BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." />
|
|
<BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." />
|
|
<BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." />
|
|
<BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
|
|
<BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
|
|
<BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
|
|
<BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." />
|
|
<BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." />
|
|
<BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." />
|
|
<BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." />
|
|
<BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
|
|
<BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
|
|
<BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." />
|
|
<BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
|
|
<BitField start="31" size="1" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." />
|
|
<BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." />
|
|
</Register>
|
|
<Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." />
|
|
<BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." />
|
|
<BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." />
|
|
<BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." />
|
|
<BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." />
|
|
<BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." />
|
|
<BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." />
|
|
<BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." />
|
|
<BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." />
|
|
<BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." />
|
|
<BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." />
|
|
<BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." />
|
|
<BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." />
|
|
<BitField start="6" size="1" name="RESERVED" description="Unused" />
|
|
<BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." />
|
|
<BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
|
|
<BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
|
|
<BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
|
|
<BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
|
|
<BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
|
|
<BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
|
|
<BitField start="6" size="1" name="RESERVED" description="Unused" />
|
|
<BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
|
|
<BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." />
|
|
</Register>
|
|
<Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." />
|
|
</Register>
|
|
<Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." />
|
|
<BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." />
|
|
<BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
|
|
<BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
|
|
<BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." />
|
|
<BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." />
|
|
<BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
|
|
<BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
|
|
<BitField start="8" size="4" name="RESERVED" description="Unused" />
|
|
<BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." />
|
|
<BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." />
|
|
<BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." />
|
|
<BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
|
|
<BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
|
|
<BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." />
|
|
<BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." />
|
|
<BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
|
|
<BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
|
|
<BitField start="8" size="4" name="RESERVED" description="Unused" />
|
|
<BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." />
|
|
<BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="8" size="4" name="RESERVED" description="Unused" />
|
|
<BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="8" size="4" name="RESERVED" description="Unused" />
|
|
<BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
|
|
<BitField start="14" size="18" name="RESERVED" description="Unused" />
|
|
</Register>
|
|
<Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="31" name="RESERVED" description="Unused" />
|
|
<BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="GPDMA" start="0x50004000" description="General purpose DMA controller">
|
|
<Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
|
|
<BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
|
|
<BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
|
|
<BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
|
|
<BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
|
|
<BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
|
|
<BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
|
|
<BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
|
|
<BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
|
|
<BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
|
|
<BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
|
|
<BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
|
|
<BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
|
|
<BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
|
|
<BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
|
|
<BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
|
|
<BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
|
|
<BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
|
|
<BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
|
|
<BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
|
|
<BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
|
|
<BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
|
|
<BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
|
|
<BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
|
|
<BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
|
|
<BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
|
|
<BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
|
|
<BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
|
|
<BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." />
|
|
<BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
|
|
</Register>
|
|
<Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
|
|
</Register>
|
|
<Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
|
|
</Register>
|
|
<Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
|
|
</Register>
|
|
<Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
|
|
</Register>
|
|
<Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
|
|
</Register>
|
|
<Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
|
|
</Register>
|
|
<Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
|
|
</Register>
|
|
<Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
|
|
</Register>
|
|
<Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
|
|
</Register>
|
|
<Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
|
|
</Register>
|
|
<Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
|
|
</Register>
|
|
<Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
|
|
</Register>
|
|
<Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
|
|
</Register>
|
|
<Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
|
|
</Register>
|
|
<Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
|
|
</Register>
|
|
<Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
|
|
</Register>
|
|
<Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
|
|
</Register>
|
|
<Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
|
|
</Register>
|
|
<Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
|
|
</Register>
|
|
<Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
|
|
</Register>
|
|
<Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
|
|
</Register>
|
|
<Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
|
|
</Register>
|
|
<Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
|
|
</Register>
|
|
<Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
|
|
<BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
|
|
<BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
|
|
<BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
|
|
<BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
|
|
<BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
|
|
<BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
|
|
</Register>
|
|
<Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
|
|
<BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
|
|
<BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
|
|
<BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
|
|
<BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
|
|
<BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
|
|
<BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
|
|
</Register>
|
|
<Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
|
|
<BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
|
|
<BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
|
|
<BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
|
|
<BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
|
|
<BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
|
|
<BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
|
|
</Register>
|
|
<Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
|
|
<BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
|
|
<BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
|
|
<BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
|
|
<BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
|
|
<BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
|
|
<BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
|
|
</Register>
|
|
<Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
|
|
<BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
|
|
<BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
|
|
<BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
|
|
<BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
|
|
<BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
|
|
<BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
|
|
</Register>
|
|
<Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
|
|
<BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
|
|
<BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
|
|
<BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
|
|
<BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
|
|
<BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
|
|
<BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
|
|
</Register>
|
|
<Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
|
|
<BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
|
|
<BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
|
|
<BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
|
|
<BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
|
|
<BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
|
|
<BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
|
|
</Register>
|
|
<Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
|
|
<BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
|
|
<BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
|
|
<BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
|
|
<BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
|
|
<BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
|
|
<BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
|
|
<BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
|
|
<BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
|
|
<BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
|
|
</Register>
|
|
<Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
|
|
<BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
|
|
<BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
|
|
<BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
|
|
<BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
|
|
<BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
|
|
<BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
|
|
<BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
|
|
<BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
|
|
<BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
|
|
<BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
|
|
<BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
|
|
<BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
|
|
<BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
|
|
<BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
|
|
<BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
|
|
<BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
|
|
<BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
|
|
<BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
|
|
<BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
|
|
<BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
|
|
<BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
|
|
<BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
|
|
<BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
|
|
<BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
|
|
<BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
|
|
<BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
|
|
<BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
|
|
<BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
|
|
<BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
|
|
<BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
|
|
<BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
|
|
<BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
|
|
<BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
|
|
<BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
|
|
<BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
|
|
<BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
|
|
<BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
|
|
<BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
|
|
<BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
|
|
<BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
|
|
<BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
|
|
<BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
|
|
<BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
|
|
<BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
|
|
<BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
|
|
<BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
|
|
<BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
|
|
<BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
|
|
<BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
|
|
<BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
|
|
<BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
|
|
<BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
|
|
<BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
|
|
<BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
|
|
<BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
|
|
<BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
|
|
<BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
|
|
<BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
|
|
<BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
|
|
<BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
|
|
<BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
|
|
<BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
|
|
<BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
|
|
<BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="USB" start="0x50008000" description="USB device/host/OTG controller">
|
|
<Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TMR" description="Timer time-out." />
|
|
<BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." />
|
|
<BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." />
|
|
<BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." />
|
|
<BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." />
|
|
<BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." />
|
|
<BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
|
|
<BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
|
|
<BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
|
|
<BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x10C" size="4" name="INTCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
|
|
<BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
|
|
<BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
|
|
<BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x110" size="4" name="STCTRL" access="Read/Write" description="OTG Status and Control and USB port select" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="PORT_FUNC" description="Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." />
|
|
<BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" />
|
|
<BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" />
|
|
<BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." />
|
|
<BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
|
|
<BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
|
|
<BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
|
|
<BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." />
|
|
</Register>
|
|
<Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." />
|
|
<BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." />
|
|
<BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." />
|
|
<BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." />
|
|
<BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." />
|
|
<BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." />
|
|
<BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." />
|
|
<BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." />
|
|
<BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." />
|
|
<BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="8" name="CMD_PHASE" description="The command phase:">
|
|
<Enum name="READ" start="0x02" description="Read" />
|
|
<Enum name="WRITE" start="0x01" description="Write" />
|
|
<Enum name="COMMAND" start="0x05" description="Command" />
|
|
</BitField>
|
|
<BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." />
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="RX_DATA" description="Data received." />
|
|
</Register>
|
|
<Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="TX_DATA" description="Transmit Data." />
|
|
</Register>
|
|
<Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." />
|
|
<BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.">
|
|
<Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." />
|
|
<Enum name="DATA_IS_VALID_" start="1" description="Data is valid." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." />
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="ENABLED_" start="1" description="Enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="ENABLED_" start="1" description="Enabled." />
|
|
</BitField>
|
|
<BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FRAME" description="Frame interrupt routing">
|
|
<Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." />
|
|
<Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing">
|
|
<Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." />
|
|
<Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
<BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
|
|
</Register>
|
|
<Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
<BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
|
|
</Register>
|
|
<Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
<BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
|
|
</Register>
|
|
<Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
<BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
|
|
</Register>
|
|
<Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
<BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
|
|
</Register>
|
|
<Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
<BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
|
|
</Register>
|
|
<Register start="+0x248" size="4" name="EPIND" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="MPS" description="The maximum packet size value." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." />
|
|
<BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." />
|
|
<BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
<BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
|
|
</Register>
|
|
<Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
|
|
<BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
|
|
<BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
<BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
|
|
</Register>
|
|
<Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
|
|
<BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
|
|
<BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
<BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
|
|
</Register>
|
|
<Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." />
|
|
<BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." />
|
|
</Register>
|
|
<Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." />
|
|
<BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
|
|
<BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
<BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
|
|
</Register>
|
|
<Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." />
|
|
<BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
|
|
<BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." />
|
|
</Register>
|
|
<Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." />
|
|
<BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." />
|
|
<BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
<BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
|
|
</Register>
|
|
<Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit.">
|
|
<Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." />
|
|
<Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit.">
|
|
<Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." />
|
|
<Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ERR" description="System Error Interrupt bit.">
|
|
<Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." />
|
|
<Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit.">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="ENABLED_" start="1" description="Enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit.">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="ENABLED_" start="1" description="Enabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit.">
|
|
<Enum name="DISABLED_" start="0" description="Disabled." />
|
|
<Enum name="ENABLED_" start="1" description="Enabled." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
<BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
|
|
</Register>
|
|
<Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
</Register>
|
|
<Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
<BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
|
|
</Register>
|
|
<Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
<BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
|
|
</Register>
|
|
<Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
</Register>
|
|
<Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
<BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
|
|
</Register>
|
|
<Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
<BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
|
|
</Register>
|
|
<Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
</Register>
|
|
<Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
<BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
|
|
</Register>
|
|
<Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="RXDATA" description="Receive data." />
|
|
</Register>
|
|
<Register start="+0x300" size="4" name="I2C_WO" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="8" name="TXDATA" description="Transmit data." />
|
|
<BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." />
|
|
<BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.">
|
|
<Enum name="NOT_COMPLETE" start="0" description="Transaction has not completed." />
|
|
<Enum name="COMPLETE" start="1" description="Transaction completed." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.">
|
|
<Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." />
|
|
<Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.">
|
|
<Enum name="ACKNOWLEDGE_RCVD" start="0" description="Last transmission received an acknowledge." />
|
|
<Enum name="NO_ACKNOWLEDGE_RCVD" start="1" description="Last transmission did not receive an acknowledge." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.">
|
|
<Enum name="BUSY" start="0" description="Master transmitter does not need data." />
|
|
<Enum name="NEED_DATA" start="1" description="Master transmitter needs data." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.">
|
|
<Enum name="BUSY" start="0" description="Slave transmitter does not need data." />
|
|
<Enum name="NEED_DATA" start="1" description="Slave transmitter needs data." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." />
|
|
<BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." />
|
|
<BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." />
|
|
<BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.">
|
|
<Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" />
|
|
<Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.">
|
|
<Enum name="DATA" start="0" description="RX FIFO contains data." />
|
|
<Enum name="EMPTY" start="1" description="RX FIFO is empty" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.">
|
|
<Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." />
|
|
<Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.">
|
|
<Enum name="VALID_DATA" start="0" description="TX FIFO contains valid data." />
|
|
<Enum name="EMPTY" start="1" description="TX FIFO is empty" />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.">
|
|
<Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." />
|
|
<Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.">
|
|
<Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." />
|
|
<Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.">
|
|
<Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." />
|
|
<Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.">
|
|
<Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." />
|
|
<Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.">
|
|
<Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." />
|
|
<Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.">
|
|
<Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." />
|
|
<Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).">
|
|
<Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." />
|
|
<Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.">
|
|
<Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." />
|
|
<Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.">
|
|
<Enum name="NO_RESET" start="0" description="No reset." />
|
|
<Enum name="RESET" start="1" description="Reset the I2C to idle state. Self clearing." />
|
|
</BitField>
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0xFF4" size="4" name="USBCLKCTRL" access="Read/Write" description="USB Clock Control" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable. Enables the usbclk input to the device controller" />
|
|
<BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="3" size="1" name="PORTSEL_CLK_EN" description="Port select register clock enable." />
|
|
<BitField start="4" size="1" name="AHB_CLK_EN" description="AHB clock enable" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0xFF4" size="4" name="OTGCLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable">
|
|
<Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." />
|
|
<Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable">
|
|
<Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." />
|
|
<Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable">
|
|
<Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." />
|
|
<Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.">
|
|
<Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." />
|
|
<Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable">
|
|
<Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." />
|
|
<Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." />
|
|
</BitField>
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0xFF8" size="4" name="USBCLKST" access="ReadOnly" description="USB Clock Status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock on. The usbclk input to the device controller is active	." />
|
|
<BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="3" size="1" name="PORTSEL_CLK_ON" description="Port select register clock on." />
|
|
<BitField start="4" size="1" name="AHB_CLK_ON" description="AHB clock on." />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0xFF8" size="4" name="OTGCLKST" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status.">
|
|
<Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." />
|
|
<Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status.">
|
|
<Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." />
|
|
<Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status.">
|
|
<Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." />
|
|
<Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status.">
|
|
<Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." />
|
|
<Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status.">
|
|
<Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." />
|
|
<Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." />
|
|
</BitField>
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="GPIO" start="0x2009C000" description="General Purpose I/O ">
|
|
<Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
</Register>
|
|
<Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
|
|
<BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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</Register>
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<Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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</Register>
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<Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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</Register>
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|
<Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
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|
<BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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<BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
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</Register>
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<Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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</Register>
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|
<Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
</Register>
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|
<Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
</Register>
|
|
<Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
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|
<BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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|
<BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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</Register>
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<Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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<BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
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</Register>
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<Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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<BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
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</Register>
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<Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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</Register>
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<Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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|
<BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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</Register>
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<Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
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|
<BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
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<BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
</Register>
|
|
<Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
</Register>
|
|
<Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
<BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
|
|
<Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
|
|
<BitField name="WDT" start="0" size="1" />
|
|
<BitField name="TIMER0" start="1" size="1" />
|
|
<BitField name="TIMER1" start="2" size="1" />
|
|
<BitField name="TIMER2" start="3" size="1" />
|
|
<BitField name="TIMER3" start="4" size="1" />
|
|
<BitField name="UART0" start="5" size="1" />
|
|
<BitField name="UART1" start="6" size="1" />
|
|
<BitField name="UART2" start="7" size="1" />
|
|
<BitField name="UART3" start="8" size="1" />
|
|
<BitField name="PWM1" start="9" size="1" />
|
|
<BitField name="I2C0" start="10" size="1" />
|
|
<BitField name="I2C1" start="11" size="1" />
|
|
<BitField name="I2C2" start="12" size="1" />
|
|
<BitField name="SPI" start="13" size="1" />
|
|
<BitField name="SSP0" start="14" size="1" />
|
|
<BitField name="SSP1" start="15" size="1" />
|
|
<BitField name="PLL0" start="16" size="1" />
|
|
<BitField name="RTC" start="17" size="1" />
|
|
<BitField name="EINT0" start="18" size="1" />
|
|
<BitField name="EINT1" start="19" size="1" />
|
|
<BitField name="EINT2" start="20" size="1" />
|
|
<BitField name="EINT3" start="21" size="1" />
|
|
<BitField name="ADC" start="22" size="1" />
|
|
<BitField name="BOD" start="23" size="1" />
|
|
<BitField name="USB" start="24" size="1" />
|
|
<BitField name="CAN" start="25" size="1" />
|
|
<BitField name="DMA" start="26" size="1" />
|
|
<BitField name="I2S" start="27" size="1" />
|
|
<BitField name="ENET" start="28" size="1" />
|
|
<BitField name="RIT" start="29" size="1" />
|
|
<BitField name="MCPWM" start="30" size="1" />
|
|
<BitField name="QEI" start="31" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
|
|
<BitField name="PLL1" start="0" size="1" />
|
|
<BitField name="USBActivity" start="1" size="1" />
|
|
<BitField name="CANActivity" start="2" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
|
|
<BitField name="WDT" start="0" size="1" />
|
|
<BitField name="TIMER0" start="1" size="1" />
|
|
<BitField name="TIMER1" start="2" size="1" />
|
|
<BitField name="TIMER2" start="3" size="1" />
|
|
<BitField name="TIMER3" start="4" size="1" />
|
|
<BitField name="UART0" start="5" size="1" />
|
|
<BitField name="UART1" start="6" size="1" />
|
|
<BitField name="UART2" start="7" size="1" />
|
|
<BitField name="UART3" start="8" size="1" />
|
|
<BitField name="PWM1" start="9" size="1" />
|
|
<BitField name="I2C0" start="10" size="1" />
|
|
<BitField name="I2C1" start="11" size="1" />
|
|
<BitField name="I2C2" start="12" size="1" />
|
|
<BitField name="SPI" start="13" size="1" />
|
|
<BitField name="SSP0" start="14" size="1" />
|
|
<BitField name="SSP1" start="15" size="1" />
|
|
<BitField name="PLL0" start="16" size="1" />
|
|
<BitField name="RTC" start="17" size="1" />
|
|
<BitField name="EINT0" start="18" size="1" />
|
|
<BitField name="EINT1" start="19" size="1" />
|
|
<BitField name="EINT2" start="20" size="1" />
|
|
<BitField name="EINT3" start="21" size="1" />
|
|
<BitField name="ADC" start="22" size="1" />
|
|
<BitField name="BOD" start="23" size="1" />
|
|
<BitField name="USB" start="24" size="1" />
|
|
<BitField name="CAN" start="25" size="1" />
|
|
<BitField name="DMA" start="26" size="1" />
|
|
<BitField name="I2S" start="27" size="1" />
|
|
<BitField name="ENET" start="28" size="1" />
|
|
<BitField name="RIT" start="29" size="1" />
|
|
<BitField name="MCPWM" start="30" size="1" />
|
|
<BitField name="QEI" start="31" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
|
|
<BitField name="PLL1" start="0" size="1" />
|
|
<BitField name="USBActivity" start="1" size="1" />
|
|
<BitField name="CANActivity" start="2" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
|
|
<BitField name="WDT" start="0" size="1" />
|
|
<BitField name="TIMER0" start="1" size="1" />
|
|
<BitField name="TIMER1" start="2" size="1" />
|
|
<BitField name="TIMER2" start="3" size="1" />
|
|
<BitField name="TIMER3" start="4" size="1" />
|
|
<BitField name="UART0" start="5" size="1" />
|
|
<BitField name="UART1" start="6" size="1" />
|
|
<BitField name="UART2" start="7" size="1" />
|
|
<BitField name="UART3" start="8" size="1" />
|
|
<BitField name="PWM1" start="9" size="1" />
|
|
<BitField name="I2C0" start="10" size="1" />
|
|
<BitField name="I2C1" start="11" size="1" />
|
|
<BitField name="I2C2" start="12" size="1" />
|
|
<BitField name="SPI" start="13" size="1" />
|
|
<BitField name="SSP0" start="14" size="1" />
|
|
<BitField name="SSP1" start="15" size="1" />
|
|
<BitField name="PLL0" start="16" size="1" />
|
|
<BitField name="RTC" start="17" size="1" />
|
|
<BitField name="EINT0" start="18" size="1" />
|
|
<BitField name="EINT1" start="19" size="1" />
|
|
<BitField name="EINT2" start="20" size="1" />
|
|
<BitField name="EINT3" start="21" size="1" />
|
|
<BitField name="ADC" start="22" size="1" />
|
|
<BitField name="BOD" start="23" size="1" />
|
|
<BitField name="USB" start="24" size="1" />
|
|
<BitField name="CAN" start="25" size="1" />
|
|
<BitField name="DMA" start="26" size="1" />
|
|
<BitField name="I2S" start="27" size="1" />
|
|
<BitField name="ENET" start="28" size="1" />
|
|
<BitField name="RIT" start="29" size="1" />
|
|
<BitField name="MCPWM" start="30" size="1" />
|
|
<BitField name="QEI" start="31" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
|
|
<BitField name="PLL1" start="0" size="1" />
|
|
<BitField name="USBActivity" start="1" size="1" />
|
|
<BitField name="CANActivity" start="2" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
|
|
<BitField name="WDT" start="0" size="1" />
|
|
<BitField name="TIMER0" start="1" size="1" />
|
|
<BitField name="TIMER1" start="2" size="1" />
|
|
<BitField name="TIMER2" start="3" size="1" />
|
|
<BitField name="TIMER3" start="4" size="1" />
|
|
<BitField name="UART0" start="5" size="1" />
|
|
<BitField name="UART1" start="6" size="1" />
|
|
<BitField name="UART2" start="7" size="1" />
|
|
<BitField name="UART3" start="8" size="1" />
|
|
<BitField name="PWM1" start="9" size="1" />
|
|
<BitField name="I2C0" start="10" size="1" />
|
|
<BitField name="I2C1" start="11" size="1" />
|
|
<BitField name="I2C2" start="12" size="1" />
|
|
<BitField name="SPI" start="13" size="1" />
|
|
<BitField name="SSP0" start="14" size="1" />
|
|
<BitField name="SSP1" start="15" size="1" />
|
|
<BitField name="PLL0" start="16" size="1" />
|
|
<BitField name="RTC" start="17" size="1" />
|
|
<BitField name="EINT0" start="18" size="1" />
|
|
<BitField name="EINT1" start="19" size="1" />
|
|
<BitField name="EINT2" start="20" size="1" />
|
|
<BitField name="EINT3" start="21" size="1" />
|
|
<BitField name="ADC" start="22" size="1" />
|
|
<BitField name="BOD" start="23" size="1" />
|
|
<BitField name="USB" start="24" size="1" />
|
|
<BitField name="CAN" start="25" size="1" />
|
|
<BitField name="DMA" start="26" size="1" />
|
|
<BitField name="I2S" start="27" size="1" />
|
|
<BitField name="ENET" start="28" size="1" />
|
|
<BitField name="RIT" start="29" size="1" />
|
|
<BitField name="MCPWM" start="30" size="1" />
|
|
<BitField name="QEI" start="31" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
|
|
<BitField name="PLL1" start="0" size="1" />
|
|
<BitField name="USBActivity" start="1" size="1" />
|
|
<BitField name="CANActivity" start="2" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
|
|
<BitField name="WDT" start="0" size="1" />
|
|
<BitField name="TIMER0" start="1" size="1" />
|
|
<BitField name="TIMER1" start="2" size="1" />
|
|
<BitField name="TIMER2" start="3" size="1" />
|
|
<BitField name="TIMER3" start="4" size="1" />
|
|
<BitField name="UART0" start="5" size="1" />
|
|
<BitField name="UART1" start="6" size="1" />
|
|
<BitField name="UART2" start="7" size="1" />
|
|
<BitField name="UART3" start="8" size="1" />
|
|
<BitField name="PWM1" start="9" size="1" />
|
|
<BitField name="I2C0" start="10" size="1" />
|
|
<BitField name="I2C1" start="11" size="1" />
|
|
<BitField name="I2C2" start="12" size="1" />
|
|
<BitField name="SPI" start="13" size="1" />
|
|
<BitField name="SSP0" start="14" size="1" />
|
|
<BitField name="SSP1" start="15" size="1" />
|
|
<BitField name="PLL0" start="16" size="1" />
|
|
<BitField name="RTC" start="17" size="1" />
|
|
<BitField name="EINT0" start="18" size="1" />
|
|
<BitField name="EINT1" start="19" size="1" />
|
|
<BitField name="EINT2" start="20" size="1" />
|
|
<BitField name="EINT3" start="21" size="1" />
|
|
<BitField name="ADC" start="22" size="1" />
|
|
<BitField name="BOD" start="23" size="1" />
|
|
<BitField name="USB" start="24" size="1" />
|
|
<BitField name="CAN" start="25" size="1" />
|
|
<BitField name="DMA" start="26" size="1" />
|
|
<BitField name="I2S" start="27" size="1" />
|
|
<BitField name="ENET" start="28" size="1" />
|
|
<BitField name="RIT" start="29" size="1" />
|
|
<BitField name="MCPWM" start="30" size="1" />
|
|
<BitField name="QEI" start="31" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
|
|
<BitField name="PLL1" start="0" size="1" />
|
|
<BitField name="USBActivity" start="1" size="1" />
|
|
<BitField name="CANActivity" start="2" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
|
|
<BitField name="WDT" start="4" size="4" />
|
|
<BitField name="TIMER0" start="12" size="4" />
|
|
<BitField name="TIMER1" start="20" size="4" />
|
|
<BitField name="TIMER2" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
|
|
<BitField name="TIMER3" start="4" size="4" />
|
|
<BitField name="UART0" start="12" size="4" />
|
|
<BitField name="UART1" start="20" size="4" />
|
|
<BitField name="UART2" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
|
|
<BitField name="UART3" start="4" size="4" />
|
|
<BitField name="PWM1" start="12" size="4" />
|
|
<BitField name="I2C0" start="20" size="4" />
|
|
<BitField name="I2C1" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
|
|
<BitField name="I2C2" start="4" size="4" />
|
|
<BitField name="SPI" start="12" size="4" />
|
|
<BitField name="SSP0" start="20" size="4" />
|
|
<BitField name="SSP1" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
|
|
<BitField name="PLL0" start="4" size="4" />
|
|
<BitField name="RTC" start="12" size="4" />
|
|
<BitField name="EINT0" start="20" size="4" />
|
|
<BitField name="EINT1" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
|
|
<BitField name="EINT2" start="4" size="4" />
|
|
<BitField name="EINT3" start="12" size="4" />
|
|
<BitField name="ADC" start="20" size="4" />
|
|
<BitField name="BOD" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
|
|
<BitField name="USB" start="4" size="4" />
|
|
<BitField name="CAN" start="12" size="4" />
|
|
<BitField name="DMA" start="20" size="4" />
|
|
<BitField name="I2S" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
|
|
<BitField name="ENET" start="4" size="4" />
|
|
<BitField name="RIT" start="12" size="4" />
|
|
<BitField name="MCPWM" start="20" size="4" />
|
|
<BitField name="QEI" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
|
|
<BitField name="PLL1" start="4" size="4" />
|
|
<BitField name="USBActivity" start="12" size="4" />
|
|
<BitField name="CANActivity" start="20" size="4" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
|
|
<Register name="SYS_CSR" start="0xE000E010" description="SysTick Control and Status Register">
|
|
<BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
|
|
<BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
|
|
<BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
|
|
<BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
|
|
</Register>
|
|
<Register name="SYS_RVR" start="0xE000E014" description="SysTick Reload Value Register">
|
|
<BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
|
|
</Register>
|
|
<Register name="SYS_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
|
|
<BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
|
|
</Register>
|
|
<Register name="SYS_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
|
|
<BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
|
|
<BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
|
|
<BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SCB" start="" description="System Control Block">
|
|
<Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
|
|
<BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
|
|
<BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
|
|
</Register>
|
|
<Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
|
|
<BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
|
|
<BitField name="VARIANT" start="20" size="4" description="Variant Number" />
|
|
<BitField name="PARTNO" start="4" size="12" description="Part Number" />
|
|
<BitField name="REVISION" start="0" size="4" description="Revision Number" />
|
|
</Register>
|
|
<Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
|
|
<BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
|
|
<BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
|
|
<BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
|
|
<BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
|
|
<BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
|
|
<BitField name="ISRPREEMPT" start="23" size="1" description="" />
|
|
<BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
|
|
<BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
|
|
<BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
|
|
<BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
|
|
</Register>
|
|
<Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
|
|
<BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
|
|
</Register>
|
|
<Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
|
|
<BitField name="VECTKEY" start="16" size="16" description="Register key" />
|
|
<BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
|
|
<BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
|
|
<BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
|
|
<BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
|
|
<BitField name="VECTRESET" start="0" size="1" description="" />
|
|
</Register>
|
|
<Register name="SCR" start="0xE000ED10" description="System Control Register">
|
|
<BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
|
|
<BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
|
|
<BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
|
|
</Register>
|
|
<Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
|
|
<BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
|
|
<BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
|
|
<BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
|
|
<BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
|
|
<BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
|
|
<BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
|
|
</Register>
|
|
<Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
|
|
<BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
|
|
<BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
|
|
<BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
|
|
</Register>
|
|
<Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
|
|
<BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
|
|
</Register>
|
|
<Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
|
|
<BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
|
|
<BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
|
|
</Register>
|
|
<Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
|
|
<BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
|
|
<BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
|
|
<BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
|
|
<BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
|
|
<BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
|
|
<BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
|
|
<BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
|
|
<BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
|
|
<BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
|
|
<BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
|
|
<BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
|
|
<BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
|
|
<BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
|
|
<BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
|
|
</Register>
|
|
<Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
|
|
<BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
|
|
<BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
|
|
<BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
|
|
<BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
|
|
<BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
|
|
</Register>
|
|
<Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
|
|
<BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
|
|
<BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
|
|
<BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
|
|
<BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
|
|
<BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
|
|
<BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
|
|
</Register>
|
|
<Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
|
|
<BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
|
|
<BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
|
|
<BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
|
|
<BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
|
|
<BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
|
|
<BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
|
|
</Register>
|
|
<Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
|
|
<BitField name="DEBUGEVT" start="31" size="1" description="" />
|
|
<BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
|
|
<BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
|
|
</Register>
|
|
<Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
|
|
<BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
|
|
</Register>
|
|
<Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
|
|
<BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
|
|
</Register>
|
|
<Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
|
|
<BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
|
|
<Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
|
|
<BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
|
|
<BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
|
|
<BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
|
|
</Register>
|
|
<Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
|
|
<BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
|
|
<BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
|
|
<BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
|
|
</Register>
|
|
<Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
|
|
<BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
|
|
</Register>
|
|
<Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
|
|
<BitField name="ADDR" start="5" size="27" description="Region base address field" />
|
|
<BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
|
|
<BitField name="REGION" start="0" size="4" description="MPU region field" />
|
|
</Register>
|
|
<Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
|
|
<BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
|
|
<BitField name="AP" start="24" size="3" description="Access permission field" />
|
|
<BitField name="TEX" start="19" size="3" description="Memory access attribute" />
|
|
<BitField name="S" start="18" size="1" description="Shareable bit" />
|
|
<BitField name="C" start="17" size="1" description="Memory access attribute" />
|
|
<BitField name="B" start="16" size="1" description="Memory access attribute" />
|
|
<BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
|
|
<BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
|
|
<BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
</Processor>
|