317 lines
11 KiB
C
317 lines
11 KiB
C
/*
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* ehci.c
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*
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* Created on: Dec 2, 2012
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* Author: hathach
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*/
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/*
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* Software License Agreement (BSD License)
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* Copyright (c) 2013, hathach (tinyusb.net)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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* This file is part of the tiny usb stack.
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*/
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#include "common/common.h"
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#if MODE_HOST_SUPPORTED && (MCU == MCU_LPC43XX || MCU == MCU_LPC18XX)
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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#include "hal/hal.h"
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#include "osal/osal.h"
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#include "common/timeout_timer.h"
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#include "../hcd.h"
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#include "../usbh_hcd.h"
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#include "ehci.h"
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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STATIC_ ehci_data_t ehci_data TUSB_CFG_ATTR_USBRAM;
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STATIC_ ehci_link_t period_frame_list0[EHCI_FRAMELIST_SIZE] ATTR_ALIGNED(4096) TUSB_CFG_ATTR_USBRAM;
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#if CONTROLLER_HOST_NUMBER > 1
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STATIC_ ehci_link_t period_frame_list1[EHCI_FRAMELIST_SIZE] ATTR_ALIGNED(4096) TUSB_CFG_ATTR_USBRAM;
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#endif
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//------------- Validation -------------//
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STATIC_ASSERT( ALIGN_OF(period_frame_list0) == 4096, "Period Framelist must be 4k alginment");
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#if CONTROLLER_HOST_NUMBER > 1
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STATIC_ASSERT( ALIGN_OF(period_frame_list1) == 4096, "Period Framelist must be 4k alginment");
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#endif
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//--------------------------------------------------------------------+
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// IMPLEMENTATION
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//--------------------------------------------------------------------+
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STATIC_ INLINE_ ehci_registers_t* const get_operational_register(uint8_t hostid) ATTR_PURE ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
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STATIC_ INLINE_ ehci_registers_t* const get_operational_register(uint8_t hostid)
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{
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return (ehci_registers_t* const) (hostid ? (&LPC_USB1->USBCMD_H) : (&LPC_USB0->USBCMD_H) );
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}
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STATIC_ INLINE_ ehci_link_t* const get_period_frame_list(uint8_t list_idx) ATTR_PURE ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
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STATIC_ INLINE_ ehci_link_t* const get_period_frame_list(uint8_t list_idx)
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{
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#if CONTROLLER_HOST_NUMBER > 1
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return list_idx ? period_frame_list1 : period_frame_list0; // TODO more than 2 controller
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#else
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return period_frame_list0;
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#endif
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}
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STATIC_ INLINE_ uint8_t hostid_to_data_idx(uint8_t hostid) ATTR_ALWAYS_INLINE ATTR_CONST ATTR_WARN_UNUSED_RESULT;
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STATIC_ INLINE_ uint8_t hostid_to_data_idx(uint8_t hostid)
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{
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#if (CONTROLLER_HOST_NUMBER == 1) && (TUSB_CFG_CONTROLLER1_MODE & TUSB_MODE_HOST)
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(void) hostid;
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return 0;
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#else
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return hostid;
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#endif
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}
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STATIC_ INLINE_ ehci_qhd_t* const get_async_head(uint8_t hostid) ATTR_ALWAYS_INLINE ATTR_PURE ATTR_WARN_UNUSED_RESULT;
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STATIC_ INLINE_ ehci_qhd_t* const get_async_head(uint8_t hostid)
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{
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return &ehci_data.controller.async_head[hostid_to_data_idx(hostid)];
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}
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STATIC_ INLINE_ ehci_qhd_t* const get_period_head(uint8_t hostid) ATTR_ALWAYS_INLINE ATTR_PURE ATTR_WARN_UNUSED_RESULT;
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STATIC_ INLINE_ ehci_qhd_t* const get_period_head(uint8_t hostid)
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{
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return &ehci_data.controller.period_head[hostid_to_data_idx(hostid)];
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}
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tusb_error_t hcd_controller_init(uint8_t hostid) ATTR_WARN_UNUSED_RESULT;
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//--------------------------------------------------------------------+
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// USBH-HCD API
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//--------------------------------------------------------------------+
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tusb_error_t hcd_init(void)
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{
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//------------- Data Structure init -------------//
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memclr_(&ehci_data, sizeof(ehci_data_t));
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#if (TUSB_CFG_CONTROLLER0_MODE & TUSB_MODE_HOST)
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ASSERT_STATUS (hcd_controller_init(0));
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#endif
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#if (TUSB_CFG_CONTROLLER1_MODE & TUSB_MODE_HOST)
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ASSERT_STATUS (hcd_controller_init(1));
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#endif
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return TUSB_ERROR_NONE;
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}
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void hcd_isr(uint8_t hostid)
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{
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}
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//--------------------------------------------------------------------+
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// Controller API
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//--------------------------------------------------------------------+
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tusb_error_t hcd_controller_init(uint8_t hostid)
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{
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ehci_registers_t* const regs = get_operational_register(hostid);
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//------------- CTRLDSSEGMENT Register (skip) -------------//
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//------------- USB INT Register -------------//
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regs->usb_int_enable = 0; // 1. disable all the interrupt
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regs->usb_sts = EHCI_INT_MASK_ALL; // 2. clear all status
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regs->usb_int_enable =
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/*EHCI_INT_MASK_USB |*/ EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE
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#if 1 // TODO enable usbint olny
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| EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC
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#endif
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;
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//------------- Asynchronous List -------------//
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ehci_qhd_t * const async_head = get_async_head(hostid);
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memclr_(async_head, sizeof(ehci_qhd_t));
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async_head->next.address = align32( (uint32_t) async_head); // circular list, next is itself
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async_head->next.type = EHCI_QUEUE_ELEMENT_QHD;
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async_head->head_list_flag = 1;
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async_head->qtd_overlay.next.terminate = 1;
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async_head->qtd_overlay.alternate.terminate = 1;
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async_head->qtd_overlay.halted = 1;
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regs->async_list_base = (uint32_t) async_head;
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//------------- Periodic List -------------//
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#if EHCI_PERIODIC_LIST
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ehci_link_t * const framelist = get_period_frame_list(hostid);
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ehci_qhd_t * const period_head = get_period_head(hostid);
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uint32_t i;
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for(i=0; i<EHCI_FRAMELIST_SIZE; i++)
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{
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framelist[i].address = (uint32_t) period_head;
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framelist[i].type = EHCI_QUEUE_ELEMENT_QHD;
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}
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period_head->smask = 1; // queue head in period list must have smask non-zero
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period_head->next.terminate = 1;
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period_head->qtd_overlay.next.terminate = 1;
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period_head->qtd_overlay.alternate.terminate = 1;
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period_head->qtd_overlay.halted = 1;
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regs->periodic_list_base = (uint32_t) framelist;
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#else
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regs->periodic_list_base = 0;
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#endif
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//------------- TT Control (NXP only) -------------//
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regs->tt_control = 0;
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//------------- USB CMD Register -------------//
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regs->usb_cmd = BIT_(EHCI_USBCMD_POS_ASYNC_ENABLE)
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#if EHCI_PERIODIC_LIST
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| BIT_(EHCI_USBCMD_POS_PERIOD_ENABLE)
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#endif
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| ((EHCI_CFG_FRAMELIST_SIZE_BITS & BIN8(011)) << EHCI_USBCMD_POS_FRAMELIST_SZIE)
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| ((EHCI_CFG_FRAMELIST_SIZE_BITS >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB);
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//------------- ConfigFlag Register (skip) -------------//
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return TUSB_ERROR_NONE;
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}
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tusb_error_t hcd_controller_stop(uint8_t hostid) ATTR_WARN_UNUSED_RESULT;
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tusb_error_t hcd_controller_stop(uint8_t hostid)
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{
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ehci_registers_t* const regs = get_operational_register(hostid);
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timeout_timer_t timeout;
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regs->usb_cmd_bit.run_stop = 0;
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timeout_set(&timeout, 16); // USB Spec: controller has to stop within 16 uframe
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while( regs->usb_sts_bit.hc_halted == 0 && !timeout_expired(&timeout)) {}
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return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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}
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//TODO host/device mode must be set immediately after a reset
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tusb_error_t hcd_controller_reset(uint8_t hostid) ATTR_WARN_UNUSED_RESULT;
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tusb_error_t hcd_controller_reset(uint8_t hostid)
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{
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ehci_registers_t* const regs = get_operational_register(hostid);
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timeout_timer_t timeout;
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if (regs->usb_sts_bit.hc_halted == 0) // need to stop before reset
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{
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ASSERT_STATUS( hcd_controller_stop(hostid) );
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}
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regs->usb_cmd_bit.reset = 1;
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timeout_set(&timeout, 16); // should not take longer the time to stop controller
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while( regs->usb_cmd_bit.reset && !timeout_expired(&timeout)) {}
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return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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}
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//--------------------------------------------------------------------+
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// PORT API
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// PIPE API
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//--------------------------------------------------------------------+
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tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
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{
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ehci_qhd_t *p_qhd;
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if (dev_addr == 0)
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{
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// async head of selected controller is used as Addr0 Endpoint --> horizontal link have to be preserved
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p_qhd = get_async_head( usbh_device_info_pool[dev_addr].core_id );
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p_qhd->head_list_flag = 1; // make sure it is still head of list
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}else
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{
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p_qhd = &ehci_data.device[dev_addr].control.qhd;
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p_qhd->head_list_flag = 0; // make sure it is still head of list
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}
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p_qhd->device_address = dev_addr;
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p_qhd->inactive_next_xact = 0;
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p_qhd->endpoint_number = 0;
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p_qhd->endpoint_speed = usbh_device_info_pool[dev_addr].speed;
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p_qhd->data_toggle_control = 1;
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p_qhd->max_package_size = max_packet_size;
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p_qhd->non_hs_control_endpoint = (usbh_device_info_pool[dev_addr].speed != TUSB_SPEED_HIGH) ? 1 : 0;
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p_qhd->nak_count_reload = 0;
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p_qhd->smask = 0;
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p_qhd->cmask = 0;
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p_qhd->hub_address = usbh_device_info_pool[dev_addr].hub_addr;
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p_qhd->hub_port = usbh_device_info_pool[dev_addr].hub_port;
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p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet
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//------------- inactive when just opened -------------//
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p_qhd->qtd_overlay.next.terminate = 1;
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p_qhd->qtd_overlay.alternate.terminate = 1;
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p_qhd->qtd_overlay.halted = 1;
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//------------- HCD Management Data -------------//
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p_qhd->used = 1;
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p_qhd->p_qtd_list = NULL;
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//------------- insert to async list -------------//
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// TODO disable async list first if got error
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if (dev_addr != 0)
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{
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ehci_qhd_t * const async_head = get_async_head(usbh_device_info_pool[dev_addr].core_id);
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p_qhd->next = async_head->next;
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async_head->next.address = (uint32_t) p_qhd;
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async_head->next.type = EHCI_QUEUE_ELEMENT_QHD;
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}
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return TUSB_ERROR_NONE;
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}
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//
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//tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_std_request_t const * p_request, uint8_t data[])
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//{
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// return TUSB_ERROR_NONE;
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//}
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//
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pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_descriptor_endpoint_t const * endpoint_desc)
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{
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return TUSB_ERROR_NONE;
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}
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#endif
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