158 lines
7.1 KiB
C
158 lines
7.1 KiB
C
/*
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* @brief Basic CMSIS include file
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CMSIS_1347_H_
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#define __CMSIS_1347_H_
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#include "lpc_types.h"
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#include "sys_config.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CMSIS_1347 CHIP: LPC1347 CMSIS include file
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* @ingroup CHIP_13XX_CMSIS_Drivers
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* @{
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*/
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#if defined(__ARMCC_VERSION)
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// Kill warning "#pragma push with no matching #pragma pop"
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#pragma diag_suppress 2525
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#pragma push
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#pragma anon_unions
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#elif defined(__CWCC__)
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#pragma push
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#pragma cpp_extensions on
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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// #pragma push // FIXME not usable for IAR
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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#if !defined(CHIP_LPC1347)
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#error Incorrect or missing device variant (CHIP_LPC1347)
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#endif
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/** @defgroup CMSIS_1347_IRQ CHIP_1347: LPC1315/LPC1316/LPC1317/LPC1345/LPC1346/LPC1347 peripheral interrupt numbers
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* @{
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*/
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typedef enum LPC1347_IRQn {
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Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
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BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
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UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
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PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
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SysTick_IRQn = -1, /*!< 15 System Tick Timer */
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/****** LPC1347 Specific Interrupt Numbers *******************************************************/
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PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
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PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
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PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
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PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
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PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
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PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
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PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
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PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
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GINT0_IRQn = 8, /*!< 8 GINT0 */
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GINT1_IRQn = 9, /*!< 9 GINT1 */
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Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
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Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
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RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
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Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
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SSP1_IRQn = 14, /*!< 14 SSP1 */
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I2C0_IRQn = 15, /*!< 15 I2C */
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TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
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TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
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TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
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TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
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SSP0_IRQn = 20, /*!< 20 SSP0 */
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UART0_IRQn = 21, /*!< 21 USART */
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USB0_IRQn = 22, /*!< 22 USB_IRQ */
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USB0_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
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ADC_IRQn = 24, /*!< 24 ADC */
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WDT_IRQn = 25, /*!< 25 WDT */
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BOD_IRQn = 26, /*!< 26 BOD */
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FMC_IRQn = 27, /*!< 27 FMC */
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Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
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Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
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USB_WAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
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Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
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} LPC1347_IRQn_Type;
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/**
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* @}
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*/
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/** @defgroup CMSIS_1347_COMMON CHIP: Common LPC1347 Cortex CMSIS definitions
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* @{
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*/
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/* Configuration of the Cortex-M3 Processor and Core Peripherals */
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#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CMSIS_1347_H_ */
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