204 lines
9.0 KiB
C
204 lines
9.0 KiB
C
/*
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* @brief LPC177x/8x basic chip inclusion file
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CHIP_LPC177X_8X_H_
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#define __CHIP_LPC177X_8X_H_
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#include "lpc_types.h"
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#include "sys_config.h"
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !defined(CORE_M3)
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#error CORE_M3 is not defined for the LPC177x/8x architecture
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#error CORE_M3 should be defined as part of your compiler define list
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#endif
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#ifndef CHIP_LPC177X_8X
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#error CHIP_LPC177X_8X is not defined!
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#endif
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/** @defgroup PERIPH_177X_8X_BASE CHIP: LPC177x/8x Peripheral addresses and register set declarations
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* @ingroup CHIP_17XX_40XX_Drivers
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* @{
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*/
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#define LPC_FMC_BASE 0x00200000
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#define LPC_EEPROM_BASE 0x00200080
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#define LPC_GPDMA_BASE 0x20080000
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#define LPC_ENET_BASE 0x20084000
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#define LPC_LCD_BASE 0x20088000
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#define LPC_USB_BASE 0x2008C000
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#define LPC_CRC_BASE 0x20090000
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#define LPC_SPIFI_BASE 0x20094000
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#define LPC_GPIO0_BASE 0x20098000
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#define LPC_GPIO1_BASE 0x20098020
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#define LPC_GPIO2_BASE 0x20098040
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#define LPC_GPIO3_BASE 0x20098060
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#define LPC_GPIO4_BASE 0x20098080
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#define LPC_GPIO5_BASE 0x200980A0
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#define LPC_EMC_BASE 0x2009C000
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#define LPC_RTC_BASE 0x40024000
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#define LPC_REGFILE_BASE 0x40024044
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#define LPC_WWDT_BASE 0x40000000
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#define LPC_UART0_BASE 0x4000C000
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#define LPC_UART1_BASE 0x40010000
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#define LPC_UART2_BASE 0x40098000
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#define LPC_UART3_BASE 0x4009C000
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#define LPC_UART4_BASE 0x400A4000
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#define LPC_SSP0_BASE 0x40088000
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#define LPC_SSP1_BASE 0x40030000
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#define LPC_SSP2_BASE 0x400AC000
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#define LPC_TIMER0_BASE 0x40004000
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#define LPC_TIMER1_BASE 0x40008000
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#define LPC_TIMER2_BASE 0x40090000
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#define LPC_TIMER3_BASE 0x40094000
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#define LPC_MCPWM_BASE 0x400B8000
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#define LPC_PWM0_BASE 0x40014000
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#define LPC_PWM1_BASE 0x40018000
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#define LPC_I2C0_BASE 0x4001C000
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#define LPC_I2C1_BASE 0x4005C000
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#define LPC_I2C2_BASE 0x400A0000
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#define LPC_I2S_BASE 0x400A8000
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#define LPC_CANAF_RAM_BASE 0x40038000
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#define LPC_CANAF_BASE 0x4003C000
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#define LPC_CANCR_BASE 0x40040000
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#define LPC_CAN1_BASE 0x40044000
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#define LPC_CAN2_BASE 0x40048000
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#define LPC_QEI_BASE 0x400BC000
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#define LPC_DAC_BASE 0x4008C000
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#define LPC_ADC_BASE 0x40034000
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#define LPC_GPIOINT_BASE 0x40028080
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#define LPC_IOCON_BASE 0x4002C000
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#define LPC_SDC_BASE 0x400C0000
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#define LPC_SYSCTL_BASE 0x400FC000
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#define LPC_PMU_BASE 0x400FC0C0
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/* Assign LPC_* names to structures mapped to addresses */
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#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE)
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#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
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#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
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#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
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#define LPC_USB ((LPC_USB_T *) LPC_USB_BASE)
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#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
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#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ENET_BASE)
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#define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO0_BASE)
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#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
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#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
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#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
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#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
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#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
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#define LPC_GPIOINT ((LPC_GPIOINT_T *) LPC_GPIOINT_BASE)
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#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
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#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
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#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
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#define LPC_UART0 ((LPC_USART_T *) LPC_UART0_BASE)
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#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
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#define LPC_UART2 ((LPC_USART_T *) LPC_UART2_BASE)
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#define LPC_UART3 ((LPC_USART_T *) LPC_UART3_BASE)
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#define LPC_UART4 ((LPC_USART_T *) LPC_UART4_BASE)
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#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
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#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
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#define LPC_SSP2 ((LPC_SSP_T *) LPC_SSP2_BASE)
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#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
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#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
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#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
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#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
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#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
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#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
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#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
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#define LPC_I2C2 ((LPC_I2C_T *) LPC_I2C2_BASE)
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#define LPC_I2S ((LPC_I2S_T *) LPC_I2S_BASE)
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#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
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#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
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#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE)
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#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE)
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#define LPC_SDC ((LPC_SDC_T *) LPC_SDC_BASE)
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#define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE)
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#define LPC_SYSCON ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE) /* Alias for LPC_SYSCTL */
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#define LPC_CANAF_RAM ((LPC_CANAF_RAM_T *) LPC_CANAF_RAM_BASE)
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#define LPC_CANAF ((LPC_CANAF_T *) LPC_CANAF_BASE)
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#define LPC_CANCR ((LPC_CANCR_T *) LPC_CANCR_BASE)
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#define LPC_CAN1 ((LPC_CAN_T *) LPC_CAN1_BASE)
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#define LPC_CAN2 ((LPC_CAN_T *) LPC_CAN2_BASE)
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#define LPC_CRC ((LPC_CRC_T *) LPC_CRC_BASE)
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#define LPC_FMC ((LPC_FMC_T *) LPC_FMC_BASE)
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/* IRQ Handler Alias list */
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#define UART_IRQHandler UART0_IRQHandler
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#define I2C_IRQHandler I2C0_IRQHandler
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#define SSP_IRQHandler SSP0_IRQHandler
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/**
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* @}
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*/
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#include "sysctl_17xx_40xx.h"
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#include "clock_17xx_40xx.h"
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#include "iocon_17xx_40xx.h"
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#include "adc_17xx_40xx.h"
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#include "can_17xx_40xx.h"
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#include "crc_17xx_40xx.h"
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#include "dac_17xx_40xx.h"
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#include "eeprom_17xx_40xx.h"
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#include "emc_17xx_40xx.h"
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#include "enet_17xx_40xx.h"
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#include "gpdma_17xx_40xx.h"
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#include "gpio_17xx_40xx.h"
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#include "gpioint_17xx_40xx.h"
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#include "i2c_17xx_40xx.h"
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#include "i2s_17xx_40xx.h"
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#include "lcd_17xx_40xx.h"
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#include "mcpwm_17xx_40xx.h"
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#include "pmu_17xx_40xx.h"
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#include "qei_17xx_40xx.h"
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#include "rtc_17xx_40xx.h"
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#include "sdc_17xx_40xx.h"
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#include "sdmmc_17xx_40xx.h"
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#include "ssp_17xx_40xx.h"
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#include "timer_17xx_40xx.h"
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#include "uart_17xx_40xx.h"
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#include "usb_17xx_40xx.h"
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#include "wwdt_17xx_40xx.h"
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#include "fmc_17xx_40xx.h"
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#include "romapi_17xx_40xx.h"
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/* FIXME - missing PWM and possibly CREG drivers */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CHIP_LPC177X_8X_H_ */
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