777 lines
23 KiB
C
777 lines
23 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018, hathach (tinyusb.org)
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* Copyright (c) 2021, HiFiPhile
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMX7X
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#include "device/dcd.h"
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#include "sam.h"
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#include "common_usb_regs.h"
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
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// We disable SOF for now until needed later on
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#ifndef USE_SOF
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# define USE_SOF 0
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#endif
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// Dual bank can improve performance, but need 2 times bigger packet buffer
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// As SAM7x has only 4KB packet buffer, use with caution !
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// Enable in FS mode as packets are smaller
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#ifndef USE_DUAL_BANK
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# if TUD_OPT_HIGH_SPEED
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# define USE_DUAL_BANK 0
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# else
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# define USE_DUAL_BANK 1
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# endif
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#endif
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#define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])FIFO_RAM_ADDR)[(ep)])
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// DMA Channel Transfer Descriptor
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typedef struct {
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volatile uint32_t next_desc;
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volatile uint32_t buff_addr;
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volatile uint32_t chnl_ctrl;
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uint32_t padding;
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} dma_desc_t;
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// Transfer control context
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typedef struct {
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uint8_t * buffer;
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uint16_t total_len;
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uint16_t queued_len;
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uint16_t max_packet_size;
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uint8_t interval;
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tu_fifo_t * fifo;
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} xfer_ctl_t;
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static tusb_speed_t get_speed(void);
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static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
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// DMA descriptors shouldn't be placed in ITCM !
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CFG_TUSB_MEM_SECTION static dma_desc_t dma_desc[6];
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static xfer_ctl_t xfer_status[EP_MAX];
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static const tusb_desc_endpoint_t ep0_desc =
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{
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.bEndpointAddress = 0x00,
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.wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
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};
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TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, int32_t size)
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{
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if (SCB->CCR & SCB_CCR_DC_Msk)
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{
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SCB_CleanInvalidateDCache_by_Addr(addr, size);
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}
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else
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{
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__DSB();
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__ISB();
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}
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}
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//------------------------------------------------------------------
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// Device API
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//------------------------------------------------------------------
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// Initialize controller to device mode
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void dcd_init (uint8_t rhport)
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{
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dcd_connect(rhport);
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}
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// Enable device interrupt
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void dcd_int_enable (uint8_t rhport)
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{
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(void) rhport;
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NVIC_EnableIRQ((IRQn_Type) ID_USBHS);
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}
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// Disable device interrupt
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void dcd_int_disable (uint8_t rhport)
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{
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(void) rhport;
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NVIC_DisableIRQ((IRQn_Type) ID_USBHS);
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}
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// Receive Set Address request, mcu port must also include status IN response
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void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
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{
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(void) dev_addr;
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// DCD can only set address after status for this request is complete
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// do it at dcd_edpt0_status_complete()
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// Response with zlp status
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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}
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// Wake up host
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void dcd_remote_wakeup (uint8_t rhport)
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{
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(void) rhport;
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USB_REG->DEVCTRL |= DEVCTRL_RMWKUP;
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}
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// Connect by enabling internal pull-up resistor on D+/D-
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void dcd_connect(uint8_t rhport)
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{
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(void) rhport;
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dcd_int_disable(rhport);
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// Enable the USB controller in device mode
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USB_REG->CTRL = CTRL_UIMOD | CTRL_USBE;
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while (!(USB_REG->SR & SR_CLKUSABLE));
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#if TUD_OPT_HIGH_SPEED
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USB_REG->DEVCTRL &= ~DEVCTRL_SPDCONF;
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#else
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USB_REG->DEVCTRL |= DEVCTRL_SPDCONF_LOW_POWER;
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#endif
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// Enable the End Of Reset, Suspend & Wakeup interrupts
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USB_REG->DEVIER = (DEVIER_EORSTES | DEVIER_SUSPES | DEVIER_WAKEUPES);
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#if USE_SOF
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USB_REG->DEVIER = DEVIER_SOFES;
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#endif
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// Clear the End Of Reset, SOF & Wakeup interrupts
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USB_REG->DEVICR = (DEVICR_EORSTC | DEVICR_SOFC | DEVICR_WAKEUPC);
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// Manually set the Suspend Interrupt
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USB_REG->DEVIFR |= DEVIFR_SUSPS;
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// Ack the Wakeup Interrupt
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USB_REG->DEVICR = DEVICR_WAKEUPC;
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// Attach the device
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USB_REG->DEVCTRL &= ~DEVCTRL_DETACH;
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// Freeze USB clock
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USB_REG->CTRL |= CTRL_FRZCLK;
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}
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// Disconnect by disabling internal pull-up resistor on D+/D-
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void dcd_disconnect(uint8_t rhport)
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{
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(void) rhport;
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dcd_int_disable(rhport);
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// Disable all endpoints
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USB_REG->DEVEPT &= ~(0x3FF << DEVEPT_EPEN0_Pos);
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// Unfreeze USB clock
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USB_REG->CTRL &= ~CTRL_FRZCLK;
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while (!(USB_REG->SR & SR_CLKUSABLE));
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// Clear all the pending interrupts
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USB_REG->DEVICR = DEVICR_Msk;
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// Disable all interrupts
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USB_REG->DEVIDR = DEVIDR_Msk;
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// Detach the device
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USB_REG->DEVCTRL |= DEVCTRL_DETACH;
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// Disable the device address
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USB_REG->DEVCTRL &=~(DEVCTRL_ADDEN | DEVCTRL_UADD);
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}
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void dcd_sof_enable(uint8_t rhport, bool en)
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{
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(void) rhport;
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(void) en;
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// TODO implement later
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}
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static tusb_speed_t get_speed(void)
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{
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switch (USB_REG->SR & SR_SPEED) {
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case SR_SPEED_FULL_SPEED:
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default:
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return TUSB_SPEED_FULL;
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case SR_SPEED_HIGH_SPEED:
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return TUSB_SPEED_HIGH;
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case SR_SPEED_LOW_SPEED:
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return TUSB_SPEED_LOW;
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}
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}
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static void dcd_ep_handler(uint8_t ep_ix)
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{
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uint32_t int_status = USB_REG->DEVEPTISR[ep_ix];
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int_status &= USB_REG->DEVEPTIMR[ep_ix];
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uint16_t count = (USB_REG->DEVEPTISR[ep_ix] &
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DEVEPTISR_BYCT) >> DEVEPTISR_BYCT_Pos;
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xfer_ctl_t *xfer = &xfer_status[ep_ix];
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if (ep_ix == 0U)
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{
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static uint8_t ctrl_dir;
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if (int_status & DEVEPTISR_CTRL_RXSTPI)
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{
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ctrl_dir = (USB_REG->DEVEPTISR[0] & DEVEPTISR_CTRL_CTRLDIR) >> DEVEPTISR_CTRL_CTRLDIR_Pos;
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// Setup packet should always be 8 bytes. If not, ignore it, and try again.
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if (count == 8)
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{
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uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
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dcd_event_setup_received(0, ptr, true);
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}
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// Ack and disable SETUP interrupt
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USB_REG->DEVEPTICR[0] = DEVEPTICR_CTRL_RXSTPIC;
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USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_RXSTPEC;
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}
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if (int_status & DEVEPTISR_RXOUTI)
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{
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uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
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if (count && xfer->total_len)
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{
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uint16_t remain = xfer->total_len - xfer->queued_len;
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if (count > remain)
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{
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count = remain;
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}
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if (xfer->buffer)
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{
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memcpy(xfer->buffer + xfer->queued_len, ptr, count);
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} else
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{
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tu_fifo_write_n(xfer->fifo, ptr, count);
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}
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xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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}
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// Acknowledge the interrupt
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USB_REG->DEVEPTICR[0] = DEVEPTICR_RXOUTIC;
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if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
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{
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// RX COMPLETE
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dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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// Disable the interrupt
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USB_REG->DEVEPTIDR[0] = DEVEPTIDR_RXOUTEC;
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// Re-enable SETUP interrupt
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if (ctrl_dir == 1)
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{
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USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
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}
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}
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}
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if (int_status & DEVEPTISR_TXINI)
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{
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// Disable the interrupt
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USB_REG->DEVEPTIDR[0] = DEVEPTIDR_TXINEC;
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if ((xfer->total_len != xfer->queued_len))
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{
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// TX not complete
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dcd_transmit_packet(xfer, 0);
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} else
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{
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// TX complete
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dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
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// Re-enable SETUP interrupt
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if (ctrl_dir == 0)
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{
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USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
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}
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}
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}
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} else
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{
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if (int_status & DEVEPTISR_RXOUTI)
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{
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if (count && xfer->total_len)
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{
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uint16_t remain = xfer->total_len - xfer->queued_len;
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if (count > remain)
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{
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count = remain;
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}
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uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
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if (xfer->buffer)
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{
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memcpy(xfer->buffer + xfer->queued_len, ptr, count);
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} else {
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tu_fifo_write_n(xfer->fifo, ptr, count);
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}
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xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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}
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// Clear the FIFO control flag to receive more data.
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USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
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// Acknowledge the interrupt
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USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_RXOUTIC;
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if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
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{
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// RX COMPLETE
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dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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// Disable the interrupt
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USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_RXOUTEC;
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// Though the host could still send, we don't know.
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}
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}
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if (int_status & DEVEPTISR_TXINI)
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{
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// Acknowledge the interrupt
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USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_TXINIC;
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if ((xfer->total_len != xfer->queued_len))
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{
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// TX not complete
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dcd_transmit_packet(xfer, ep_ix);
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} else
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{
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// TX complete
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dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
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// Disable the interrupt
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USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_TXINEC;
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}
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}
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}
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}
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static void dcd_dma_handler(uint8_t ep_ix)
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{
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uint32_t status = USB_REG->DEVDMA[ep_ix - 1].DEVDMASTATUS;
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if (status & DEVDMASTATUS_CHANN_ENB)
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{
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return; // Ignore EOT_STA interrupt
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}
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// Disable DMA interrupt
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USB_REG->DEVIDR = DEVIDR_DMA_1 << (ep_ix - 1);
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xfer_ctl_t *xfer = &xfer_status[ep_ix];
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uint16_t count = xfer->total_len - ((status & DEVDMASTATUS_BUFF_COUNT) >> DEVDMASTATUS_BUFF_COUNT_Pos);
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if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR)
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{
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dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
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} else
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{
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dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
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}
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}
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void dcd_int_handler(uint8_t rhport)
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{
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(void) rhport;
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uint32_t int_status = USB_REG->DEVISR;
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int_status &= USB_REG->DEVIMR;
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// End of reset interrupt
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if (int_status & DEVISR_EORST)
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{
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// Unfreeze USB clock
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USB_REG->CTRL &= ~CTRL_FRZCLK;
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while(!(USB_REG->SR & SR_CLKUSABLE));
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// Reset all endpoints
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for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++)
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{
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USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + ep_ix);
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USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + ep_ix));
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}
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dcd_edpt_open (0, &ep0_desc);
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USB_REG->DEVICR = DEVICR_EORSTC;
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USB_REG->DEVICR = DEVICR_WAKEUPC;
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USB_REG->DEVICR = DEVICR_SUSPC;
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USB_REG->DEVIER = DEVIER_SUSPES;
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dcd_event_bus_reset(rhport, get_speed(), true);
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}
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// End of Wakeup interrupt
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if (int_status & DEVISR_WAKEUP)
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{
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USB_REG->CTRL &= ~CTRL_FRZCLK;
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while (!(USB_REG->SR & SR_CLKUSABLE));
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USB_REG->DEVICR = DEVICR_WAKEUPC;
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USB_REG->DEVIDR = DEVIDR_WAKEUPEC;
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USB_REG->DEVIER = DEVIER_SUSPES;
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dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
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}
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// Suspend interrupt
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if (int_status & DEVISR_SUSP)
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{
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// Unfreeze USB clock
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USB_REG->CTRL &= ~CTRL_FRZCLK;
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while (!(USB_REG->SR & SR_CLKUSABLE));
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USB_REG->DEVICR = DEVICR_SUSPC;
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USB_REG->DEVIDR = DEVIDR_SUSPEC;
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USB_REG->DEVIER = DEVIER_WAKEUPES;
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USB_REG->CTRL |= CTRL_FRZCLK;
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dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
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}
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#if USE_SOF
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if(int_status & DEVISR_SOF)
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{
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USB_REG->DEVICR = DEVICR_SOFC;
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dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
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}
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#endif
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// Endpoints interrupt
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for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
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{
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if (int_status & (DEVISR_PEP_0 << ep_ix))
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{
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dcd_ep_handler(ep_ix);
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}
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}
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// Endpoints DMA interrupt
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for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
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{
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if (EP_DMA_SUPPORT(ep_ix))
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{
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if (int_status & (DEVISR_DMA_1 << (ep_ix - 1)))
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{
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dcd_dma_handler(ep_ix);
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}
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}
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}
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}
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//--------------------------------------------------------------------+
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// Endpoint API
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//--------------------------------------------------------------------+
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// Invoked when a control transfer's status stage is complete.
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// May help DCD to prepare for next control transfer, this API is optional.
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void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
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{
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(void) rhport;
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if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
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request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
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request->bRequest == TUSB_REQ_SET_ADDRESS )
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{
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uint8_t const dev_addr = (uint8_t) request->wValue;
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USB_REG->DEVCTRL |= dev_addr | DEVCTRL_ADDEN;
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}
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}
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// Configure endpoint's registers according to descriptor
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bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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{
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(void) rhport;
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uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
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uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress);
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uint16_t const epMaxPktSize = tu_edpt_packet_size(ep_desc);
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tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
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uint8_t fifoSize = 0; // FIFO size
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|
uint16_t defaultEndpointSize = 8; // Default size of Endpoint
|
|
// Find upper 2 power number of epMaxPktSize
|
|
if (epMaxPktSize)
|
|
{
|
|
while (defaultEndpointSize < epMaxPktSize)
|
|
{
|
|
fifoSize++;
|
|
defaultEndpointSize <<= 1;
|
|
}
|
|
}
|
|
xfer_status[epnum].max_packet_size = epMaxPktSize;
|
|
|
|
USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + epnum);
|
|
USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + epnum));
|
|
|
|
if (epnum == 0)
|
|
{
|
|
// Enable the control endpoint - Endpoint 0
|
|
USB_REG->DEVEPT |= DEVEPT_EPEN0;
|
|
// Configure the Endpoint 0 configuration register
|
|
USB_REG->DEVEPTCFG[0] =
|
|
(
|
|
(fifoSize << DEVEPTCFG_EPSIZE_Pos) |
|
|
(TUSB_XFER_CONTROL << DEVEPTCFG_EPTYPE_Pos) |
|
|
(DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) |
|
|
DEVEPTCFG_ALLOC
|
|
);
|
|
USB_REG->DEVEPTIER[0] = DEVEPTIER_RSTDTS;
|
|
USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_STALLRQC;
|
|
if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[0] & DEVEPTISR_CFGOK))
|
|
{
|
|
// Endpoint configuration is successful
|
|
USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
|
|
// Enable Endpoint 0 Interrupts
|
|
USB_REG->DEVIER = DEVIER_PEP_0;
|
|
return true;
|
|
} else
|
|
{
|
|
// Endpoint configuration is not successful
|
|
return false;
|
|
}
|
|
} else
|
|
{
|
|
// Enable the endpoint
|
|
USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos);
|
|
// Set up the maxpacket size, fifo start address fifosize
|
|
// and enable the interrupt. CLear the data toggle.
|
|
// AUTOSW is needed for DMA ack !
|
|
USB_REG->DEVEPTCFG[epnum] =
|
|
(
|
|
(fifoSize << DEVEPTCFG_EPSIZE_Pos) |
|
|
(eptype << DEVEPTCFG_EPTYPE_Pos) |
|
|
(DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) |
|
|
DEVEPTCFG_AUTOSW |
|
|
((dir & 0x01) << DEVEPTCFG_EPDIR_Pos)
|
|
);
|
|
if (eptype == TUSB_XFER_ISOCHRONOUS)
|
|
{
|
|
USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_NBTRANS_1_TRANS;
|
|
}
|
|
#if USE_DUAL_BANK
|
|
if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK)
|
|
{
|
|
USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_EPBK_2_BANK;
|
|
}
|
|
#endif
|
|
USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_ALLOC;
|
|
USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RSTDTS;
|
|
USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC;
|
|
if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[epnum] & DEVEPTISR_CFGOK))
|
|
{
|
|
USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos);
|
|
return true;
|
|
} else
|
|
{
|
|
// Endpoint configuration is not successful
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
|
|
void dcd_edpt_close_all (uint8_t rhport)
|
|
{
|
|
(void) rhport;
|
|
// TODO implement dcd_edpt_close_all()
|
|
}
|
|
|
|
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
|
{
|
|
(void) rhport;
|
|
uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
|
|
// Disable endpoint interrupt
|
|
USB_REG->DEVIDR = 1 << (DEVIDR_PEP_0_Pos + epnum);
|
|
// Disable EP
|
|
USB_REG->DEVEPT &=~(1 << (DEVEPT_EPEN0_Pos + epnum));
|
|
}
|
|
|
|
static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
|
|
{
|
|
uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
|
|
if (len)
|
|
{
|
|
if (len > xfer->max_packet_size)
|
|
{
|
|
len = xfer->max_packet_size;
|
|
}
|
|
uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
|
|
if(xfer->buffer)
|
|
{
|
|
memcpy(ptr, xfer->buffer + xfer->queued_len, len);
|
|
}
|
|
else
|
|
{
|
|
tu_fifo_read_n(xfer->fifo, ptr, len);
|
|
}
|
|
__DSB();
|
|
__ISB();
|
|
xfer->queued_len = (uint16_t)(xfer->queued_len + len);
|
|
}
|
|
if (ep_ix == 0U)
|
|
{
|
|
// Control endpoint: clear the interrupt flag to send the data
|
|
USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC;
|
|
} else
|
|
{
|
|
// Other endpoint types: clear the FIFO control flag to send the data
|
|
USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
|
|
}
|
|
USB_REG->DEVEPTIER[ep_ix] = DEVEPTIER_TXINES;
|
|
}
|
|
|
|
// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
|
|
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
|
{
|
|
(void) rhport;
|
|
uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
uint8_t const dir = tu_edpt_dir(ep_addr);
|
|
|
|
xfer_ctl_t * xfer = &xfer_status[epnum];
|
|
|
|
xfer->buffer = buffer;
|
|
xfer->total_len = total_bytes;
|
|
xfer->queued_len = 0;
|
|
xfer->fifo = NULL;
|
|
|
|
if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
|
|
{
|
|
// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
|
|
// address to 32-byte boundaries.
|
|
CleanInValidateCache((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31);
|
|
uint32_t udd_dma_ctrl = total_bytes << DEVDMACONTROL_BUFF_LENGTH_Pos;
|
|
if (dir == TUSB_DIR_OUT)
|
|
{
|
|
udd_dma_ctrl |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN;
|
|
} else {
|
|
udd_dma_ctrl |= DEVDMACONTROL_END_B_EN;
|
|
}
|
|
USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)buffer;
|
|
udd_dma_ctrl |= DEVDMACONTROL_END_BUFFIT | DEVDMACONTROL_CHANN_ENB;
|
|
// Disable IRQs to have a short sequence
|
|
// between read of EOT_STA and DMA enable
|
|
uint32_t irq_state = __get_PRIMASK();
|
|
__disable_irq();
|
|
if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST))
|
|
{
|
|
USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl;
|
|
USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1);
|
|
__set_PRIMASK(irq_state);
|
|
return true;
|
|
}
|
|
__set_PRIMASK(irq_state);
|
|
|
|
// Here a ZLP has been received
|
|
// and the DMA transfer must be not started.
|
|
// It is the end of transfer
|
|
return false;
|
|
} else
|
|
{
|
|
if (dir == TUSB_DIR_OUT)
|
|
{
|
|
USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
|
|
} else
|
|
{
|
|
dcd_transmit_packet(xfer,epnum);
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// The number of bytes has to be given explicitly to allow more flexible control of how many
|
|
// bytes should be written and second to keep the return value free to give back a boolean
|
|
// success message. If total_bytes is too big, the FIFO will copy only what is available
|
|
// into the USB buffer!
|
|
bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
|
|
{
|
|
(void) rhport;
|
|
uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
uint8_t const dir = tu_edpt_dir(ep_addr);
|
|
|
|
xfer_ctl_t * xfer = &xfer_status[epnum];
|
|
if(epnum == 0x80)
|
|
xfer = &xfer_status[EP_MAX];
|
|
|
|
xfer->buffer = NULL;
|
|
xfer->total_len = total_bytes;
|
|
xfer->queued_len = 0;
|
|
xfer->fifo = ff;
|
|
|
|
if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
|
|
{
|
|
tu_fifo_buffer_info_t info;
|
|
uint32_t udd_dma_ctrl_lin = DEVDMACONTROL_CHANN_ENB;
|
|
uint32_t udd_dma_ctrl_wrap = DEVDMACONTROL_CHANN_ENB | DEVDMACONTROL_END_BUFFIT;
|
|
if (dir == TUSB_DIR_OUT)
|
|
{
|
|
tu_fifo_get_write_info(ff, &info);
|
|
udd_dma_ctrl_lin |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN;
|
|
udd_dma_ctrl_wrap |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN;
|
|
} else {
|
|
tu_fifo_get_read_info(ff, &info);
|
|
if(info.len_wrap == 0)
|
|
{
|
|
udd_dma_ctrl_lin |= DEVDMACONTROL_END_B_EN;
|
|
}
|
|
udd_dma_ctrl_wrap |= DEVDMACONTROL_END_B_EN;
|
|
}
|
|
|
|
// Clean invalidate cache of linear part
|
|
CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31);
|
|
|
|
USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.ptr_lin;
|
|
if (info.len_wrap)
|
|
{
|
|
// Clean invalidate cache of wrapped part
|
|
CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), info.len_wrap + 31);
|
|
|
|
dma_desc[epnum - 1].next_desc = 0;
|
|
dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
|
|
dma_desc[epnum - 1].chnl_ctrl =
|
|
udd_dma_ctrl_wrap | (info.len_wrap << DEVDMACONTROL_BUFF_LENGTH_Pos);
|
|
// Clean cache of wrapped DMA descriptor
|
|
CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t));
|
|
|
|
udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST;
|
|
USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
|
|
} else {
|
|
udd_dma_ctrl_lin |= DEVDMACONTROL_END_BUFFIT;
|
|
}
|
|
udd_dma_ctrl_lin |= (info.len_lin << DEVDMACONTROL_BUFF_LENGTH_Pos);
|
|
// Disable IRQs to have a short sequence
|
|
// between read of EOT_STA and DMA enable
|
|
uint32_t irq_state = __get_PRIMASK();
|
|
__disable_irq();
|
|
if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST))
|
|
{
|
|
USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl_lin;
|
|
USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1);
|
|
__set_PRIMASK(irq_state);
|
|
return true;
|
|
}
|
|
__set_PRIMASK(irq_state);
|
|
|
|
// Here a ZLP has been received
|
|
// and the DMA transfer must be not started.
|
|
// It is the end of transfer
|
|
return false;
|
|
} else
|
|
{
|
|
if (dir == TUSB_DIR_OUT)
|
|
{
|
|
USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
|
|
} else
|
|
{
|
|
dcd_transmit_packet(xfer,epnum);
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// Stall endpoint
|
|
void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
|
|
{
|
|
(void) rhport;
|
|
uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
USB_REG->DEVEPTIER[epnum] = DEVEPTIER_CTRL_STALLRQS;
|
|
// Re-enable SETUP interrupt
|
|
if (epnum == 0)
|
|
{
|
|
USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
|
|
}
|
|
}
|
|
|
|
// clear stall, data toggle is also reset to DATA0
|
|
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
|
{
|
|
(void) rhport;
|
|
uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC;
|
|
USB_REG->DEVEPTIER[epnum] = HSTPIPIER_RSTDTS;
|
|
}
|
|
|
|
#endif
|