11920 lines
1.6 MiB
11920 lines
1.6 MiB
<!DOCTYPE Register_Definition_File>
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<Processor name="LPC11U6x" description="LPC11U6x ARM cortex-m0+">
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<RegisterGroup name="I2C0" start="0x40000000" description="I2C-bus controller">
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<Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
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<BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
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<BitField start="4" size="1" name="STO" description="STOP flag." />
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<BitField start="5" size="1" name="STA" description="START flag." />
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<BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
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<BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
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<BitField start="3" size="5" name="STATUS" description="These bits give the actual status information about the I2C interface." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="GC" description="General Call enable bit." />
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<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
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<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
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<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
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<BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
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<BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
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<BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
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<BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
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<Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
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<Enum name="THE_I2C_MODULE_WILL_" start="1" description="The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
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</BitField>
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<BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
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<Enum name="HIGH" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
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<Enum name="NORMAL" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
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</BitField>
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<BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
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<Enum name="MATCH" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." />
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<Enum name="ANYADDRESS" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
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</BitField>
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<BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
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</Register>
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<Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="GC" description="General Call enable bit." />
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<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="GC" description="General Call enable bit." />
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<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="GC" description="General Call enable bit." />
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<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
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<BitField start="1" size="7" name="MASK" description="Mask bits." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
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</Register>
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<Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
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<BitField start="1" size="7" name="MASK" description="Mask bits." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
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</Register>
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<Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
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<BitField start="1" size="7" name="MASK" description="Mask bits." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
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</Register>
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<Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
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<BitField start="1" size="7" name="MASK" description="Mask bits." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
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</Register>
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</RegisterGroup>
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<RegisterGroup name="WWDT" start="0x40004000" description="Windowed Watchdog Timer (WWDT)">
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<Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.">
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<Enum name="STOPPED" start="0" description="The watchdog timer is stopped." />
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<Enum name="RUNNING" start="1" description="The watchdog timer is running." />
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</BitField>
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<BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.">
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<Enum name="INTERRUPT" start="0" description="A watchdog timeout will not cause a chip reset." />
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</BitField>
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<BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1." />
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<BitField start="3" size="1" name="WDINT" description="Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software." />
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<BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit can be set once by software and is only cleared by a reset.">
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<Enum name="NOT_LOCKED" start="0" description="The watchdog time-out value (TC) can be changed at any time." />
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<Enum name="LOCKED" start="1" description="The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
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</BitField>
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<BitField start="5" size="1" name="LOCK" description="A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7)." />
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<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This 24-bit register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="24" name="COUNT" description="Watchdog time-out value." />
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<BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="8" name="FEED" description="Feed value should be 0xAA followed by 0x55." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="24" name="COUNT" description="Counter timer value." />
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<BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="CLKSEL" description="Selects source of WDT clock">
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<Enum name="IRC" start="0" description="IRC" />
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<Enum name="WATCHDOG_OSCILLATOR_" start="1" description="Watchdog oscillator (WDOSC)" />
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</BitField>
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<BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0." />
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</Register>
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<Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." />
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<BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="24" name="WINDOW" description="Watchdog window value." />
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<BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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</RegisterGroup>
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<RegisterGroup name="USART0" start="0x40008000" description="USART0">
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<Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="8" name="RBR" description="The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved" />
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</Register>
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<Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="8" name="THR" description="Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved" />
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</Register>
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<Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="8" name="DLLSB" description="The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved" />
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</Register>
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<Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="8" name="DLMSB" description="The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
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<BitField start="8" size="24" name="RESERVED" description="Reserved" />
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</Register>
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<Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)" reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="RBRINTEN" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt.">
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<Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupt." />
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<Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupt." />
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</BitField>
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<BitField start="1" size="1" name="THREINTEN" description="THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5].">
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<Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupt." />
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<Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupt." />
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</BitField>
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<BitField start="2" size="1" name="RLSINTEN" description="Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1].">
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<Enum name="DISABLE_THE_RLS_INTE" start="0" description="Disable the RLS interrupt." />
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<Enum name="ENABLE_THE_RLS_INTER" start="1" description="Enable the RLS interrupt." />
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</BitField>
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<BitField start="3" size="1" name="MSINTEN" description="Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR.">
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<Enum name="DISABLE_THE_MS_INTER" start="0" description="Disable the MS interrupt." />
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<Enum name="ENABLE_THE_MS_INTERR" start="1" description="Enable the MS interrupt." />
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</BitField>
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<BitField start="4" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
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<Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
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<Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
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</BitField>
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<BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
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<Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
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<Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
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</BitField>
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<BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
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<Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
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<Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
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</BitField>
|
|
<BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved.">
|
|
<Enum name="1_RECEIVE_LINE_S" start="0x3" description="1 - Receive Line Status (RLS)." />
|
|
<Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
|
|
<Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
|
|
<Enum name="3_THRE_INTERRUPT" start="0x1" description="3 - THRE Interrupt." />
|
|
<Enum name="4_MODEM_STATUS" start="0x0" description="4 - Modem status" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="6" size="2" name="FIFOEN" description="These bits are equivalent to FCR[0]." />
|
|
<BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
|
|
<BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FIFOEN" description="FIFO enable">
|
|
<Enum name="DISABLED" start="0" description="USART FIFOs are disabled. Must not be used in the application." />
|
|
<Enum name="ENABLED" start="1" description="Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset">
|
|
<Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." />
|
|
<Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset">
|
|
<Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." />
|
|
<Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="RESERVED" description="Reserved" />
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="6" size="2" name="RXTL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
|
|
<Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
|
|
<Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
|
|
<Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
|
|
<Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="WLS" description="Word Length Select">
|
|
<Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
|
|
<Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
|
|
<Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
|
|
<Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SBS" description="Stop Bit Select">
|
|
<Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
|
|
<Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PE" description="Parity Enable">
|
|
<Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
|
|
<Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PS" description="Parity Select">
|
|
<Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
|
|
<Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
|
|
<Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
|
|
<Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="BC" description="Break Control">
|
|
<Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
|
|
<Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
|
|
<Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
|
|
<Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DTRCTRL" description="Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active." />
|
|
<BitField start="1" size="1" name="RTSCTRL" description="Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.">
|
|
<Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
|
|
<Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="6" size="1" name="RTSEN" description="RTS enable">
|
|
<Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
|
|
<Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CTSEN" description="CTS enable">
|
|
<Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
|
|
<Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RDR" description="Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
|
|
<Enum name="RBR_IS_EMPTY_" start="0" description="RBR is empty." />
|
|
<Enum name="RBR_CONTAINS_VALID_D" start="1" description="RBR contains valid data." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
|
|
<Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Overrun error status is active." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Parity error status is active." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Framing error status is active." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
|
|
<Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
|
|
<Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
|
|
<Enum name="THR_CONTAINS_VALID_D" start="0" description="THR contains valid data." />
|
|
<Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
|
|
<Enum name="VALID_D" start="0" description="THR and/or the TSR contains valid data." />
|
|
<Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
|
|
<Enum name="NO_ERROR" start="0" description="RBR contains no USART RX errors or FCR[0]=0." />
|
|
<Enum name="ERRO" start="1" description="USART RBR contains at least one USART RX error." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="TXERR" description="Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
|
|
<Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
|
|
<Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
|
|
<Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
|
|
<Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
|
|
<Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
|
|
<Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
|
|
<Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
|
|
<Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
|
|
<BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
|
|
<BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
|
|
<BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="START" description="This bit is automatically cleared after auto-baud completion.">
|
|
<Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
|
|
<Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
|
|
<Enum name="MODE_0_" start="0" description="Mode 0." />
|
|
<Enum name="MODE_1_" start="1" description="Mode 1." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AUTORESTART" description="Start mode">
|
|
<Enum name="NO_RESTART" start="0" description="No restart" />
|
|
<Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
|
|
</BitField>
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write only accessible).">
|
|
<Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." />
|
|
<Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write only accessible).">
|
|
<Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." />
|
|
<Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA (remote control) mode." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable">
|
|
<Enum name="IRDA_MODE_IS_DISABLE" start="0" description="IrDA mode is disabled, USARTn acts as a standard USART." />
|
|
<Enum name="IRDA_MODE_IS_ENABLED" start="1" description="IrDA mode is enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="IRDAINV" description="Serial input inverter">
|
|
<Enum name="INVERTED" start="0" description="The serial input is not inverted." />
|
|
<Enum name="NOT_INVERTED" start="1" description="The serial input is inverted. This has no effect on the serial output." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
|
|
<Enum name="DISABLED" start="0" description="IrDA fixed pulse width mode disabled." />
|
|
<Enum name="ENABLED" start="1" description="IrDA fixed pulse width mode enabled." />
|
|
</BitField>
|
|
<BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse width when FixPulseEn = 1.">
|
|
<Enum name="3_DIV_16_X_BAUD_RATE" start="0x0" description="3 / (16 x baud rate)" />
|
|
<Enum name="2_X_TPCLK" start="0x1" description="2 x TPCLK" />
|
|
<Enum name="4_X_TPCLK" start="0x2" description="4 x TPCLK" />
|
|
<Enum name="8_X_TPCLK" start="0x3" description="8 x TPCLK" />
|
|
<Enum name="16_X_TPCLK" start="0x4" description="16 x TPCLK" />
|
|
<Enum name="32_X_TPCLK" start="0x5" description="32 x TPCLK" />
|
|
<Enum name="64_X_TPCLK" start="0x6" description="64 x TPCLK" />
|
|
<Enum name="128_X_TPCLK" start="0x7" description="128 x TPCLK" />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
|
|
<BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
|
|
<BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
|
|
<BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
|
|
<BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half duplex enable register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
|
|
<Enum name="DISABLE_HALF_DUPLEX_" start="0" description="Disable half-duplex mode." />
|
|
<Enum name="ENABLE_HALF_DUPLEX_M" start="1" description="Enable half-duplex mode." />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface Control register. Enables and configures the Smart Card Interface feature." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
|
|
<Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." />
|
|
<Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
|
|
<Enum name="ENABLED" start="0" description="A NACK response is enabled." />
|
|
<Enum name="DISABLED" start="1" description="A NACK response is inhibited." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
|
|
<Enum name="T_EQ_0" start="0" description="T = 0" />
|
|
<Enum name="T_EQ_1" start="1" description="T = 1" />
|
|
</BitField>
|
|
<BitField start="3" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="5" size="3" name="TXRETRY" description="When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared." />
|
|
<BitField start="8" size="8" name="XTRAGUARD" description="When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character" />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="NMMEN" description="NMM enable.">
|
|
<Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
|
|
<Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
|
|
<Enum name="THE_RECEIVER_IS_ENAB" start="0" description="The receiver is enabled." />
|
|
<Enum name="THE_RECEIVER_IS_DISA" start="1" description="The receiver is disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="AADEN" description="AAD enable.">
|
|
<Enum name="AUTO_ADDRESS_DETECT_" start="0" description="Auto Address Detect (AAD) is disabled." />
|
|
<Enum name="AUTO_ADDRESS_DETECT_" start="1" description="Auto Address Detect (AAD) is enabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="SEL" description="Select direction control pin">
|
|
<Enum name="RTS" start="0" description="If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
|
|
<Enum name="DTR" start="1" description="If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="DCTRL" description="Auto direction control enable.">
|
|
<Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
|
|
<Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OINV" description="Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
|
|
<Enum name="LOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
|
|
<Enum name="HIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CSRC" description="Clock source select.">
|
|
<Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" />
|
|
<Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="FES" description="Falling edge sampling.">
|
|
<Enum name="RISING" start="0" description="RxD is sampled on the rising edge of SCLK " />
|
|
<Enum name="FALLING" start="1" description="RxD is sampled on the falling edge of SCLK" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
|
|
<Enum name="SYNC" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic" />
|
|
<Enum name="NOSYNC" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
|
|
<Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" />
|
|
<Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SSDIS" description="Start/stop bits">
|
|
<Enum name="SEND_START_AND_STOP_" start="0" description="Send start and stop bits as in other modes." />
|
|
<Enum name="DO_NOT_SEND_STARTSTOP" start="1" description="Do not send start/stop bits." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
|
|
<Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." />
|
|
<Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." />
|
|
</BitField>
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CT16B0" start="0x4000C000" description="16-bit counter/timers CT16B0">
|
|
<Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
|
|
<BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
|
|
<BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
|
|
<BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
|
|
<BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
|
|
<BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
|
|
<BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CEN" description="Counter enable.">
|
|
<Enum name="DISABLED" start="0" description="The counters are disabled." />
|
|
<Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CRST" description="Counter reset.">
|
|
<Enum name="NOP" start="0" description="Do nothing." />
|
|
<Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="TCVAL" description="Timer counter value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="PCVAL" description="Prescale value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="PC" description="Prescale counter value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." />
|
|
<BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." />
|
|
<BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 267 shows the encoding of these bits.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." />
|
|
<Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." />
|
|
<Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." />
|
|
<Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." />
|
|
<Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
|
|
<Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Increments every rising PCLK edge" />
|
|
<Enum name="RISING" start="0x1" description="Counter Moderising edge. . TC is incremented on rising edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="FALLING" start="0x2" description="Counter Mode falling edge: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="DUAL" start="0x3" description="Counter Mode dual edge: TC is incremented on both edges on the CAP input selected by bits 3:2." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 isreserved.">
|
|
<Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." />
|
|
<Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." />
|
|
<Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
|
|
<BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
|
|
<Enum name="CAP0RISING" start="0x0" description="Rising Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP0FALLING" start="0x1" description="Falling Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1RISING" start="0x2" description="Rising Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1FALLING" start="0x3" description="Falling Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP2RISING" start="0x4" description="Rising Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1FALLING" start="0x5" description="Falling Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
|
|
<Enum name="EM0" start="0" description="CT16Bn_MAT0 is controlled by EM0." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT0." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
|
|
<Enum name="EM1" start="0" description="CT16Bn_MAT01 is controlled by EM1." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT1." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
|
|
<Enum name="EM2" start="0" description="CT16Bn_MAT2 is controlled by EM2." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT2." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3.">
|
|
<Enum name="EM3" start="0" description="CT16Bn_MAT3 is controlled by EM3." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT3." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CT16B1" start="0x40010000" description="16-bit counter/timers CT16B1">
|
|
<Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
|
|
<BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
|
|
<BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
|
|
<BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
|
|
<BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
|
|
<BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
|
|
<BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CEN" description="Counter enable.">
|
|
<Enum name="DISABLED" start="0" description="The counters are disabled." />
|
|
<Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CRST" description="Counter reset.">
|
|
<Enum name="NOP" start="0" description="Do nothing." />
|
|
<Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="TCVAL" description="Timer counter value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="PCVAL" description="Prescale value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="PC" description="Prescale counter value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." />
|
|
<BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." />
|
|
<BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 267 shows the encoding of these bits.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." />
|
|
<Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." />
|
|
<Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." />
|
|
<Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear. Clear the
corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is
LOW if pinned out)." />
|
|
<Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1
(CT16Bn_MAT0 pin is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding
External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
|
|
<Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Increments every rising PCLK edge" />
|
|
<Enum name="RISING" start="0x1" description="Counter Moderising edge. . TC is incremented on rising edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="FALLING" start="0x2" description="Counter Mode falling edge: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="DUAL" start="0x3" description="Counter Mode dual edge: TC is incremented on both edges on the CAP input selected by bits 3:2." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 isreserved.">
|
|
<Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." />
|
|
<Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." />
|
|
<Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
|
|
<BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
|
|
<Enum name="CAP0RISING" start="0x0" description="Rising Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP0FALLING" start="0x1" description="Falling Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1RISING" start="0x2" description="Rising Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1FALLING" start="0x3" description="Falling Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP2RISING" start="0x4" description="Rising Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1FALLING" start="0x5" description="Falling Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
|
|
<Enum name="EM0" start="0" description="CT16Bn_MAT0 is controlled by EM0." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT0." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
|
|
<Enum name="EM1" start="0" description="CT16Bn_MAT01 is controlled by EM1." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT1." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
|
|
<Enum name="EM2" start="0" description="CT16Bn_MAT2 is controlled by EM2." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT2." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3.">
|
|
<Enum name="EM3" start="0" description="CT16Bn_MAT3 is controlled by EM3." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT3." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CT32B0" start="0x40014000" description="32-bit counter/timers CT32B0">
|
|
<Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
|
|
<BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
|
|
<BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
|
|
<BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
|
|
<BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
|
|
<BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
|
|
<BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CEN" description="Counter enable.">
|
|
<Enum name="DISABLED" start="0" description="The counters are disabled." />
|
|
<Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CRST" description="Counter reset.">
|
|
<Enum name="NOP" start="0" description="Do nothing." />
|
|
<Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="TCVAL" description="Timer counter value." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PCVAL" description="Prescaler value." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PC" description="Prescale counter value." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." />
|
|
<Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." />
|
|
<Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." />
|
|
<Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." />
|
|
<Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment the Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
|
|
<Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Increments every rising PCLK edge" />
|
|
<Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="COUNTER_MODE_DUAL_ED" start="0x3" description="Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 is reserved.">
|
|
<Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." />
|
|
<Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." />
|
|
<Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
|
|
<BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
|
|
<Enum name="CAP0RISING" start="0x0" description="Rising Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP0FALLING" start="0x1" description="Falling Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1RISING" start="0x2" description="Rising Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1FALLING" start="0x3" description="Falling Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP2RISING" start="0x4" description="Rising Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP2FALLING" start="0x5" description="Falling Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
|
|
<Enum name="EM0" start="0" description="CT32Bn_MAT0 is controlled by EM0." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT0." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
|
|
<Enum name="EM1" start="0" description="CT32Bn_MAT01 is controlled by EM1." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT1." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
|
|
<Enum name="EM2" start="0" description="CT32Bn_MAT2 is controlled by EM2." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT2." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.">
|
|
<Enum name="EM3" start="0" description="CT32Bn_MAT3 is controlled by EM3." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT132Bn_MAT3." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CT32B1" start="0x40018000" description="32-bit counter/timers CT32B1">
|
|
<Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
|
|
<BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
|
|
<BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
|
|
<BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
|
|
<BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
|
|
<BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
|
|
<BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CEN" description="Counter enable.">
|
|
<Enum name="DISABLED" start="0" description="The counters are disabled." />
|
|
<Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CRST" description="Counter reset.">
|
|
<Enum name="NOP" start="0" description="Do nothing." />
|
|
<Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="TCVAL" description="Timer counter value." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PCVAL" description="Prescaler value." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="PC" description="Prescale counter value." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.">
|
|
<Enum name="ENABLED" start="1" description="Enabled." />
|
|
<Enum name="DISABLED" start="0" description="Disabled." />
|
|
</BitField>
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
|
|
</Register>
|
|
<Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
|
|
<BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." />
|
|
<Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." />
|
|
<Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." />
|
|
<Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
|
|
<Enum name="NOP" start="0x0" description="Do Nothing." />
|
|
<Enum name="CLEAR" start="0x1" description="Clear the corresponding
External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned
out)." />
|
|
<Enum name="SET" start="0x2" description="Set
the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin
is HIGH if pinned out)." />
|
|
<Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment the Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
|
|
<Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Increments every rising PCLK edge" />
|
|
<Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
|
|
<Enum name="COUNTER_MODE_DUAL_ED" start="0x3" description="Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 is reserved.">
|
|
<Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." />
|
|
<Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." />
|
|
<Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
|
|
<BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
|
|
<Enum name="CAP0RISING" start="0x0" description="Rising Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP0FALLING" start="0x1" description="Falling Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1RISING" start="0x2" description="Rising Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP1FALLING" start="0x3" description="Falling Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP2RISING" start="0x4" description="Rising Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." />
|
|
<Enum name="CAP2FALLING" start="0x5" description="Falling Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
|
|
<Enum name="EM0" start="0" description="CT32Bn_MAT0 is controlled by EM0." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT0." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
|
|
<Enum name="EM1" start="0" description="CT32Bn_MAT01 is controlled by EM1." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT1." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
|
|
<Enum name="EM2" start="0" description="CT32Bn_MAT2 is controlled by EM2." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT2." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.">
|
|
<Enum name="EM3" start="0" description="CT32Bn_MAT3 is controlled by EM3." />
|
|
<Enum name="PWM" start="1" description="PWM mode is enabled for CT132Bn_MAT3." />
|
|
</BitField>
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="ADC" start="0x4001C000" description="12-bit Analog-to-Digital Converter (ADC)">
|
|
<Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="A/D Control Register. Contains the clock divide value, enable bits for each sequence and the A/D power-down bit." reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="CLKDIV" description="The system clock is divided by this value plus one to produce the clock for the A/D converter, which should be less than or equal to 50 MHz (up to 100 MHz in 10-bit mode). Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
|
|
<BitField start="8" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="LPWRMODE" description="Select low-power ADC mode. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately 15 ADC clock delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. This mode will NOT power-up the A/D if the ADC_ENA bit is low.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The low-power ADC mode is enabled." />
|
|
</BitField>
|
|
<BitField start="30" size="1" name="CAL_MODE" description="Writing a 1 to this bit initiates a self-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted until the full calibration cycle has ended." />
|
|
<BitField start="31" size="1" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="SEQA_CTRL" access="Read/Write" description="A/D Conversion Sequence-A control Register: Controls triggering and channel selection for conversion sequence-A. Also specifies interrupt mode for sequence-A." reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="CHANNELS" description="Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQA_ENA bit (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write." />
|
|
<BitField start="12" size="3" name="TRIGGER" description="Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field." />
|
|
<BitField start="15" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="18" size="1" name="TRIGPOL" description="Select the polarity of the selected input trigger for this conversion sequence.">
|
|
<Enum name="NEGATIVE_EDGE" start="0" description="Negative edge. A negative edge launches the conversion sequence on the selected trigger input." />
|
|
<Enum name="POSITIVE_EDGE" start="1" description="Positive edge. A positive edge launches the conversion sequence on the selected trigger input." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="SYNCBYPASS" description="Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.">
|
|
<Enum name="ENABLE_SYNCHRONIZATI" start="0" description="Enable synchronization. The hardware trigger bypass is not enabled." />
|
|
<Enum name="BYPASS_SYNCHRONIZATI" start="1" description="Bypass synchronization. The hardware trigger bypass is enabled." />
|
|
</BitField>
|
|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="26" size="1" name="START" description="Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero." />
|
|
<BitField start="27" size="1" name="BURST" description="Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated." />
|
|
<BitField start="28" size="1" name="SINGLESTEP" description="When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit." />
|
|
<BitField start="29" size="1" name="LOWPRIO" description="Set priority for sequence A.">
|
|
<Enum name="LOW_PRIORITY" start="0" description="Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost." />
|
|
<Enum name="HIGH_PRIORITY" start="1" description="High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt this sequence and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point." />
|
|
</BitField>
|
|
<BitField start="30" size="1" name="MODE" description="Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below:">
|
|
<Enum name="END_OF_CONVERSION" start="0" description="End of conversion. The sequence A interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled." />
|
|
<Enum name="END_OF_SEQUENCE" start="1" description="End of sequence. The sequence A interrupt/DMA flag will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register may not be utilized in this mode." />
|
|
</BitField>
|
|
<BitField start="31" size="1" name="SEQA_ENA" description="Sequence Enable">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Sequence A is disabled. Sequence A triggers are ignored. If this bit is cleared while sequence A is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Sequence A is enabled." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="SEQB_CTRL" access="Read/Write" description="A/D Conversion Sequence-B Control Register: Controls triggering and channel selection for conversion sequence-B. Also specifies interrupt mode for sequence-B." reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="12" name="CHANNELS" description="Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQB_ENA bit (bit 31) is LOW. It is permissible to change this field and set bit 31 in the same write." />
|
|
<BitField start="12" size="3" name="TRIGGER" description="Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field." />
|
|
<BitField start="15" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="18" size="1" name="TRIGPOL" description="Select the polarity of the selected input trigger for this conversion sequence.">
|
|
<Enum name="NEGATIVE_EDGE" start="0" description="Negative edge. A negative edge launches the conversion sequence on the selected trigger input." />
|
|
<Enum name="POSITIVE_EDGE" start="1" description="Positive edge. A positive edge launches the conversion sequence on the selected trigger input." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="SYNCBYPASS" description="Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.">
|
|
<Enum name="ENABLE_SYNCHRONIZATI" start="0" description="Enable synchronization. The hardware trigger bypass is not enabled." />
|
|
<Enum name="BYPASS_SYNCHRONIZATI" start="1" description="Bypass synchronization. The hardware trigger bypass is enabled." />
|
|
</BitField>
|
|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="26" size="1" name="START" description="Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write a 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero." />
|
|
<BitField start="27" size="1" name="BURST" description="Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other B triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated." />
|
|
<BitField start="28" size="1" name="SINGLESTEP" description="When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit." />
|
|
<BitField start="29" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="30" size="1" name="MODE" description="Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQB_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-B will be generated and which overrun conditions contribute to an overrun interrupt as described below:">
|
|
<Enum name="END_OF_CONVERSION" start="0" description="End of conversion. The sequence B interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence B. This flag will mirror the DATAVALID bit in the SEQB_GDAT register. The OVERRUN bit in the SEQB_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled." />
|
|
<Enum name="END_OF_SEQUENCE" start="1" description="End of sequence. The sequence B interrupt/DMA flag will be set when the entire set of sequence B conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQB_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register will not be utilized in this mode." />
|
|
</BitField>
|
|
<BitField start="31" size="1" name="SEQB_ENA" description="Sequence Enable">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Sequence B is disabled. Sequence B triggers are ignored. If this bit is cleared while sequence B is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Sequence B is enabled." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="SEQA_GDAT" access="Read/Write" description="A/D Sequence-A Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-A" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is the a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read." />
|
|
<BitField start="16" size="2" name="THCMPRANGE" description="Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH)." />
|
|
<BitField start="18" size="2" name="THCMPCROSS" description="Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred." />
|
|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="26" size="4" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1...)." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled)." />
|
|
<BitField start="31" size="1" name="DATAVALID" description="This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="SEQB_GDAT" access="Read/Write" description="A/D Sequence-B Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-B" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. This will be a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on V REFP. DATAVALID = 1 indicates that this result has not yet been read." />
|
|
<BitField start="16" size="2" name="THCMPRANGE" description="Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
|
|
<BitField start="18" size="2" name="THCMPCROSS" description="Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
|
|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="26" size="4" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 0b0000 identifies channel 0, 0b0001 channel 1...)." />
|
|
<BitField start="30" size="1" name="OVERRUN" description="This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQB_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled)." />
|
|
<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)." />
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|
</Register>
|
|
<Register start="+0x020+0" size="4" name="DAT[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
|
|
<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
|
|
<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
|
|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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|
<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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|
<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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|
</Register>
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|
<Register start="+0x020+4" size="4" name="DAT[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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|
<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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|
<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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|
</Register>
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|
<Register start="+0x020+8" size="4" name="DAT[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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|
<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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|
<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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|
</Register>
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<Register start="+0x020+12" size="4" name="DAT[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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|
<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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|
<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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</Register>
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|
<Register start="+0x020+16" size="4" name="DAT[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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|
<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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</Register>
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|
<Register start="+0x020+20" size="4" name="DAT[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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|
<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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</Register>
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|
<Register start="+0x020+24" size="4" name="DAT[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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|
<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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|
<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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|
<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
|
|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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|
<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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|
<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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|
</Register>
|
|
<Register start="+0x020+28" size="4" name="DAT[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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|
<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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|
<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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|
<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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|
<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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|
</Register>
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|
<Register start="+0x020+32" size="4" name="DAT[8]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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|
<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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</Register>
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<Register start="+0x020+36" size="4" name="DAT[9]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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</Register>
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<Register start="+0x020+40" size="4" name="DAT[10]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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</Register>
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<Register start="+0x020+44" size="4" name="DAT[11]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
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<BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
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<BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
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<BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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<BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
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<BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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<BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
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</Register>
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<Register start="+0x050" size="4" name="THR0_LOW" access="Read/Write" description="A/D Low Compare Threshold Register 0 : Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0." reset_value="0x0" reset_mask="0xFFFFFFFF">
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<BitField start="4" size="12" name="THRLOW" description="Low threshold value against which A/D results will be compared" />
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<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x054" size="4" name="THR1_LOW" access="Read/Write" description="A/D Low Compare Threshold Register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1." reset_value="0x0" reset_mask="0xFFFFFFFF">
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<BitField start="4" size="12" name="THRLOW" description="Low threshold value against which A/D results will be compared" />
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<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x058" size="4" name="THR0_HIGH" access="Read/Write" description="A/D High Compare Threshold Register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0." reset_value="0x0" reset_mask="0xFFFFFFFF">
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<BitField start="4" size="12" name="THRHIGH" description="High threshold value against which A/D results will be compared" />
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<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x05C" size="4" name="THR1_HIGH" access="Read/Write" description="A/D High Compare Threshold Register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1." reset_value="0x0" reset_mask="0xFFFFFFFF">
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<BitField start="4" size="12" name="THRHIGH" description="High threshold value against which A/D results will be compared" />
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<BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
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</Register>
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<Register start="+0x060" size="4" name="CHAN_THRSEL" access="ReadOnly" description="A/D Channel-Threshold Select Register. Specifies which set of threshold compare registers are to be used for each channel" reset_value="0x0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="CH0_THRSEL" description="Threshold select by channel.">
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<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 0 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
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<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 0 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
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</BitField>
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<BitField start="1" size="1" name="CH1_THRSEL" description="Threshold select by channel.">
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<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 1 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
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<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 1 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
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</BitField>
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<BitField start="2" size="1" name="CH2_THRSEL" description="Threshold select by channel.">
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<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 2 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
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<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 2 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
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</BitField>
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<BitField start="3" size="1" name="CH3_THRSEL" description="Threshold select by channel.">
|
|
<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 3 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
|
|
<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 3 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="CH4_THRSEL" description="Threshold select by channel.">
|
|
<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 4 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
|
|
<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 4 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="CH5_THRSEL" description="Threshold select by channel.">
|
|
<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 5 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
|
|
<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 5 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CH6_THRSEL" description="Threshold select by channel.">
|
|
<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 6 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
|
|
<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 6 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CH7_THRSEL" description="Threshold select by channel.">
|
|
<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 7 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
|
|
<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 7 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="CH8_THRSEL" description="Threshold select by channel.">
|
|
<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 8 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
|
|
<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 8 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="CH9_THRSEL" description="Threshold select by channel.">
|
|
<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 9 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
|
|
<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 9 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="CH10_THRSEL" description="Threshold select by channel.">
|
|
<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 10 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
|
|
<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 10 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="CH11_THRSEL" description="Threshold select by channel.">
|
|
<Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 11 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
|
|
<Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 11 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x064" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated." reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SEQA_INTEN" description="Sequence A interrupt enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The sequence A interrupt/DMA request is disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The sequence A interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="SEQB_INTEN" description="Sequence B interrupt enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The sequence B interrupt/DMA request is disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The sequence B interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="OVR_INTEN" description="Overrun interrupt enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The overrun interrupt is disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt request. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt request to be asserted." />
|
|
</BitField>
|
|
<BitField start="3" size="2" name="ADCMPINTEN0" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="5" size="2" name="ADCMPINTEN1" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="7" size="2" name="ADCMPINTEN2" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="9" size="2" name="ADCMPINTEN3" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="ADCMPINTEN4" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="13" size="2" name="ADCMPINTEN5" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="15" size="2" name="ADCMPINTEN6" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="17" size="2" name="ADCMPINTEN7" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="19" size="2" name="ADCMPINTEN8" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="21" size="2" name="ADCMPINTEN9" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="23" size="2" name="ADCMPINTEN10" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="25" size="2" name="ADCMPINTEN11" description="Threshold comparison interrupt enable.">
|
|
<Enum name="DISABLED" start="0x0" description="Disabled." />
|
|
<Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
|
|
<Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x068" size="4" name="FLAGS" access="ReadOnly" description="A/D Flags Register. Contains the four interrupt request flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)." reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="THCMP0" description="Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="1" size="1" name="THCMP1" description="Threshold comparison event on Channel 1. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="2" size="1" name="THCMP2" description="Threshold comparison event on Channel 2. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="3" size="1" name="THCMP3" description="Threshold comparison event on Channel 3. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="4" size="1" name="THCMP4" description="Threshold comparison event on Channel 4. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="5" size="1" name="THCMP5" description="Threshold comparison event on Channel 5. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="6" size="1" name="THCMP6" description="Threshold comparison event on Channel 6. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="7" size="1" name="THCMP7" description="Threshold comparison event on Channel 7. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="8" size="1" name="THCMP8" description="Threshold comparison event on Channel 8. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="9" size="1" name="THCMP9" description="Threshold comparison event on Channel 9. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="10" size="1" name="THCMP10" description="Threshold comparison event on Channel 10. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="11" size="1" name="THCMP11" description="Threshold comparison event on Channel 11. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
|
|
<BitField start="12" size="1" name="OVERRUN0" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 0" />
|
|
<BitField start="13" size="1" name="OVERRUN1" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 1" />
|
|
<BitField start="14" size="1" name="OVERRUN2" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 2" />
|
|
<BitField start="15" size="1" name="OVERRUN3" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 3" />
|
|
<BitField start="16" size="1" name="OVERRUN4" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 4" />
|
|
<BitField start="17" size="1" name="OVERRUN5" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 5" />
|
|
<BitField start="18" size="1" name="OVERRUN6" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 6" />
|
|
<BitField start="19" size="1" name="OVERRUN7" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 7" />
|
|
<BitField start="20" size="1" name="OVERRUN8" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 8" />
|
|
<BitField start="21" size="1" name="OVERRUN9" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 9" />
|
|
<BitField start="22" size="1" name="OVERRUN10" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 10" />
|
|
<BitField start="23" size="1" name="OVERRUN11" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 11" />
|
|
<BitField start="24" size="1" name="SEQA_OVR" description="Mirrors the global OVERRUN status flag in the SEQA_GDAT register" />
|
|
<BitField start="25" size="1" name="SEQB_OVR" description="Mirrors the global OVERRUN status flag in the SEQB_GDAT register" />
|
|
<BitField start="26" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="28" size="1" name="SEQA_INT" description="Sequence A interrupt/DMA flag. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every A/D conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register." />
|
|
<BitField start="29" size="1" name="SEQB_INT" description="Sequence A interrupt/DMA flag. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every A/D conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register." />
|
|
<BitField start="30" size="1" name="THCMP_INT" description="Threshold Comparison Interrupt/DMA flag. This bit will be set if any of the 12 THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the component flags in bits 11:0 are cleared via writing 1s to those bits." />
|
|
<BitField start="31" size="1" name="OVR_INT" description="Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers." />
|
|
</Register>
|
|
<Register start="+0x06C" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0x00000F00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="RESERVED" description="Reserved." />
|
|
<BitField start="5" size="1" name="VRANGE" description="Reserved.">
|
|
<Enum name="HIGH_VOLTAGE" start="0" description="High voltage. VDDA = 2.7 V to 3.6 V." />
|
|
<Enum name="LOW_VOLTAGE" start="1" description="Low voltage. VDDA = 1.8 V to 2.7 V." />
|
|
</BitField>
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="I2C1" start="0x40020000" description="I2C1">
|
|
<Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
|
|
<BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
|
|
<BitField start="4" size="1" name="STO" description="STOP flag." />
|
|
<BitField start="5" size="1" name="STA" description="START flag." />
|
|
<BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
|
|
<BitField start="3" size="5" name="STATUS" description="These bits give the actual status information about the I2C interface." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
|
|
<BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
|
|
<BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
|
|
<Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
|
|
<Enum name="THE_I2C_MODULE_WILL_" start="1" description="The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
|
|
<Enum name="HIGH" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
|
|
<Enum name="NORMAL" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
|
|
<Enum name="MATCH" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." />
|
|
<Enum name="ANYADDRESS" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="GC" description="General Call enable bit." />
|
|
<BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
|
|
</Register>
|
|
<Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
|
|
</Register>
|
|
<Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
|
|
</Register>
|
|
<Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
|
|
<BitField start="1" size="7" name="MASK" description="Mask bits." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="RTC" start="0x40024000" description="Real-Time Clock (RTC)">
|
|
<Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="RTC control register" reset_value="0xF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SWRESET" description="Software reset control">
|
|
<Enum name="NOT_IN_RESET" start="0" description="Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC." />
|
|
<Enum name="IN_RESET" start="1" description="In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. This bit may also serve as a Power Fail Detect flag for the always-on voltage domain." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="OFD" description="Oscillator fail detect status.">
|
|
<Enum name="RUN" start="0" description="Run. The RTC oscillator is running properly. Writing a 0 has no effect." />
|
|
<Enum name="FAIL" start="1" description="Fail. RTC oscillator fail detected. Clear this flag after the following power-up. Writing a 1 clears this bit." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ALARM1HZ" description="RTC 1 Hz timer alarm flag status.">
|
|
<Enum name="NO_MATCH" start="0" description="No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect." />
|
|
<Enum name="MATCH" start="1" description="Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="WAKE1KHZ" description="RTC 1 kHz timer wake-up flag status.">
|
|
<Enum name="RUN" start="0" description="Run. The RTC 1 kHz timer is running. Writing a 0 has no effect." />
|
|
<Enum name="TIME_OUT" start="1" description="Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="ALARMDPD_EN" description="RTC 1 Hz timer alarm enable for Deep power-down.">
|
|
<Enum name="DISABLE" start="0" description="Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode." />
|
|
<Enum name="ENABLE" start="1" description="Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="WAKEDPD_EN" description="RTC 1 kHz timer wake-up enable for Deep power-down.">
|
|
<Enum name="DISABLE" start="0" description="Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode." />
|
|
<Enum name="ENABLE" start="1" description="Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="RTC1KHZ_EN" description="RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).">
|
|
<Enum name="DISABLE" start="0" description="Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode." />
|
|
<Enum name="ENABLE" start="1" description="Enable. The 1 kHz RTC timer is enabled." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RTC_EN" description="RTC enable.">
|
|
<Enum name="DISABLE" start="0" description="Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register." />
|
|
<Enum name="ENABLE" start="1" description="Enable. The 1 Hz RTC clock is running and RTC operation is enabled. You must set this bit to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="MATCH" access="Read/Write" description="RTC match register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="MATVAL" description="Contains the match value against which the 1 Hz RTC timer will be compared to generate set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="COUNT" access="Read/Write" description="RTC counter register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="VAL" description="A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC1HZ_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC1HZ_EN bit is set." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="WAKE" access="Read/Write" description="RTC high-resolution/wake-up timer control register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="VAL" description="A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="DMATRIGMUX" start="0x40028000" description="DMA controller">
|
|
<Register start="+0x000+0" size="4" name="DMA_ITRIG_PINMUX[0]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+4" size="4" name="DMA_ITRIG_PINMUX[1]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+8" size="4" name="DMA_ITRIG_PINMUX[2]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+12" size="4" name="DMA_ITRIG_PINMUX[3]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+16" size="4" name="DMA_ITRIG_PINMUX[4]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+20" size="4" name="DMA_ITRIG_PINMUX[5]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+24" size="4" name="DMA_ITRIG_PINMUX[6]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+28" size="4" name="DMA_ITRIG_PINMUX[7]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+32" size="4" name="DMA_ITRIG_PINMUX[8]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+36" size="4" name="DMA_ITRIG_PINMUX[9]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+40" size="4" name="DMA_ITRIG_PINMUX[10]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+44" size="4" name="DMA_ITRIG_PINMUX[11]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+48" size="4" name="DMA_ITRIG_PINMUX[12]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+52" size="4" name="DMA_ITRIG_PINMUX[13]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+56" size="4" name="DMA_ITRIG_PINMUX[14]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+60" size="4" name="DMA_ITRIG_PINMUX[15]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0	 = ADC0_SEQA_IRQ 1 = 	ADC0_SEQB_IRQ 2	 = CT16B0_MAT0 3 = 	CT16B1_MAT0 4	 = CT32B0_MAT0 5	 = CT16B1_MAT0 6	 = PINT0 ( pin interrupt 0) 7 = 	PINT1 (pin interrupt1 ) 8 = 	SCT0_DMA0 9 = 	SCT0_DMA1 10	 = SCT1_DMA0 11	 = SCT1_DMA1" />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="PMU" start="0x40038000" description="Power Management Unit (PMU)">
|
|
<Register start="+0x000" size="4" name="PCON" access="Read/Write" description="Power control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="PM" description="Power mode">
|
|
<Enum name="DEFAULT" start="0x0" description="Default. The part is in active or sleep mode." />
|
|
<Enum name="DEEP_SLEEP" start="0x1" description="Deep-sleep. ARM WFI will enter Deep-sleep mode." />
|
|
<Enum name="POWER_DOWN" start="0x2" description="Power-down. ARM WFI will enter Power-down mode." />
|
|
<Enum name="DEEP_POWER_DOWN" start="0x3" description="Deep power-down. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down)." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="NODPD" description="A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked." />
|
|
<BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to this bit." />
|
|
<BitField start="8" size="1" name="SLEEPFLAG" description="Sleep mode flag">
|
|
<Enum name="ACTIVE_MODE" start="0" description="Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect." />
|
|
<Enum name="LOW_POWER_MODE" start="1" description="Low power mode. Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0." />
|
|
</BitField>
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Do not write ones to this bit." />
|
|
<BitField start="11" size="1" name="DPDFLAG" description="Deep power-down flag">
|
|
<Enum name="NOT_DEEP_POWER_DOWN" start="0" description="Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect." />
|
|
<Enum name="DEEP_POWER_DOWN" start="1" description="Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to this bit." />
|
|
</Register>
|
|
<Register start="+0x004+0" size="4" name="GPREG0" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
|
|
</Register>
|
|
<Register start="+0x004+4" size="4" name="GPREG1" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
|
|
</Register>
|
|
<Register start="+0x004+8" size="4" name="GPREG2" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
|
|
</Register>
|
|
<Register start="+0x004+12" size="4" name="GPREG3" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="GPREG4" access="Read/Write" description="Deep power down control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="RESERVED" description="Reserved. Do not write ones to this bit." />
|
|
<BitField start="10" size="1" name="WAKEUPHYS" description="WAKEUP pin hysteresis enable">
|
|
<Enum name="DISABLE_HYSTERESIS_F" start="0" description="Disable Hysteresis for WAKUP pin disabled." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Hysteresis for WAKEUP pin enabled." />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="WAKEPAD_DISABLE" description="WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the RTC wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used.">
|
|
<Enum name="ENABLE" start="0" description="Enable. The wake-up function is enabled on pin PIO0_16." />
|
|
<Enum name="DISABLE" start="1" description="Disable. Setting this bit disables the wake-up function on pin PIO0_16." />
|
|
</BitField>
|
|
<BitField start="12" size="20" name="GPDATA" description="Data retained during Deep power-down mode." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="FLASHCTRL" start="0x4003C000" description=" Flash controller ">
|
|
<Register start="+0x010" size="4" name="FLASHCFG" access="Read/Write" description="Flash configuration register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="2" name="FLASHTIM" description="Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.">
|
|
<Enum name="1_SYSTEM_CLOCK_FLASH" start="0x0" description="1 system clock flash access time (for system clock frequencies of up to 20 MHz)." />
|
|
<Enum name="2_SYSTEM_CLOCKS_FLAS" start="0x1" description="2 system clocks flash access time (for system clock frequencies of up to 30 MHz)." />
|
|
<Enum name="RESERVED_" start="0x2" description="Reserved." />
|
|
<Enum name="RESERVED_" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="17" name="STOPA" description="Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes. If the option bistprotection=1, bits 2:0 cannot be written and are forced to 111." />
|
|
<BitField start="17" size="1" name="STRTBIST" description="When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="Signature Word " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="SIG" description="32-bit signature." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SSP0" start="0x40040000" description="SSP/SPI ">
|
|
<Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
|
|
<Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
|
|
<Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
|
|
<Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
|
|
<Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
|
|
<Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
|
|
<Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
|
|
<Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
|
|
<Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
|
|
<Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
|
|
<Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
|
|
<Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
|
|
<Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
|
|
<Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="FRF" description="Frame Format.">
|
|
<Enum name="SPI" start="0x0" description="SPI" />
|
|
<Enum name="TI" start="0x1" description="TI" />
|
|
<Enum name="MICROWIRE" start="0x2" description="Microwire" />
|
|
<Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
|
|
<Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." />
|
|
<Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
|
|
<Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
|
|
<Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
|
|
</BitField>
|
|
<BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
|
|
<Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." />
|
|
<Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="SSE" description="SPI Enable.">
|
|
<Enum name="DISABLED" start="0" description="The SPI controller is disabled." />
|
|
<Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
|
|
<Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
|
|
<Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
|
|
<BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
|
|
<BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
|
|
<BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
|
|
<BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
|
|
<BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
|
|
<BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
|
|
<BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
|
|
<BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
|
|
<BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
|
|
<BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
|
|
<BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="IOCON" start="0x40044000" description="I/O control (IOCON) ">
|
|
<Register start="+0x000+0" size="4" name="PIO0_0" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+4" size="4" name="PIO0_1" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+8" size="4" name="PIO0_2" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x000+12" size="4" name="PIO0_3" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="PIO0_4" access="Read/Write" description="I/O configuration for open-drain pin PIO0_4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function. " />
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).">
|
|
<Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." />
|
|
<Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" />
|
|
<Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="PIO0_5" access="Read/Write" description="I/O configuration for open-drain pin PIO0_5" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function. " />
|
|
<BitField start="3" size="5" name="RESERVED" description="Reserved." />
|
|
<BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).">
|
|
<Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." />
|
|
<Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" />
|
|
<Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+0" size="4" name="PIO0_6" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+4" size="4" name="PIO0_7" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+8" size="4" name="PIO0_8" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+12" size="4" name="PIO0_9" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+16" size="4" name="PIO0_10" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+20" size="4" name="PIO0_11" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+24" size="4" name="PIO0_12" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+28" size="4" name="PIO0_13" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+32" size="4" name="PIO0_14" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+36" size="4" name="PIO0_15" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+40" size="4" name="PIO0_16" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+44" size="4" name="PIO0_17" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+48" size="4" name="PIO0_18" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+52" size="4" name="PIO0_19" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+56" size="4" name="PIO0_20" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+60" size="4" name="PIO0_21" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+64" size="4" name="PIO0_22" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018+68" size="4" name="PIO0_23" access="Read/Write" description="I/O configuration for port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+0" size="4" name="PIO1_0" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+4" size="4" name="PIO1_1" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+8" size="4" name="PIO1_2" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+12" size="4" name="PIO1_3" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+16" size="4" name="PIO1_4" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+20" size="4" name="PIO1_5" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+24" size="4" name="PIO1_6" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+28" size="4" name="PIO1_7" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+32" size="4" name="PIO1_8" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+36" size="4" name="PIO1_9" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+40" size="4" name="PIO1_10" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+44" size="4" name="PIO1_11" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+48" size="4" name="PIO1_12" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+52" size="4" name="PIO1_13" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+56" size="4" name="PIO1_14" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+60" size="4" name="PIO1_15" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+64" size="4" name="PIO1_16" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+68" size="4" name="PIO1_17" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+72" size="4" name="PIO1_18" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+76" size="4" name="PIO1_19" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+80" size="4" name="PIO1_20" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+84" size="4" name="PIO1_21" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+88" size="4" name="PIO1_22" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+92" size="4" name="PIO1_23" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+96" size="4" name="PIO1_24" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+100" size="4" name="PIO1_25" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+104" size="4" name="PIO1_26" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+108" size="4" name="PIO1_27" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+112" size="4" name="PIO1_28" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+116" size="4" name="PIO1_29" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+120" size="4" name="PIO1_30" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060+124" size="4" name="PIO1_31" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0F0+0" size="4" name="PIO2_0" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0F0+4" size="4" name="PIO2_1" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+0" size="4" name="PIO2_2" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+4" size="4" name="PIO2_3" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+8" size="4" name="PIO2_4" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+12" size="4" name="PIO2_5" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+16" size="4" name="PIO2_6" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+20" size="4" name="PIO2_7" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+24" size="4" name="PIO2_8" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+28" size="4" name="PIO2_9" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+32" size="4" name="PIO2_10" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+36" size="4" name="PIO2_11" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+40" size="4" name="PIO2_12" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+44" size="4" name="PIO2_13" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+48" size="4" name="PIO2_14" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+52" size="4" name="PIO2_15" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+56" size="4" name="PIO2_16" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+60" size="4" name="PIO2_17" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+64" size="4" name="PIO2_18" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+68" size="4" name="PIO2_19" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+72" size="4" name="PIO2_20" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+76" size="4" name="PIO2_21" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+80" size="4" name="PIO2_22" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x0FC+84" size="4" name="PIO2_23" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="3" name="FUNC" description="Selects pin function." />
|
|
<BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
|
|
<Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
|
|
<Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
|
|
<Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
|
|
<Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="HYS" description="Hysteresis.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLE" start="1" description="Enable." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="INV" description="Invert input">
|
|
<Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
|
|
<Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
|
|
</BitField>
|
|
<BitField start="7" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="10" size="1" name="OD" description="Open-drain mode.">
|
|
<Enum name="DISABLE" start="0" description="Disable." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled. This is not a true open-drain mode." />
|
|
</BitField>
|
|
<BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
|
|
<Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
|
|
<Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
|
|
<Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
|
|
<Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
|
|
</BitField>
|
|
<BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
|
|
<Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
|
|
<Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
|
|
<Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
|
|
<Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
|
|
<Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
|
|
<Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
|
|
<Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
|
|
</BitField>
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SYSCON" start="0x40048000" description="System configuration (SYSCON)">
|
|
<Register start="+0x000" size="4" name="SYSMEMREMAP" access="Read/Write" description="System memory remap" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="MAP" description="System memory remap. Value 0x3 is reserved.">
|
|
<Enum name="BOOT_LOADER_MODE" start="0x0" description="Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM." />
|
|
<Enum name="USER_RAM_MODE" start="0x1" description="User RAM Mode. Interrupt vectors are re-mapped to Static RAM." />
|
|
<Enum name="USER_FLASH_MODE" start="0x2" description="User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="PRESETCTRL" access="Read/Write" description="Peripheral reset control" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SSP0_RST_N" description="SSP0 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the SSP0 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. SSP0 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="I2C0_RST_N" description="I2C0 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the I2C0 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. I2C0 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SSP1_RST_N" description="SSP1 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the SSP1 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. SSP1 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="I2C1_RST_N" description="I2C1 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the I2C1 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. I2C1 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="FRG_RST_N" description="FRG reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the FRG peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. FRG reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="USART1_RST_N" description="USART1 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the USART1 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. USART1 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="USART2_RST_N" description="USART2 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the USART2 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. USART2 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="USART3_RST_N" description="USART3 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the USART3 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. USART3 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="USART4_RST_N" description="USART4 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the USART4 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. USART4 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="SCT0_RST_N" description="SCT0 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the SCT0 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. SCT0 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="SCT1_RST_N" description="SCT1 reset control">
|
|
<Enum name="RESET" start="0" description="Reset. Resets the SCT1 peripheral." />
|
|
<Enum name="CLEAR_RESET" start="1" description="Clear reset. SCT1 reset de-asserted." />
|
|
</BitField>
|
|
<BitField start="11" size="21" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="SYSPLLCTRL" access="Read/Write" description="System PLL control" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32" />
|
|
<BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P.">
|
|
<Enum name="P_EQ_1" start="0x0" description="P = 1" />
|
|
<Enum name="P_EQ_2" start="0x1" description="P = 2" />
|
|
<Enum name="P_EQ_4" start="0x2" description="P = 4" />
|
|
<Enum name="P_EQ_8" start="0x3" description="P = 8" />
|
|
</BitField>
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="SYSPLLSTAT" access="ReadOnly" description="System PLL status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="LOCK" description="PLL lock status">
|
|
<Enum name="NO_LOCK" start="0" description="No lock. PLL not locked" />
|
|
<Enum name="LOCK" start="1" description="Lock. PLL locked" />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="USBPLLCTRL" access="Read/Write" description="USB PLL control" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32" />
|
|
<BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P.">
|
|
<Enum name="P_EQ_1" start="0x0" description="P = 1" />
|
|
<Enum name="P_EQ_2" start="0x1" description="P = 2" />
|
|
<Enum name="P_EQ_4" start="0x2" description="P = 4" />
|
|
<Enum name="P_EQ_8" start="0x3" description="P = 8" />
|
|
</BitField>
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="USBPLLSTAT" access="ReadOnly" description="USB PLL status" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="LOCK" description="PLL lock status">
|
|
<Enum name="NO_LOCK" start="0" description="No lock. PLL not locked" />
|
|
<Enum name="LOCK" start="1" description="Lock. PLL locked" />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="RTCOSCCTRL" access="Read/Write" description="RTC oscillator 32 kHz output control" reset_value="0x1" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RTCOSCEN" description="Enable the RTC 32 kHz output.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. 32 kHz output disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. 32 kHz output enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="SYSOSCCTRL" access="Read/Write" description="System oscillator control" reset_value="0x000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="BYPASS" description="Bypass system oscillator">
|
|
<Enum name="OSCILLATOR_IS_NOT_BY" start="0" description="Oscillator is not bypassed." />
|
|
<Enum name="BYPASS_ENABLED" start="1" description="Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="FREQRANGE" description="Determines frequency range for Low-power oscillator.">
|
|
<Enum name="LOW" start="0" description="Low. 1 - 20 MHz frequency range." />
|
|
<Enum name="HIGH" start="1" description="High. 15 - 25 MHz frequency range." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="WDTOSCCTRL" access="Read/Write" description="Watchdog oscillator control" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="DIVSEL" description="Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64" />
|
|
<BitField start="5" size="4" name="FREQSEL" description="Select watchdog oscillator analog output frequency (Fclkana).">
|
|
<Enum name="0" start="0x1" description="0.6 MHz" />
|
|
<Enum name="1" start="0x2" description="1.05 MHz" />
|
|
<Enum name="1" start="0x3" description="1.4 MHz" />
|
|
<Enum name="1" start="0x4" description="1.75 MHz" />
|
|
<Enum name="2" start="0x5" description="2.1 MHz" />
|
|
<Enum name="2" start="0x6" description="2.4 MHz" />
|
|
<Enum name="2" start="0x7" description="2.7 MHz" />
|
|
<Enum name="3" start="0x8" description="3.0 MHz" />
|
|
<Enum name="3" start="0x9" description="3.25 MHz" />
|
|
<Enum name="3" start="0xA" description="3.5 MHz" />
|
|
<Enum name="3" start="0xB" description="3.75 MHz" />
|
|
<Enum name="4" start="0xC" description="4.0 MHz" />
|
|
<Enum name="4" start="0xD" description="4.2 MHz" />
|
|
<Enum name="4" start="0xE" description="4.4 MHz" />
|
|
<Enum name="4" start="0xF" description="4.6 MHz" />
|
|
</BitField>
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="IRCCTRL" access="Read/Write" description="IRC control" reset_value="0x080" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="TRIM" description="Trim value" />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="SYSRSTSTAT" access="Read/Write" description="System reset status register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="POR" description="POR reset status">
|
|
<Enum name="NO_POR_DETECTED" start="0" description="No POR detected" />
|
|
<Enum name="POR_DETECTED" start="1" description="POR detected" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="EXTRST" description="Status of the external RESET pin">
|
|
<Enum name="NO_RESET_EVENT_DETEC" start="0" description="No reset event detected" />
|
|
<Enum name="RESET_DETECTED" start="1" description="Reset detected" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="WDT" description="Status of the Watchdog reset">
|
|
<Enum name="NO_WDT_RESET_DETECTE" start="0" description="No WDT reset detected" />
|
|
<Enum name="WDT_RESET_DETECTED" start="1" description="WDT reset detected" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="BOD" description="Status of the Brown-out detect reset">
|
|
<Enum name="NO_BOD_RESET_DETECTE" start="0" description="No BOD reset detected" />
|
|
<Enum name="BOD_RESET_DETECTED" start="1" description="BOD reset detected" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SYSRST" description="Status of the software system reset">
|
|
<Enum name="NO_SYSTEM_RESET_DETE" start="0" description="No System reset detected" />
|
|
<Enum name="SYSTEM_RESET_DETECTE" start="1" description="System reset detected" />
|
|
</BitField>
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x040" size="4" name="SYSPLLCLKSEL" access="Read/Write" description="System PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="SEL" description="System PLL clock source">
|
|
<Enum name="IRC" start="0x0" description="IRC" />
|
|
<Enum name="SYSTEM_OSCILLATOR" start="0x1" description="System oscillator. Crystal Oscillator (SYSOSC)" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="32_KHZ_CLOCK" start="0x3" description="32 kHz clock.Select this option when the 32 kHz clock is the clock source for the main clock and select the pll input in the MAINCLKSEL register. Do not use the 32 kHz clock with the PLL." />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x044" size="4" name="SYSPLLCLKUEN" access="Read/Write" description="System PLL clock source update enable" reset_value="0x1" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENA" description="Enable system PLL clock source update">
|
|
<Enum name="NO_CHANGE" start="0" description="No change" />
|
|
<Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x048" size="4" name="USBPLLCLKSEL" access="Read/Write" description="USB PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="SEL" description="USB PLL clock source">
|
|
<Enum name="IRC" start="0x0" description="IRC. For full-speed USB, switch the USB PLL clock source to the system oscillator for correct USB operation. The IRC is suitable for low-speed USB operation only." />
|
|
<Enum name="SYSTEM_OSCILLATOR" start="0x1" description="System oscillator" />
|
|
<Enum name="RESERVED" start="0x2" description="Reserved" />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved" />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="USBPLLCLKUEN" access="Read/Write" description="USB PLL clock source update enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENA" description="Enable USB PLL clock source update">
|
|
<Enum name="NO_CHANGE" start="0" description="No change" />
|
|
<Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="MAINCLKSEL" access="Read/Write" description="Main clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="SEL" description="Clock source for main clock">
|
|
<Enum name="IRC_OSCILLATOR" start="0x0" description="IRC Oscillator" />
|
|
<Enum name="PLL_INPUT" start="0x1" description="PLL input" />
|
|
<Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" />
|
|
<Enum name="PLL_OUTPUT" start="0x3" description="PLL output" />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x074" size="4" name="MAINCLKUEN" access="Read/Write" description="Main clock source update enable" reset_value="0x1" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENA" description="Enable main clock source update">
|
|
<Enum name="NO_CHANGE" start="0" description="No change" />
|
|
<Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x078" size="4" name="SYSAHBCLKDIV" access="Read/Write" description="System clock divider" reset_value="0x001" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x080" size="4" name="SYSAHBCLKCTRL" access="Read/Write" description="System clock control" reset_value="0x3F" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SYS" description="This bit is read-only and always reads as 1. It configures the always-on clock for the AHB, the APB bridges, the Cortex-M0 core clocks, SYSCON, reset control, SRAM0, and the PMU. Writes to this bit are ignored." />
|
|
<BitField start="1" size="1" name="ROM" description="Enables clock for ROM.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RAM0" description="Enables clock for Main SRAM0.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="FLASHREG" description="Enables clock for flash register interface.">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="FLASHARRAY" description="Enables clock for flash access.">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="I2C0" description="Enables clock for I2C.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="GPIO" description="Enables clock for GPIO port registers.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CT16B0" description="Enables clock for 16-bit counter/timer 0.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="CT16B1" description="Enables clock for 16-bit counter/timer 1.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="CT32B0" description="Enables clock for 32-bit counter/timer 0.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="CT32B1" description="Enables clock for 32-bit counter/timer 1.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="SSP0" description="Enables clock for SSP0.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="USART0" description="Enables clock for USART0.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="ADC" description="Enables clock for ADC.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="USB" description="Enables clock to the USB register interface.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="WWDT" description="Enables clock for WWDT.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="16" size="1" name="IOCON" description="Enables clock for I/O configuration block.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="17" size="1" name="RESERVED" description="Reserved" />
|
|
<BitField start="18" size="1" name="SSP1" description="Enables clock for SSP1.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="PINT" description="Enables clock to GPIO Pin interrupt register interface.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="USART1" description="Enables clock to USART1 register interface.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="21" size="1" name="USART2" description="Enables clock to USART2 register interface.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="USART3_4" description="Enables clock to USART3 and USART4 register interfaces.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="23" size="1" name="GROUP0INT" description="Enables clock to GPIO GROUP0 interrupt register interface.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="24" size="1" name="GROUP1INT" description="Enables clock to GPIO GROUP1 interrupt register interface.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="25" size="1" name="I2C1" description="Enables clock for I2C1.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="26" size="1" name="RAM1" description="Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="27" size="1" name="USBSRAM" description="Enables USB SRAM/SRAM2 block located at 0x2000 4000 to 0x2000 4800.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="28" size="1" name="CRC" description="Enables clock for CRC.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="29" size="1" name="DMA" description="Enables clock for DMA.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="30" size="1" name="RTC" description="Enables clock for RTC register interface.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
<BitField start="31" size="1" name="SCT0_1" description="Enables clock for SCT0 and SCT1.">
|
|
<Enum name="DISABLE" start="0" description="Disable" />
|
|
<Enum name="ENABLE" start="1" description="Enable" />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x094" size="4" name="SSP0CLKDIV" access="Read/Write" description="SSP0 clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="SPI0_PCLK clock divider values. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x098" size="4" name="USART0CLKDIV" access="Read/Write" description="USART0 clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x09C" size="4" name="SSP1CLKDIV" access="Read/Write" description="SSP1 clock divider" reset_value="0x0000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0A0" size="4" name="FRGCLKDIV" access="Read/Write" description="Clock divider for the common fractional baud rate generator of USART1, USART2, USART3, USART4" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0C0" size="4" name="USBCLKSEL" access="Read/Write" description="USB clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="SEL" description="USB clock source. Values 0x2 and 0x3 are reserved.">
|
|
<Enum name="USB_PLL_OUT" start="0x0" description="USB PLL out" />
|
|
<Enum name="MAIN_CLOCK" start="0x1" description="Main clock" />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0C4" size="4" name="USBCLKUEN" access="Read/Write" description="USB clock source update enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENA" description="Enable USB clock source update">
|
|
<Enum name="NO_CHANGE" start="0" description="No change" />
|
|
<Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0C8" size="4" name="USBCLKDIV" access="Read/Write" description="USB clock source divider" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="USB clock divider values 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0E0" size="4" name="CLKOUTSEL" access="Read/Write" description="CLKOUT clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="SEL" description="CLKOUT clock source">
|
|
<Enum name="IRC_OSCILLATOR" start="0x0" description="IRC oscillator" />
|
|
<Enum name="CRYSTAL_OSCILLATOR" start="0x1" description="Crystal oscillator (SYSOSC)" />
|
|
<Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" />
|
|
<Enum name="MAIN_CLOCK" start="0x3" description="Main clock" />
|
|
</BitField>
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0E4" size="4" name="CLKOUTUEN" access="Read/Write" description="CLKOUT clock source update enable" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENA" description="Enable CLKOUT clock source update">
|
|
<Enum name="NO_CHANGE" start="0" description="No change" />
|
|
<Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0E8" size="4" name="CLKOUTDIV" access="Read/Write" description="CLKOUT clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0F0" size="4" name="UARTFRGDIV" access="Read/Write" description="USART fractional generator divider value" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0F4" size="4" name="UARTFRGMULT" access="Read/Write" description="USART fractional generator multiplier value" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="MULT" description="Numerator of the fractional divider. MULT is equal to the programmed value." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0FC" size="4" name="EXTTRACECMD" access="Read/Write" description="External trace buffer command register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="START" description="Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well." />
|
|
<BitField start="1" size="1" name="STOP" description="Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x100" size="4" name="PIOPORCAP0" access="ReadOnly" description="POR captured PIO status 0" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="24" name="PIOSTAT" description="State of PIO0_23 through PIO0_0 at power-on reset" />
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x104" size="4" name="PIOPORCAP1" access="ReadOnly" description="POR captured PIO status 1" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PIOSTAT" description="State of PIO1_31 through PIO1_0 at power-on reset" />
|
|
</Register>
|
|
<Register start="+0x108" size="4" name="PIOPORCAP2" access="ReadOnly" description="POR captured PIO status 1" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="24" name="PIOSTAT" description="State of PIO2_23 through PIO2_0 at power-on reset" />
|
|
</Register>
|
|
<Register start="+0x134" size="4" name="IOCONCLKDIV6" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x138" size="4" name="IOCONCLKDIV5" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x13C" size="4" name="IOCONCLKDIV4" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x140" size="4" name="IOCONCLKDIV3" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x144" size="4" name="IOCONCLKDIV2" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x148" size="4" name="IOCONCLKDIV1" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x14C" size="4" name="IOCONCLKDIV0" access="Read/Write" description="Peripheral clock to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x150" size="4" name="BODCTRL" access="Read/Write" description="Brown-Out Detect" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="BODRSTLEV" description="BOD reset level">
|
|
<Enum name="LEVEL_0" start="0x0" description="Level 0." />
|
|
<Enum name="LEVEL_1" start="0x1" description="Level 1." />
|
|
<Enum name="LEVEL_2" start="0x2" description="Level 2." />
|
|
<Enum name="LEVEL_3" start="0x3" description="Level 3." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="BODINTVAL" description="BOD interrupt level">
|
|
<Enum name="RESERVED" start="0x0" description="Reserved." />
|
|
<Enum name="RESERVED" start="0x1" description="Reserved" />
|
|
<Enum name="LEVEL_2" start="0x2" description="Level 2." />
|
|
<Enum name="LEVEL_3" start="0x3" description="Level 3." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="BODRSTENA" description="BOD reset enable">
|
|
<Enum name="DISABLE_RESET_FUNCTI" start="0" description="Disable reset function." />
|
|
<Enum name="ENABLE_RESET_FUNCTIO" start="1" description="Enable reset function." />
|
|
</BitField>
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x154" size="4" name="SYSTCKCAL" access="Read/Write" description="System tick counter calibration" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="26" name="CAL" description="System tick timer calibration value" />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x170" size="4" name="IRQLATENCY" access="Read/Write" description="IRQ delay. Allows trade-off between interrupt latency and determinism." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="LATENCY" description="8-bit latency value" />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x174" size="4" name="NMISRC" access="Read/Write" description="NMI Source Control" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="IRQN" description="The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 6 for the list of interrupt sources and their IRQ numbers." />
|
|
<BitField start="5" size="26" name="RESERVED" description="Reserved" />
|
|
<BitField start="31" size="1" name="NMIEN" description="Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0." />
|
|
</Register>
|
|
<Register start="+0x178+0" size="4" name="PINTSEL0" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x178+4" size="4" name="PINTSEL1" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x178+8" size="4" name="PINTSEL2" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x178+12" size="4" name="PINTSEL3" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x178+16" size="4" name="PINTSEL4" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x178+20" size="4" name="PINTSEL5" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x178+24" size="4" name="PINTSEL6" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x178+28" size="4" name="PINTSEL7" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x198" size="4" name="USBCLKCTRL" access="Read/Write" description="USB clock control" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="AP_CLK" description="USB need_clock signal control">
|
|
<Enum name="HARDWARE" start="0" description="Hardware. Under hardware control." />
|
|
<Enum name="FORCED" start="1" description="Forced. Forced HIGH." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="POL_CLK" description="USB need_clock polarity for triggering the USB wake-up interrupt">
|
|
<Enum name="FALLING_EDGE" start="0" description="Falling edge. Falling edge of the USB need_clock triggers the USB wake-up (default)." />
|
|
<Enum name="RISING_EDGE" start="1" description="Rising edge. Rising edge of the USB need_clock triggers the USB wake-up." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="RESERVED" description="Reserved. Only write 0 to this bit." />
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x19C" size="4" name="USBCLKST" access="ReadOnly" description="USB clock status" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="NEED_CLKST" description="USB need_clock signal status">
|
|
<Enum name="LOW" start="0" description="LOW" />
|
|
<Enum name="HIGH" start="1" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x204" size="4" name="STARTERP0" access="Read/Write" description="Start logic 0 interrupt wake-up enable register 0" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PINT0" description="Pin interrupt 0 wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="PINT1" description="Pin interrupt 1 wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="PINT2" description="Pin interrupt 2 wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="PINT3" description="Pin interrupt 3 wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="PINT4" description="Pin interrupt 4 wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="PINT5" description="Pin interrupt 5 wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="PINT6" description="Pin interrupt 6 wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="PINT7" description="Pin interrupt 7 wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x214" size="4" name="STARTERP1" access="Read/Write" description="Start logic 1 interrupt wake-up enable register 1" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="12" size="1" name="RTCINT" description="RTC interrupt wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="WWDT_BODINT" description="Combined WWDT interrupt or Brown Out Detect (BOD) interrupt wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="14" size="5" name="RESERVED" description="Reserved" />
|
|
<BitField start="19" size="1" name="USB_WAKEUP" description="USB need_clock signal wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="GROUP0INT" description="GPIO GROUP0 interrupt wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="21" size="1" name="GROUP1INT" description="GPIO GROUP1 interrupt wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="23" size="1" name="USART1_4" description="Combined USART1 and USART4 interrupt wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
<BitField start="24" size="1" name="USART2_3" description="Combined USART2 and USART3 interrupt wake-up">
|
|
<Enum name="DISABLED" start="0" description="Disabled" />
|
|
<Enum name="ENABLED" start="1" description="Enabled" />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x230" size="4" name="PDSLEEPCFG" access="Read/Write" description="Power-down states in deep-sleep mode" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="3" size="1" name="BOD_PD" description="BOD power-down control for Deep-sleep and Power-down mode">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="RESERVED" description="Reserved." />
|
|
<BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down control for Deep-sleep and Power-down mode">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="7" size="25" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x234" size="4" name="PDAWAKECFG" access="Read/Write" description="Power-down states for wake-up from deep-sleep" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output wake-up configuration">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down wake-up configuration">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="FLASH_PD" description="Flash wake-up configuration">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="BOD_PD" description="BOD wake-up configuration">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="ADC_PD" description="ADC wake-up configuration">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator wake-up configuration">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator wake-up configuration">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="SYSPLL_PD" description="System PLL wake-up configuration">
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="USBPLL_PD" description="USB PLL wake-up configuration">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
|
|
<BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver wake-up configuration">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." />
|
|
<BitField start="12" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="13" size="1" name="TEMPSENSE_PD" description="Temperature sensor wake-up configuration">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="14" size="18" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x238" size="4" name="PDRUNCFG" access="Read/Write" description="Power configuration register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output power-down">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="FLASH_PD" description="Flash power-down">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="BOD_PD" description="BOD power-down">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="ADC_PD" description="ADC power-down">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator power-down. After power-up, add a software delay of approximately 500 us before using.">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="SYSPLL_PD" description="System PLL power-down">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="USBPLL_PD" description="USB PLL power-down">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
|
|
<BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver power-down configuration">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." />
|
|
<BitField start="12" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="13" size="1" name="TEMPSENSE_PD" description="Temperature sensor wake-up configuration">
|
|
<Enum name="POWERED" start="0" description="Powered" />
|
|
<Enum name="POWERED_DOWN" start="1" description="Powered down" />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="RESERVED" description="Reserved. Always write these bits as 0b11." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x3F4" size="4" name="DEVICE_ID" access="ReadOnly" description="Device ID" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="DEVICEID" description="PARTID" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="USART4" start="0x4004C000" description="USART4 ">
|
|
<Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENABLE" description="USART Enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART.">
|
|
<Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." />
|
|
<Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." />
|
|
<Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART.">
|
|
<Enum name="NO_PARITY" start="0x0" description="No parity." />
|
|
<Enum name="RESERVED" start="0x1" description="Reserved." />
|
|
<Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." />
|
|
<Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.">
|
|
<Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
|
|
<Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode.">
|
|
<Enum name="STANDARD" start="0" description="UART uses standard clocking." />
|
|
<Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information.">
|
|
<Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." />
|
|
<Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation.">
|
|
<Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." />
|
|
<Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode.">
|
|
<Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." />
|
|
<Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select.">
|
|
<Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." />
|
|
<Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="LOOP" description="Selects data loopback mode.">
|
|
<Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
|
|
<Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation.">
|
|
<Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." />
|
|
<Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="OESEL" description="Output Enable Select.">
|
|
<Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." />
|
|
<Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." />
|
|
</BitField>
|
|
<BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity.">
|
|
<Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." />
|
|
<Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="RXPOL" description="Receive data polarity.">
|
|
<Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
|
|
<Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
|
|
</BitField>
|
|
<BitField start="23" size="1" name="TXPOL" description="Transmit data polarity.">
|
|
<Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
|
|
<Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
|
|
</BitField>
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="1" size="1" name="TXBRKEN" description="Break Enable.">
|
|
<Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
|
|
<Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." />
|
|
</BitField>
|
|
<BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="1" name="TXDIS" description="Transmit Disable.">
|
|
<Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." />
|
|
<Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.">
|
|
<Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." />
|
|
<Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." />
|
|
<Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." />
|
|
</BitField>
|
|
<BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." />
|
|
</BitField>
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." />
|
|
<BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." />
|
|
<BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register." />
|
|
<BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." />
|
|
<BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." />
|
|
<BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." />
|
|
<BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." />
|
|
<BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." />
|
|
<BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." />
|
|
<BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." />
|
|
<BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
|
|
<BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." />
|
|
<BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." />
|
|
<BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." />
|
|
<BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." />
|
|
<BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." />
|
|
<BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." />
|
|
<BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." />
|
|
<BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." />
|
|
<BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." />
|
|
<BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
|
|
<BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
<BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
|
|
<BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." />
|
|
<BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." />
|
|
<BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." />
|
|
<BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." />
|
|
<BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." />
|
|
<BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." />
|
|
<BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." />
|
|
<BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." />
|
|
<BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SSP1" start="0x40058000" description="SSP1">
|
|
<Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
|
|
<Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
|
|
<Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
|
|
<Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
|
|
<Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
|
|
<Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
|
|
<Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
|
|
<Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
|
|
<Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
|
|
<Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
|
|
<Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
|
|
<Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
|
|
<Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
|
|
<Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="FRF" description="Frame Format.">
|
|
<Enum name="SPI" start="0x0" description="SPI" />
|
|
<Enum name="TI" start="0x1" description="TI" />
|
|
<Enum name="MICROWIRE" start="0x2" description="Microwire" />
|
|
<Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
|
|
<Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." />
|
|
<Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
|
|
<Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
|
|
<Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
|
|
</BitField>
|
|
<BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
|
|
<Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." />
|
|
<Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="SSE" description="SPI Enable.">
|
|
<Enum name="DISABLED" start="0" description="The SPI controller is disabled." />
|
|
<Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
|
|
<Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
|
|
<Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
|
|
<BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
|
|
<BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
|
|
<BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
|
|
<BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
|
|
<BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
|
|
<BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
|
|
<BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
|
|
<BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
|
|
<BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
|
|
<BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
|
|
<BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
|
|
<BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
|
|
<BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="GINT0" start="0x4005C000" description="GPIO group interrupt 0">
|
|
<Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
|
|
<Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
|
|
<Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
|
|
<Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
|
|
<Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
|
|
<Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
|
|
<Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x020+0" size="4" name="PORT_POL[0]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
</Register>
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|
<Register start="+0x020+4" size="4" name="PORT_POL[1]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
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|
<BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
</Register>
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|
<Register start="+0x020+8" size="4" name="PORT_POL[2]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
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|
<BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
</Register>
|
|
<Register start="+0x040+0" size="4" name="PORT_ENA[0]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
</Register>
|
|
<Register start="+0x040+4" size="4" name="PORT_ENA[1]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
</Register>
|
|
<Register start="+0x040+8" size="4" name="PORT_ENA[2]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="GINT1" start="0x40060000" description="GINT1">
|
|
<Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
|
|
<Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
|
|
<Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
|
|
<Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
|
|
<Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
|
|
<Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
|
|
<Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x020+0" size="4" name="PORT_POL[0]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
</Register>
|
|
<Register start="+0x020+4" size="4" name="PORT_POL[1]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
</Register>
|
|
<Register start="+0x020+8" size="4" name="PORT_POL[2]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
|
|
<BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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<BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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<BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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<BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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<BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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<BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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<BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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<BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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|
<BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
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</Register>
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<Register start="+0x040+0" size="4" name="PORT_ENA[0]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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</Register>
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<Register start="+0x040+4" size="4" name="PORT_ENA[1]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF">
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|
<BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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<BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
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|
<BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
</Register>
|
|
<Register start="+0x040+8" size="4" name="PORT_ENA[2]" access="Read/Write" description="GPIO grouped interrupt port enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
<BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="USART1" start="0x4006C000" description="USART1">
|
|
<Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENABLE" description="USART Enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART.">
|
|
<Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." />
|
|
<Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." />
|
|
<Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART.">
|
|
<Enum name="NO_PARITY" start="0x0" description="No parity." />
|
|
<Enum name="RESERVED" start="0x1" description="Reserved." />
|
|
<Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." />
|
|
<Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.">
|
|
<Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
|
|
<Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode.">
|
|
<Enum name="STANDARD" start="0" description="UART uses standard clocking." />
|
|
<Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information.">
|
|
<Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." />
|
|
<Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation.">
|
|
<Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." />
|
|
<Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode.">
|
|
<Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." />
|
|
<Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select.">
|
|
<Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." />
|
|
<Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="LOOP" description="Selects data loopback mode.">
|
|
<Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
|
|
<Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation.">
|
|
<Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." />
|
|
<Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="OESEL" description="Output Enable Select.">
|
|
<Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." />
|
|
<Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." />
|
|
</BitField>
|
|
<BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity.">
|
|
<Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." />
|
|
<Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="RXPOL" description="Receive data polarity.">
|
|
<Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
|
|
<Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
|
|
</BitField>
|
|
<BitField start="23" size="1" name="TXPOL" description="Transmit data polarity.">
|
|
<Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
|
|
<Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
|
|
</BitField>
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="1" size="1" name="TXBRKEN" description="Break Enable.">
|
|
<Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
|
|
<Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." />
|
|
</BitField>
|
|
<BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="1" name="TXDIS" description="Transmit Disable.">
|
|
<Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." />
|
|
<Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.">
|
|
<Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." />
|
|
<Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." />
|
|
<Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." />
|
|
</BitField>
|
|
<BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." />
|
|
</BitField>
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." />
|
|
<BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." />
|
|
<BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register." />
|
|
<BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." />
|
|
<BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." />
|
|
<BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." />
|
|
<BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." />
|
|
<BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." />
|
|
<BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." />
|
|
<BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." />
|
|
<BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
|
|
<BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." />
|
|
<BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." />
|
|
<BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." />
|
|
<BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." />
|
|
<BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." />
|
|
<BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." />
|
|
<BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." />
|
|
<BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." />
|
|
<BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." />
|
|
<BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
|
|
<BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
<BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
|
|
<BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." />
|
|
<BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." />
|
|
<BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." />
|
|
<BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." />
|
|
<BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." />
|
|
<BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." />
|
|
<BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." />
|
|
<BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." />
|
|
<BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="USART2" start="0x40070000" description="USART2">
|
|
<Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENABLE" description="USART Enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART.">
|
|
<Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." />
|
|
<Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." />
|
|
<Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART.">
|
|
<Enum name="NO_PARITY" start="0x0" description="No parity." />
|
|
<Enum name="RESERVED" start="0x1" description="Reserved." />
|
|
<Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." />
|
|
<Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.">
|
|
<Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
|
|
<Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode.">
|
|
<Enum name="STANDARD" start="0" description="UART uses standard clocking." />
|
|
<Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information.">
|
|
<Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." />
|
|
<Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation.">
|
|
<Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." />
|
|
<Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode.">
|
|
<Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." />
|
|
<Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select.">
|
|
<Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." />
|
|
<Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="LOOP" description="Selects data loopback mode.">
|
|
<Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
|
|
<Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation.">
|
|
<Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." />
|
|
<Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="OESEL" description="Output Enable Select.">
|
|
<Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." />
|
|
<Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." />
|
|
</BitField>
|
|
<BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity.">
|
|
<Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." />
|
|
<Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="RXPOL" description="Receive data polarity.">
|
|
<Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
|
|
<Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
|
|
</BitField>
|
|
<BitField start="23" size="1" name="TXPOL" description="Transmit data polarity.">
|
|
<Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
|
|
<Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
|
|
</BitField>
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="1" size="1" name="TXBRKEN" description="Break Enable.">
|
|
<Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
|
|
<Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." />
|
|
</BitField>
|
|
<BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="1" name="TXDIS" description="Transmit Disable.">
|
|
<Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." />
|
|
<Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.">
|
|
<Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." />
|
|
<Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." />
|
|
<Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." />
|
|
</BitField>
|
|
<BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." />
|
|
</BitField>
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." />
|
|
<BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." />
|
|
<BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register." />
|
|
<BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." />
|
|
<BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." />
|
|
<BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." />
|
|
<BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." />
|
|
<BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." />
|
|
<BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." />
|
|
<BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." />
|
|
<BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
|
|
<BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." />
|
|
<BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." />
|
|
<BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." />
|
|
<BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." />
|
|
<BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." />
|
|
<BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." />
|
|
<BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." />
|
|
<BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." />
|
|
<BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." />
|
|
<BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
|
|
<BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
<BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
|
|
<BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." />
|
|
<BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." />
|
|
<BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." />
|
|
<BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." />
|
|
<BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." />
|
|
<BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." />
|
|
<BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." />
|
|
<BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." />
|
|
<BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="USART3" start="0x40074000" description="USART3">
|
|
<Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENABLE" description="USART Enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART.">
|
|
<Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." />
|
|
<Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." />
|
|
<Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART.">
|
|
<Enum name="NO_PARITY" start="0x0" description="No parity." />
|
|
<Enum name="RESERVED" start="0x1" description="Reserved." />
|
|
<Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." />
|
|
<Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.">
|
|
<Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
|
|
<Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode.">
|
|
<Enum name="STANDARD" start="0" description="UART uses standard clocking." />
|
|
<Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." />
|
|
</BitField>
|
|
<BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information.">
|
|
<Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." />
|
|
<Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation.">
|
|
<Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." />
|
|
<Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode.">
|
|
<Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." />
|
|
<Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select.">
|
|
<Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." />
|
|
<Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="LOOP" description="Selects data loopback mode.">
|
|
<Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
|
|
<Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation.">
|
|
<Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." />
|
|
<Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." />
|
|
</BitField>
|
|
<BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." />
|
|
</BitField>
|
|
<BitField start="20" size="1" name="OESEL" description="Output Enable Select.">
|
|
<Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." />
|
|
<Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." />
|
|
</BitField>
|
|
<BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity.">
|
|
<Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." />
|
|
<Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." />
|
|
</BitField>
|
|
<BitField start="22" size="1" name="RXPOL" description="Receive data polarity.">
|
|
<Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
|
|
<Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
|
|
</BitField>
|
|
<BitField start="23" size="1" name="TXPOL" description="Transmit data polarity.">
|
|
<Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
|
|
<Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
|
|
</BitField>
|
|
<BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="1" size="1" name="TXBRKEN" description="Break Enable.">
|
|
<Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
|
|
<Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." />
|
|
</BitField>
|
|
<BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="6" size="1" name="TXDIS" description="Transmit Disable.">
|
|
<Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." />
|
|
<Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.">
|
|
<Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." />
|
|
<Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." />
|
|
</BitField>
|
|
<BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." />
|
|
<Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." />
|
|
</BitField>
|
|
<BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." />
|
|
</BitField>
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." />
|
|
<BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." />
|
|
<BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register." />
|
|
<BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." />
|
|
<BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." />
|
|
<BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." />
|
|
<BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." />
|
|
<BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." />
|
|
<BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." />
|
|
<BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." />
|
|
<BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
|
|
<BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." />
|
|
<BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." />
|
|
<BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." />
|
|
<BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." />
|
|
<BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." />
|
|
<BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." />
|
|
<BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." />
|
|
<BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." />
|
|
<BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." />
|
|
<BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
|
|
<BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
<BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
|
|
<BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." />
|
|
<BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." />
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." />
|
|
<BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." />
|
|
<BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." />
|
|
<BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." />
|
|
<BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." />
|
|
<BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." />
|
|
<BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." />
|
|
<BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." />
|
|
<BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." />
|
|
<BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." />
|
|
<BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="USB" start="0x40080000" description="USB device controller">
|
|
<Register start="+0x000" size="4" name="DEVCMDSTAT" access="Read/Write" description="USB Device Command/Status register" reset_value="0x00000800" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="DEV_ADDR" description="USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request." />
|
|
<BitField start="7" size="1" name="DEV_EN" description="USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR." />
|
|
<BitField start="8" size="1" name="SETUP" description="SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW." />
|
|
<BitField start="9" size="1" name="PLL_ON" description="USB Clock/PLL control.">
|
|
<Enum name="USB_NEEDCLK_FUNCTION" start="0" description="USB_NeedClk functional" />
|
|
<Enum name="USB_NEEDCLK_ALWAYS_1" start="1" description="USB_NeedClk always 1. Clock will not be stopped in case of suspend." />
|
|
</BitField>
|
|
<BitField start="10" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="11" size="1" name="LPM_SUP" description="LPM Support.">
|
|
<Enum name="LPM_NOT_SUPPORTED" start="0" description="LPM not supported." />
|
|
<Enum name="LPM_SUPPORTED" start="1" description="LPM supported." />
|
|
</BitField>
|
|
<BitField start="12" size="1" name="INTONNAK_AO" description="Interrupt on NAK for interrupt and bulk OUT EP">
|
|
<Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" />
|
|
<Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
|
|
</BitField>
|
|
<BitField start="13" size="1" name="INTONNAK_AI" description="Interrupt on NAK for interrupt and bulk IN EP">
|
|
<Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" />
|
|
<Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="INTONNAK_CO" description="Interrupt on NAK for control OUT EP">
|
|
<Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" />
|
|
<Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="INTONNAK_CI" description="Interrupt on NAK for control IN EP">
|
|
<Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" />
|
|
<Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
|
|
</BitField>
|
|
<BitField start="16" size="1" name="DCON" description="Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one." />
|
|
<BitField start="17" size="1" name="DSUS" description="Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect." />
|
|
<BitField start="18" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="19" size="1" name="LPM_SUS" description="Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one." />
|
|
<BitField start="20" size="1" name="LPM_REWP" description="LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction." />
|
|
<BitField start="21" size="3" name="RESERVED" description="Reserved." />
|
|
<BitField start="24" size="1" name="DCON_C" description="Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it." />
|
|
<BitField start="25" size="1" name="DSUS_C" description="Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it." />
|
|
<BitField start="26" size="1" name="DRES_C" description="Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it." />
|
|
<BitField start="27" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="28" size="1" name="VBUSDEBOUNCED" description="This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect." />
|
|
<BitField start="29" size="3" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="INFO" access="Read/Write" description="USB Info register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="11" name="FRAME_NR" description="Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device." />
|
|
<BitField start="11" size="4" name="ERR_CODE" description="The error code which last occurred:">
|
|
<Enum name="NO_ERROR" start="0x0" description="No error" />
|
|
<Enum name="PID_ENCODING_ERROR" start="0x1" description="PID encoding error" />
|
|
<Enum name="PID_UNKNOWN" start="0x2" description="PID unknown" />
|
|
<Enum name="PACKET_UNEXPECTED" start="0x3" description="Packet unexpected" />
|
|
<Enum name="TOKEN_CRC_ERROR" start="0x4" description="Token CRC error" />
|
|
<Enum name="DATA_CRC_ERROR" start="0x5" description="Data CRC error" />
|
|
<Enum name="TIME_OUT" start="0x6" description="Time out" />
|
|
<Enum name="BABBLE" start="0x7" description="Babble" />
|
|
<Enum name="TRUNCATED_EOP" start="0x8" description="Truncated EOP" />
|
|
<Enum name="SENT_RECEIVED_NAK" start="0x9" description="Sent/Received NAK" />
|
|
<Enum name="SENT_STALL" start="0xA" description="Sent Stall" />
|
|
<Enum name="OVERRUN" start="0xB" description="Overrun" />
|
|
<Enum name="SENT_EMPTY_PACKET" start="0xC" description="Sent empty packet" />
|
|
<Enum name="BITSTUFF_ERROR" start="0xD" description="Bitstuff error" />
|
|
<Enum name="SYNC_ERROR" start="0xE" description="Sync error" />
|
|
<Enum name="WRONG_DATA_TOGGLE" start="0xF" description="Wrong data toggle" />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="EPLISTSTART" access="Read/Write" description="USB EP Command/Status List start address" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="RESERVED" description="Reserved" />
|
|
<BitField start="8" size="24" name="EP_LIST" description="Start address of the USB EP Command/Status List." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="DATABUFSTART" access="Read/Write" description="USB Data buffer start address" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="22" name="RESERVED" description="Reserved" />
|
|
<BitField start="22" size="10" name="DA_BUF" description="Start address of the buffer pointer page where all endpoint data buffers are located." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="LPM" access="Read/Write" description="Link Power Management register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="HIRD_HW" description="Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token" />
|
|
<BitField start="4" size="4" name="HIRD_SW" description="Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume." />
|
|
<BitField start="8" size="1" name="DATA_PENDING" description="As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1." />
|
|
<BitField start="9" size="23" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="EPSKIP" access="Read/Write" description="USB Endpoint skip" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="30" name="SKIP" description="Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit." />
|
|
<BitField start="30" size="2" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="EPINUSE" access="Read/Write" description="USB Endpoint Buffer in use" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." />
|
|
<BitField start="2" size="8" name="BUF" description="Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="EPBUFCFG" access="Read/Write" description="USB Endpoint Buffer Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." />
|
|
<BitField start="2" size="8" name="BUF_SB" description="Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="INTSTAT" access="Read/Write" description="USB interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="EP0OUT" description="Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="1" size="1" name="EP0IN" description="Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="2" size="1" name="EP1OUT" description="Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="3" size="1" name="EP1IN" description="Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="4" size="1" name="EP2OUT" description="Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="5" size="1" name="EP2IN" description="Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="6" size="1" name="EP3OUT" description="Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="7" size="1" name="EP3IN" description="Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="8" size="1" name="EP4OUT" description="Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="9" size="1" name="EP4IN" description="Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it." />
|
|
<BitField start="10" size="20" name="RESERVED" description="Reserved" />
|
|
<BitField start="30" size="1" name="FRAME_INT" description="Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it." />
|
|
<BitField start="31" size="1" name="DEV_INT" description="Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="INTEN" access="Read/Write" description="USB interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="EP_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
|
|
<BitField start="10" size="20" name="RESERVED" description="Reserved" />
|
|
<BitField start="30" size="1" name="FRAME_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
|
|
<BitField start="31" size="1" name="DEV_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="INTSETSTAT" access="Read/Write" description="USB set interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="EP_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned." />
|
|
<BitField start="10" size="20" name="RESERVED" description="Reserved" />
|
|
<BitField start="30" size="1" name="FRAME_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned." />
|
|
<BitField start="31" size="1" name="DEV_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="INTROUTING" access="Read/Write" description="USB interrupt routing register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="ROUTE_INT9_0" description="This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
|
|
<BitField start="10" size="20" name="RESERVED" description="Reserved" />
|
|
<BitField start="30" size="1" name="ROUTE_INT30" description="This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
|
|
<BitField start="31" size="1" name="ROUTE_INT31" description="This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
|
|
</Register>
|
|
<Register start="+0x034" size="4" name="EPTOGGLE" access="ReadOnly" description="USB Endpoint toggle register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="TOGGLE" description="Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint." />
|
|
<BitField start="10" size="22" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="CRC" start="0x50000000" description="Cyclic Redundancy Check (CRC) engine">
|
|
<Register start="+0x00" size="4" name="MODE" access="Read/Write" description="CRC mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="CRC_POLY" description="CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial" />
|
|
<BitField start="2" size="1" name="BIT_RVS_WR" description="Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte)" />
|
|
<BitField start="3" size="1" name="CMPL_WR" description="Data complement: 1= 1's complement for CRC_WR_DATA 0= No 1's complement for CRC_WR_DATA" />
|
|
<BitField start="4" size="1" name="BIT_RVS_SUM" description="CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM" />
|
|
<BitField start="5" size="1" name="CMPL_SUM" description="CRC sum complement: 1= 1's complement for CRC_SUM 0=No 1's complement for CRC_SUM" />
|
|
<BitField start="6" size="26" name="Reserved" description="Always 0 when read" />
|
|
</Register>
|
|
<Register start="+0x04" size="4" name="SEED" access="Read/Write" description="CRC seed register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CRC_SEED" description="A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses." />
|
|
</Register>
|
|
<Register start="+0x08" size="4" name="SUM" access="ReadOnly" description="CRC checksum register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="32" name="CRC_SUM" description="The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes." />
|
|
</Register>
|
|
<Register start="+0x08" size="4" name="WR_DATA" access="WriteOnly" description="CRC data register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="CRC_WR_DATA" description="Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="DMA" start="0x50004000" description="DMA controller">
|
|
<Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="DMA control." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENABLE" description="DMA controller master enable.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. The DMA controller is enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="1" size="1" name="ACTIVEINT" description="Summarizes whether any enabled interrupts are pending.">
|
|
<Enum name="NOT_PENDING" start="0" description="Not pending. No enabled interrupts are pending." />
|
|
<Enum name="PENDING" start="1" description="Pending. At least one enabled interrupt is pending." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="ACTIVEERRINT" description="Summarizes whether any error interrupts are pending.">
|
|
<Enum name="NOT_PENDING" start="0" description="Not pending. No error interrupts are pending." />
|
|
<Enum name="PENDING" start="1" description="Pending. At least one error interrupt is pending." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="SRAMBASE" access="Read/Write" description="SRAM address of the channel configuration table." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="10" size="22" name="OFFSET" description="Address of the beginning of the DMA descriptor table. The table must begin on a 1 kB boundary. Boundary needed for 18 channel DMA configuration: 512 bytes (bottom 9 bits = 0)" />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="ENABLESET0" access="Read/Write" description="Channel Enable read and Set for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="ENA" description="Enable for DMA channels 15:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="ENABLECLR0" access="WriteOnly" description="Channel Enable Clear for all DMA channels." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="16" name="CLR" description="Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n." />
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="ACTIVE0" access="ReadOnly" description="Channel Active status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="ACT" description="Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x038" size="4" name="BUSY0" access="ReadOnly" description="Channel Busy status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="BSY" description="Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x040" size="4" name="ERRINT0" access="Read/Write" description="Error Interrupt status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="ERR" description="Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x048" size="4" name="INTENSET0" access="Read/Write" description="Interrupt Enable read and Set for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="INTEN" description="Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="INTENCLR0" access="WriteOnly" description="Interrupt Enable Clear for all DMA channels." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="16" name="CLR" description="Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x058" size="4" name="INTA0" access="Read/Write" description="Interrupt A status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="IA" description="Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x060" size="4" name="INTB0" access="Read/Write" description="Interrupt B status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="IB" description="Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x068" size="4" name="SETVALID0" access="WriteOnly" description="Set ValidPending control bits for all DMA channels." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="16" name="SV" description="SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x070" size="4" name="SETTRIG0" access="WriteOnly" description="Set Trigger control bits for all DMA channels." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="16" name="TRIG" description="Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x078" size="4" name="ABORT0" access="WriteOnly" description="Channel Abort control for all DMA channels." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="16" name="AORTCTRL" description="Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n." />
|
|
<BitField start="16" size="16" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x400+0" size="4" name="CFG0" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+16" size="4" name="CFG1" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+32" size="4" name="CFG2" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+48" size="4" name="CFG3" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+64" size="4" name="CFG4" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+80" size="4" name="CFG5" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+96" size="4" name="CFG6" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+112" size="4" name="CFG7" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+128" size="4" name="CFG8" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+144" size="4" name="CFG9" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+160" size="4" name="CFG10" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+176" size="4" name="CFG11" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+192" size="4" name="CFG12" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+208" size="4" name="CFG13" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+224" size="4" name="CFG14" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x400+240" size="4" name="CFG15" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
|
|
<Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
|
|
<Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
|
|
<Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
|
|
<Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
|
|
</BitField>
|
|
<BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
|
|
<Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
|
|
<Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
|
|
<BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
|
|
</BitField>
|
|
<BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
|
|
<BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+0" size="4" name="CTLSTAT0" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+16" size="4" name="CTLSTAT1" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+32" size="4" name="CTLSTAT2" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+48" size="4" name="CTLSTAT3" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+64" size="4" name="CTLSTAT4" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+80" size="4" name="CTLSTAT5" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+96" size="4" name="CTLSTAT6" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+112" size="4" name="CTLSTAT7" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+128" size="4" name="CTLSTAT8" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+144" size="4" name="CTLSTAT9" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+160" size="4" name="CTLSTAT10" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+176" size="4" name="CTLSTAT11" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+192" size="4" name="CTLSTAT12" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+208" size="4" name="CTLSTAT13" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+224" size="4" name="CTLSTAT14" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x404+240" size="4" name="CTLSTAT15" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
|
|
<Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
|
|
<Enum name="VALID_PENDING" start="1" description="Valid pending." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
|
|
<Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
|
|
<Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
|
|
</BitField>
|
|
<BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+0" size="4" name="XFERCFG0" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+16" size="4" name="XFERCFG1" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+32" size="4" name="XFERCFG2" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+48" size="4" name="XFERCFG3" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+64" size="4" name="XFERCFG4" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+80" size="4" name="XFERCFG5" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+96" size="4" name="XFERCFG6" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+112" size="4" name="XFERCFG7" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+128" size="4" name="XFERCFG8" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+144" size="4" name="XFERCFG9" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+160" size="4" name="XFERCFG10" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+176" size="4" name="XFERCFG11" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+192" size="4" name="XFERCFG12" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+208" size="4" name="XFERCFG13" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+224" size="4" name="XFERCFG14" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
<Register start="+0x408+240" size="4" name="XFERCFG15" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
|
|
<Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
|
|
<Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
|
|
<Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
|
|
<Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
|
|
<Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
|
|
</BitField>
|
|
<BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
|
|
<Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
|
|
<Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
|
|
<Enum name="NO_EFFECT" start="0" description="No effect." />
|
|
<Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
|
|
<Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
|
|
<Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
|
|
<Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
|
|
<Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
|
|
</BitField>
|
|
<BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
<BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
|
|
<Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
|
|
<Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
|
|
<Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
|
|
<Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
|
|
</BitField>
|
|
<BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
|
|
<BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SCT0" start="0x5000C000" description="State Configurable Timers (SCTimer/PWM)">
|
|
<Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="UNIFY" description="SCT operation">
|
|
<Enum name="THE_SCT_OPERATES_AS" start="0" description="The SCT operates as two 16-bit counters named L and H." />
|
|
<Enum name="THE_SCT_OPERATES_AS" start="1" description="The SCT operates as a unified 32-bit counter." />
|
|
</BitField>
|
|
<BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
|
|
<Enum name="THE_BUS_CLOCK_CLOCKS" start="0x0" description="The bus clock clocks the SCT and prescalers." />
|
|
<Enum name="THE_SCT_CLOCK_IS_THE" start="0x1" description="The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode." />
|
|
<Enum name="THE_INPUT_SELECTED_B" start="0x2" description="The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode." />
|
|
<Enum name="PRESCALED_SCT_INPUT" start="0x3" description="Prescaled SCT input. The SCT and prescalers are clocked by the input edge selected by the CKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the) input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and can the same or faster than the system clock." />
|
|
</BitField>
|
|
<BitField start="3" size="4" name="CKSEL" description="SCT clock select">
|
|
<Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
|
|
<Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
|
|
<Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
|
|
<Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
|
|
<Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
|
|
<Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
|
|
<Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
|
|
<Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." />
|
|
<BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." />
|
|
<BitField start="9" size="8" name="INSYNC" description="Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used." />
|
|
<BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." />
|
|
<BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." />
|
|
<BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." />
|
|
<BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
|
|
<BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
|
|
<BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
|
|
<Enum name="THE_COUNTER_COUNTS_U" start="0" description="The counter counts up to its limit condition, then is cleared to zero." />
|
|
<Enum name="THE_COUNTER_COUNTS_U" start="1" description="The counter counts up to its limit, then counts down to a limit condition or to 0." />
|
|
</BitField>
|
|
<BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." />
|
|
<BitField start="13" size="3" name="RESERVED" description="Reserved" />
|
|
<BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." />
|
|
<BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." />
|
|
<BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
|
|
<BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
|
|
<BitField start="20" size="1" name="BIDIR_H" description="Direction select">
|
|
<Enum name="THE_H_COUNTER_COUNTS" start="0" description="The H counter counts up to its limit condition, then is cleared to zero." />
|
|
<Enum name="THE_H_COUNTER_COUNTS" start="1" description="The H counter counts up to its limit, then counts down to a limit condition or to 0." />
|
|
</BitField>
|
|
<BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." />
|
|
<BitField start="29" size="3" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
|
|
<BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
|
|
</Register>
|
|
<Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="STATE_L" description="State variable." />
|
|
<BitField start="5" size="11" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="5" name="STATE_H" description="State variable." />
|
|
<BitField start="21" size="11" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
|
|
<BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
|
|
<BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
|
|
<BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
|
|
<BitField start="4" size="12" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
|
|
<BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
|
|
<BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
|
|
<BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
|
|
<BitField start="20" size="12" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
|
|
<BitField start="5" size="11" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="5" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 20). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
|
|
<BitField start="21" size="11" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
|
|
<Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
|
|
<Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
|
|
<Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
|
|
<Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
|
|
<Enum name="NO_CHANGE" start="0x0" description="No change." />
|
|
<Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
|
|
<Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
|
|
<Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
|
|
<Enum name="NO_CHANGE" start="0x0" description="No change." />
|
|
<Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
|
|
<Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
|
|
<Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
|
|
<Enum name="NO_CHANGE" start="0x0" description="No change." />
|
|
<Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
|
|
<Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
|
|
<Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
|
|
<Enum name="NO_CHANGE" start="0x0" description="No change." />
|
|
<Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
|
|
<Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
|
|
<Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="DEV_0" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="24" name="RESERVED" description="Reserved" />
|
|
<BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers." />
|
|
<BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
|
|
</Register>
|
|
<Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="DEV_1" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="24" name="RESERVED" description="Reserved" />
|
|
<BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers." />
|
|
<BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
|
|
</Register>
|
|
<Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="IEN" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="FLAG" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="NCEN" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="NCFLAG" description="Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
|
|
<BitField start="4" size="26" name="RESERVED" description="Reserved." />
|
|
<BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful." />
|
|
<BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted." />
|
|
</Register>
|
|
<Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SCT1" start="0x5000E000" description="SCT1">
|
|
<Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="UNIFY" description="SCT operation">
|
|
<Enum name="THE_SCT_OPERATES_AS" start="0" description="The SCT operates as two 16-bit counters named L and H." />
|
|
<Enum name="THE_SCT_OPERATES_AS" start="1" description="The SCT operates as a unified 32-bit counter." />
|
|
</BitField>
|
|
<BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
|
|
<Enum name="THE_BUS_CLOCK_CLOCKS" start="0x0" description="The bus clock clocks the SCT and prescalers." />
|
|
<Enum name="THE_SCT_CLOCK_IS_THE" start="0x1" description="The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode." />
|
|
<Enum name="THE_INPUT_SELECTED_B" start="0x2" description="The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode." />
|
|
<Enum name="PRESCALED_SCT_INPUT" start="0x3" description="Prescaled SCT input. The SCT and prescalers are clocked by the input edge selected by the CKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the) input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and can the same or faster than the system clock." />
|
|
</BitField>
|
|
<BitField start="3" size="4" name="CKSEL" description="SCT clock select">
|
|
<Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
|
|
<Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
|
|
<Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
|
|
<Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
|
|
<Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
|
|
<Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
|
|
<Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
|
|
<Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
|
|
</BitField>
|
|
<BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." />
|
|
<BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." />
|
|
<BitField start="9" size="8" name="INSYNC" description="Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used." />
|
|
<BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." />
|
|
<BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." />
|
|
<BitField start="19" size="13" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." />
|
|
<BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." />
|
|
<BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
|
|
<BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
|
|
<BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
|
|
<Enum name="THE_COUNTER_COUNTS_U" start="0" description="The counter counts up to its limit condition, then is cleared to zero." />
|
|
<Enum name="THE_COUNTER_COUNTS_U" start="1" description="The counter counts up to its limit, then counts down to a limit condition or to 0." />
|
|
</BitField>
|
|
<BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." />
|
|
<BitField start="13" size="3" name="RESERVED" description="Reserved" />
|
|
<BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." />
|
|
<BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." />
|
|
<BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
|
|
<BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
|
|
<BitField start="20" size="1" name="BIDIR_H" description="Direction select">
|
|
<Enum name="THE_H_COUNTER_COUNTS" start="0" description="The H counter counts up to its limit condition, then is cleared to zero." />
|
|
<Enum name="THE_H_COUNTER_COUNTS" start="1" description="The H counter counts up to its limit, then counts down to a limit condition or to 0." />
|
|
</BitField>
|
|
<BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." />
|
|
<BitField start="29" size="3" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
|
|
<BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
|
|
</Register>
|
|
<Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="STATE_L" description="State variable." />
|
|
<BitField start="5" size="11" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="5" name="STATE_H" description="State variable." />
|
|
<BitField start="21" size="11" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
|
|
<BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
|
|
<BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
|
|
<BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
|
|
<BitField start="4" size="12" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
|
|
<BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
|
|
<BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
|
|
<BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
|
|
<BitField start="20" size="12" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="5" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
|
|
<BitField start="5" size="11" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="5" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 20). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
|
|
<BitField start="21" size="11" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
|
|
<Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
|
|
<Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
|
|
<Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
|
|
<Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
|
|
<Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
|
|
<Enum name="NO_CHANGE" start="0x0" description="No change." />
|
|
<Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
|
|
<Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
|
|
<Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
|
|
</BitField>
|
|
<BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
|
|
<Enum name="NO_CHANGE" start="0x0" description="No change." />
|
|
<Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
|
|
<Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
|
|
<Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
|
|
</BitField>
|
|
<BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
|
|
<Enum name="NO_CHANGE" start="0x0" description="No change." />
|
|
<Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
|
|
<Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
|
|
<Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
|
|
</BitField>
|
|
<BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
|
|
<Enum name="NO_CHANGE" start="0x0" description="No change." />
|
|
<Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
|
|
<Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
|
|
<Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
|
|
</BitField>
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="DEV_0" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="24" name="RESERVED" description="Reserved" />
|
|
<BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers." />
|
|
<BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
|
|
</Register>
|
|
<Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="DEV_1" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="24" name="RESERVED" description="Reserved" />
|
|
<BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers." />
|
|
<BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
|
|
</Register>
|
|
<Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="IEN" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="FLAG" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="NCEN" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
|
|
<BitField start="4" size="28" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="NCFLAG" description="Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
|
|
<BitField start="4" size="26" name="RESERVED" description="Reserved." />
|
|
<BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful." />
|
|
<BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted." />
|
|
</Register>
|
|
<Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
<BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
|
|
</Register>
|
|
<Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
|
|
<BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
|
|
</Register>
|
|
<Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
<BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
|
|
</Register>
|
|
<Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
|
|
<BitField start="6" size="10" name="RESERVED" description="Reserved." />
|
|
<BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
|
|
<BitField start="22" size="10" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." />
|
|
<BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
|
|
<Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
|
|
<Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
|
|
</BitField>
|
|
<BitField start="5" size="1" name="OUTSEL" description="Input/output select">
|
|
<Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
|
|
<Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
|
|
</BitField>
|
|
<BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." />
|
|
<BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .">
|
|
<Enum name="LOW" start="0x0" description="LOW" />
|
|
<Enum name="RISE" start="0x1" description="Rise" />
|
|
<Enum name="FALL" start="0x2" description="Fall" />
|
|
<Enum name="HIGH" start="0x3" description="HIGH" />
|
|
</BitField>
|
|
<BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
|
|
<Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
|
|
<Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
|
|
<Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
|
|
<Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
|
|
</BitField>
|
|
<BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.">
|
|
<Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
|
|
<Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
|
|
</BitField>
|
|
<BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." />
|
|
<BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." />
|
|
<BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
|
|
<Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
|
|
<Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
|
|
<Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
|
|
</BitField>
|
|
<BitField start="23" size="9" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
<Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
|
|
<BitField start="6" size="26" name="RESERVED" description="Reserved" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="GPIO_PORT" start="0xA0000000" description="General Purpose I/O (GPIO) ">
|
|
<Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
|
|
</Register>
|
|
<Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
|
|
</Register>
|
|
<Register start="+0x2000+0" size="4" name="DIR[0]" access="Read/Write" description="Port Direction registers " reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
</Register>
|
|
<Register start="+0x2000+4" size="4" name="DIR[1]" access="Read/Write" description="Port Direction registers " reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
|
|
<BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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|
<BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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</Register>
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<Register start="+0x2000+8" size="4" name="DIR[2]" access="Read/Write" description="Port Direction registers " reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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|
<BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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|
<BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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<BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
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</Register>
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<Register start="+0x2080+0" size="4" name="MASK[0]" access="Read/Write" description="Port Mask register " reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
</Register>
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<Register start="+0x2080+4" size="4" name="MASK[1]" access="Read/Write" description="Port Mask register " reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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|
<BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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</Register>
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<Register start="+0x2080+8" size="4" name="MASK[2]" access="Read/Write" description="Port Mask register " reset_value="0" reset_mask="0xFFFFFFFF">
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<BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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<BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
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</Register>
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<Register start="+0x2100+0" size="4" name="PIN[0]" access="Read/Write" description="Port pin register " reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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</Register>
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<Register start="+0x2100+4" size="4" name="PIN[1]" access="Read/Write" description="Port pin register " reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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</Register>
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<Register start="+0x2100+8" size="4" name="PIN[2]" access="Read/Write" description="Port pin register " reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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<BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
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</Register>
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<Register start="+0x2180+0" size="4" name="MPIN[0]" access="Read/Write" description="Masked port register " reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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</Register>
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<Register start="+0x2180+4" size="4" name="MPIN[1]" access="Read/Write" description="Masked port register " reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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</Register>
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<Register start="+0x2180+8" size="4" name="MPIN[2]" access="Read/Write" description="Masked port register " reset_value="0" reset_mask="0x00000000">
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<BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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<BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
|
|
<BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
<BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
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|
</Register>
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|
<Register start="+0x2200+0" size="4" name="SET[0]" access="Read/Write" description="Write: Set port register Read: port output bits " reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SETP00" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="1" size="1" name="SETP01" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="2" size="1" name="SETP02" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="3" size="1" name="SETP03" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="4" size="1" name="SETP04" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="5" size="1" name="SETP05" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="6" size="1" name="SETP06" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="7" size="1" name="SETP07" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="8" size="1" name="SETP08" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="9" size="1" name="SETP09" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="10" size="1" name="SETP010" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="11" size="1" name="SETP011" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="12" size="1" name="SETP012" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="13" size="1" name="SETP013" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="14" size="1" name="SETP014" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="15" size="1" name="SETP015" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="16" size="1" name="SETP016" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="17" size="1" name="SETP017" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="18" size="1" name="SETP018" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="19" size="1" name="SETP019" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="20" size="1" name="SETP020" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="21" size="1" name="SETP021" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="22" size="1" name="SETP022" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="23" size="1" name="SETP023" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="24" size="1" name="SETP024" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="25" size="1" name="SETP025" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="26" size="1" name="SETP026" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="27" size="1" name="SETP027" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="28" size="1" name="SETP028" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="29" size="1" name="SETP029" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="30" size="1" name="SETP030" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="31" size="1" name="SETP031" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
</Register>
|
|
<Register start="+0x2200+4" size="4" name="SET[1]" access="Read/Write" description="Write: Set port register Read: port output bits " reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SETP00" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="1" size="1" name="SETP01" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="2" size="1" name="SETP02" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="3" size="1" name="SETP03" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="4" size="1" name="SETP04" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="5" size="1" name="SETP05" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="6" size="1" name="SETP06" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="7" size="1" name="SETP07" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="8" size="1" name="SETP08" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="9" size="1" name="SETP09" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="10" size="1" name="SETP010" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="11" size="1" name="SETP011" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="12" size="1" name="SETP012" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="13" size="1" name="SETP013" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="14" size="1" name="SETP014" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="15" size="1" name="SETP015" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="16" size="1" name="SETP016" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="17" size="1" name="SETP017" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="18" size="1" name="SETP018" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="19" size="1" name="SETP019" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="20" size="1" name="SETP020" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="21" size="1" name="SETP021" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="22" size="1" name="SETP022" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="23" size="1" name="SETP023" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="24" size="1" name="SETP024" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="25" size="1" name="SETP025" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="26" size="1" name="SETP026" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="27" size="1" name="SETP027" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="28" size="1" name="SETP028" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="29" size="1" name="SETP029" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="30" size="1" name="SETP030" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="31" size="1" name="SETP031" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
</Register>
|
|
<Register start="+0x2200+8" size="4" name="SET[2]" access="Read/Write" description="Write: Set port register Read: port output bits " reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SETP00" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="1" size="1" name="SETP01" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="2" size="1" name="SETP02" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="3" size="1" name="SETP03" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="4" size="1" name="SETP04" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="5" size="1" name="SETP05" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="6" size="1" name="SETP06" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="7" size="1" name="SETP07" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="8" size="1" name="SETP08" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="9" size="1" name="SETP09" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="10" size="1" name="SETP010" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="11" size="1" name="SETP011" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="12" size="1" name="SETP012" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="13" size="1" name="SETP013" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="14" size="1" name="SETP014" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="15" size="1" name="SETP015" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="16" size="1" name="SETP016" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="17" size="1" name="SETP017" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="18" size="1" name="SETP018" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="19" size="1" name="SETP019" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="20" size="1" name="SETP020" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="21" size="1" name="SETP021" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="22" size="1" name="SETP022" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="23" size="1" name="SETP023" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="24" size="1" name="SETP024" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="25" size="1" name="SETP025" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="26" size="1" name="SETP026" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="27" size="1" name="SETP027" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="28" size="1" name="SETP028" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="29" size="1" name="SETP029" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="30" size="1" name="SETP030" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
<BitField start="31" size="1" name="SETP031" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
|
|
</Register>
|
|
<Register start="+0x2280+0" size="4" name="CLR[0]" access="WriteOnly" description="Clear port" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
</Register>
|
|
<Register start="+0x2280+4" size="4" name="CLR[1]" access="WriteOnly" description="Clear port" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
</Register>
|
|
<Register start="+0x2280+8" size="4" name="CLR[2]" access="WriteOnly" description="Clear port" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
<BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
|
|
</Register>
|
|
<Register start="+0x2300+0" size="4" name="NOT[0]" access="WriteOnly" description="Toggle port " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="NOTP00" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="1" size="1" name="NOTP01" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="2" size="1" name="NOTP02" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="3" size="1" name="NOTP03" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="4" size="1" name="NOTP04" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="5" size="1" name="NOTP05" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="6" size="1" name="NOTP06" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="7" size="1" name="NOTP07" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="8" size="1" name="NOTP08" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="9" size="1" name="NOTP09" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="10" size="1" name="NOTP010" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="11" size="1" name="NOTP011" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="12" size="1" name="NOTP012" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="13" size="1" name="NOTP013" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="14" size="1" name="NOTP014" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="15" size="1" name="NOTP015" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="16" size="1" name="NOTP016" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="17" size="1" name="NOTP017" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="18" size="1" name="NOTP018" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="19" size="1" name="NOTP019" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="20" size="1" name="NOTP020" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="21" size="1" name="NOTP021" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="22" size="1" name="NOTP022" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="23" size="1" name="NOTP023" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="24" size="1" name="NOTP024" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="25" size="1" name="NOTP025" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="26" size="1" name="NOTP026" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="27" size="1" name="NOTP027" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="28" size="1" name="NOTP028" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="29" size="1" name="NOTP029" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="30" size="1" name="NOTP030" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="31" size="1" name="NOTP031" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
</Register>
|
|
<Register start="+0x2300+4" size="4" name="NOT[1]" access="WriteOnly" description="Toggle port " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="NOTP00" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="1" size="1" name="NOTP01" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="2" size="1" name="NOTP02" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="3" size="1" name="NOTP03" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="4" size="1" name="NOTP04" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="5" size="1" name="NOTP05" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="6" size="1" name="NOTP06" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="7" size="1" name="NOTP07" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="8" size="1" name="NOTP08" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="9" size="1" name="NOTP09" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="10" size="1" name="NOTP010" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="11" size="1" name="NOTP011" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="12" size="1" name="NOTP012" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="13" size="1" name="NOTP013" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="14" size="1" name="NOTP014" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="15" size="1" name="NOTP015" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="16" size="1" name="NOTP016" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="17" size="1" name="NOTP017" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="18" size="1" name="NOTP018" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="19" size="1" name="NOTP019" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="20" size="1" name="NOTP020" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="21" size="1" name="NOTP021" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="22" size="1" name="NOTP022" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="23" size="1" name="NOTP023" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="24" size="1" name="NOTP024" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="25" size="1" name="NOTP025" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="26" size="1" name="NOTP026" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="27" size="1" name="NOTP027" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="28" size="1" name="NOTP028" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="29" size="1" name="NOTP029" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="30" size="1" name="NOTP030" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="31" size="1" name="NOTP031" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
</Register>
|
|
<Register start="+0x2300+8" size="4" name="NOT[2]" access="WriteOnly" description="Toggle port " reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="NOTP00" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="1" size="1" name="NOTP01" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="2" size="1" name="NOTP02" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="3" size="1" name="NOTP03" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="4" size="1" name="NOTP04" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="5" size="1" name="NOTP05" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="6" size="1" name="NOTP06" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="7" size="1" name="NOTP07" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="8" size="1" name="NOTP08" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="9" size="1" name="NOTP09" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="10" size="1" name="NOTP010" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="11" size="1" name="NOTP011" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="12" size="1" name="NOTP012" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="13" size="1" name="NOTP013" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="14" size="1" name="NOTP014" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="15" size="1" name="NOTP015" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="16" size="1" name="NOTP016" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="17" size="1" name="NOTP017" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="18" size="1" name="NOTP018" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="19" size="1" name="NOTP019" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="20" size="1" name="NOTP020" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="21" size="1" name="NOTP021" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="22" size="1" name="NOTP022" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="23" size="1" name="NOTP023" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="24" size="1" name="NOTP024" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="25" size="1" name="NOTP025" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="26" size="1" name="NOTP026" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="27" size="1" name="NOTP027" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="28" size="1" name="NOTP028" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="29" size="1" name="NOTP029" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="30" size="1" name="NOTP030" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
<BitField start="31" size="1" name="NOTP031" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="PINT" start="0xA0004000" description=" Pin interrupt
and pattern match (PINT) ">
|
|
<Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
|
|
<BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
|
|
<BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
|
|
<BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
|
|
<BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
|
|
<BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
|
|
<BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
|
|
<BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin interrupt level or rising edge interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Pin interrupt level or rising edge interrupt set register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Pin interrupt level (rising edge interrupt) clear register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
|
|
<BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
|
|
<BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
|
|
<BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
|
|
<BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
|
|
<BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
|
|
<BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
|
|
<BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin interrupt active level or falling edge interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
|
|
<BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
|
|
<BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
|
|
<BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
|
|
<BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
|
|
<BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
|
|
<BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
|
|
<BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Pin interrupt active level or falling edge interrupt set register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
|
|
<BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
|
|
<BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
|
|
<BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
|
|
<BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
|
|
<BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
|
|
<BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
|
|
<BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Pin interrupt active level or falling edge interrupt clear register" reset_value="0" reset_mask="0x00000000">
|
|
<BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
|
|
<BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
|
|
<BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
|
|
<BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
|
|
<BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
|
|
<BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
|
|
<BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
|
|
<BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin interrupt rising edge register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
|
|
<BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
|
|
<BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
|
|
<BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
|
|
<BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
|
|
<BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
|
|
<BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
|
|
<BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin interrupt falling edge register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
|
|
<BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
|
|
<BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
|
|
<BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
|
|
<BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
|
|
<BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
|
|
<BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
|
|
<BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
|
|
<BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
|
|
<BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
|
|
<BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
|
|
<BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
|
|
<BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
|
|
<BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
|
|
<BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
|
|
<BitField start="8" size="24" name="RESERVED" description="Reserved." />
|
|
</Register>
|
|
<Register start="+0x028" size="4" name="PMCTRL" access="Read/Write" description="Pattern match interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="1" name="SEL_PMATCH" description="Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.">
|
|
<Enum name="PIN_INTERRUPT_INTER" start="0" description="Pin interrupt. Interrupts are driven in response to the standard pin interrupt function" />
|
|
<Enum name="PATTERN_MATCH_INTER" start="1" description="Pattern match. Interrupts are driven in response to pattern matches." />
|
|
</BitField>
|
|
<BitField start="1" size="1" name="ENA_RXEV" description="Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true.">
|
|
<Enum name="DISABLED_RXEV_OUTPU" start="0" description="Disabled. RXEV output to the cpu is disabled." />
|
|
<Enum name="ENABLED_RXEV_OUTPUT" start="1" description="Enabled. RXEV output to the cpu is enabled." />
|
|
</BitField>
|
|
<BitField start="2" size="22" name="RESERVED" description="Reserved. Do not write 1s to unused bits." />
|
|
<BitField start="24" size="8" name="PMAT" description="This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs." />
|
|
</Register>
|
|
<Register start="+0x02C" size="4" name="PMSRC" access="Read/Write" description="Pattern match interrupt bit-slice source register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="8" name="Reserved" description="Software should not write 1s to unused bits." />
|
|
<BitField start="8" size="3" name="SRC0" description="Selects the input source for bit slice 0">
|
|
<Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects the output of pin interrupt select register 0 as the source to bit slice 0." />
|
|
<Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects the output of pin interrupt select register 1 as the source to bit slice 0." />
|
|
<Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects the output of pin interrupt select register 2 as the source to bit slice 0." />
|
|
<Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects the output of pin interrupt select register 3 as the source to bit slice 0." />
|
|
<Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects the output of pin interrupt select register 4 as the source to bit slice 0." />
|
|
<Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects the output of pin interrupt select register 5 as the source to bit slice 0." />
|
|
<Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects the output of pin interrupt select register 6 as the source to bit slice 0." />
|
|
<Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects the output of pin interrupt select register 7 as the source to bit slice 0." />
|
|
</BitField>
|
|
<BitField start="11" size="3" name="SRC1" description="Selects the input source for bit slice 1">
|
|
<Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 1." />
|
|
<Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 1." />
|
|
<Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 1." />
|
|
<Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 1." />
|
|
<Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 1." />
|
|
<Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 1." />
|
|
<Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 1." />
|
|
<Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 1." />
|
|
</BitField>
|
|
<BitField start="14" size="3" name="SRC2" description="Selects the input source for bit slice 2">
|
|
<Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 2." />
|
|
<Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 2." />
|
|
<Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 2." />
|
|
<Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 2." />
|
|
<Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 2." />
|
|
<Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 2." />
|
|
<Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 2." />
|
|
<Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 2." />
|
|
</BitField>
|
|
<BitField start="17" size="3" name="SRC3" description="Selects the input source for bit slice 3">
|
|
<Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 3." />
|
|
<Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 3." />
|
|
<Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 3." />
|
|
<Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 3." />
|
|
<Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 3." />
|
|
<Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 3." />
|
|
<Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 3." />
|
|
<Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 3." />
|
|
</BitField>
|
|
<BitField start="20" size="3" name="SRC4" description="Selects the input source for bit slice 4">
|
|
<Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 4." />
|
|
<Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 4." />
|
|
<Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 4." />
|
|
<Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 4." />
|
|
<Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 4." />
|
|
<Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 4." />
|
|
<Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 4." />
|
|
<Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 4." />
|
|
</BitField>
|
|
<BitField start="23" size="3" name="SRC5" description="Selects the input source for bit slice 5">
|
|
<Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 5." />
|
|
<Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 5." />
|
|
<Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 5." />
|
|
<Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 5." />
|
|
<Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 5." />
|
|
<Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 5." />
|
|
<Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 5." />
|
|
<Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 5." />
|
|
</BitField>
|
|
<BitField start="26" size="3" name="SRC6" description="Selects the input source for bit slice 6">
|
|
<Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 6." />
|
|
<Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 6." />
|
|
<Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 6." />
|
|
<Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 6." />
|
|
<Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 6." />
|
|
<Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 6." />
|
|
<Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 6." />
|
|
<Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 6." />
|
|
</BitField>
|
|
<BitField start="29" size="3" name="SRC7" description="Selects the input source for bit slice 7">
|
|
<Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 7." />
|
|
<Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 7." />
|
|
<Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 7." />
|
|
<Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 7." />
|
|
<Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 7." />
|
|
<Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 7." />
|
|
<Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 7." />
|
|
<Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 7." />
|
|
</BitField>
|
|
</Register>
|
|
<Register start="+0x030" size="4" name="PMCFG" access="Read/Write" description="Pattern match interrupt bit slice configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
|
|
<BitField start="0" size="7" name="PROD_ENDPTS" description="A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice)." />
|
|
<BitField start="7" size="1" name="RESERVED" description="Reserved. Bit slice 7 is automatically considered a product end point." />
|
|
<BitField start="8" size="3" name="CFG0" description="Specifies the match contribution condition for bit slice 0.">
|
|
<Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
|
|
<Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
|
|
<Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
|
|
<Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
|
|
<Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
|
|
</BitField>
|
|
<BitField start="11" size="3" name="CFG1" description="Specifies the match contribution condition for bit slice 1.">
|
|
<Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
|
|
<Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
|
|
<Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
|
|
<Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
|
|
<Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
|
|
</BitField>
|
|
<BitField start="14" size="3" name="CFG2" description="Specifies the match contribution condition for bit slice 2.">
|
|
<Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
|
|
<Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
|
|
<Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
|
|
<Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
|
|
<Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
|
|
</BitField>
|
|
<BitField start="17" size="3" name="CFG3" description="Specifies the match contribution condition for bit slice 3.">
|
|
<Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
|
|
<Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
|
|
<Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
|
|
<Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
|
|
<Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
|
|
</BitField>
|
|
<BitField start="20" size="3" name="CFG4" description="Specifies the match contribution condition for bit slice 4.">
|
|
<Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
|
|
<Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
|
|
<Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
|
|
<Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
|
|
<Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
|
|
</BitField>
|
|
<BitField start="23" size="3" name="CFG5" description="Specifies the match contribution condition for bit slice 5.">
|
|
<Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
|
|
<Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
|
|
<Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
|
|
<Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
|
|
<Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
|
|
</BitField>
|
|
<BitField start="26" size="3" name="CFG6" description="Specifies the match contribution condition for bit slice 6.">
|
|
<Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
|
|
<Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
|
|
<Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
|
|
<Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
|
|
<Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
|
|
</BitField>
|
|
<BitField start="29" size="3" name="CFG7" description="Specifies the match contribution condition for bit slice 7.">
|
|
<Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
|
|
<Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
|
|
<Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
|
|
<Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
|
|
<Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
|
|
<Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
|
|
</BitField>
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
|
|
<Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
|
|
<BitField name="PIN_INT0" start="0" size="1" />
|
|
<BitField name="PIN_INT1" start="1" size="1" />
|
|
<BitField name="PIN_INT2" start="2" size="1" />
|
|
<BitField name="PIN_INT3" start="3" size="1" />
|
|
<BitField name="PIN_INT4" start="4" size="1" />
|
|
<BitField name="PIN_INT5" start="5" size="1" />
|
|
<BitField name="PIN_INT6" start="6" size="1" />
|
|
<BitField name="PIN_INT7" start="7" size="1" />
|
|
<BitField name="GINT0" start="8" size="1" />
|
|
<BitField name="GINT1" start="9" size="1" />
|
|
<BitField name="I2C1" start="10" size="1" />
|
|
<BitField name="USART1_4" start="11" size="1" />
|
|
<BitField name="USART2_3" start="12" size="1" />
|
|
<BitField name="SCT0_1" start="13" size="1" />
|
|
<BitField name="SSP1" start="14" size="1" />
|
|
<BitField name="I2C0" start="15" size="1" />
|
|
<BitField name="CT16B0" start="16" size="1" />
|
|
<BitField name="CT16B1" start="17" size="1" />
|
|
<BitField name="CT32B0" start="18" size="1" />
|
|
<BitField name="CT32B1" start="19" size="1" />
|
|
<BitField name="SSP0" start="20" size="1" />
|
|
<BitField name="USART" start="21" size="1" />
|
|
<BitField name="USB" start="22" size="1" />
|
|
<BitField name="USB_FIQ" start="23" size="1" />
|
|
<BitField name="ADC_A" start="24" size="1" />
|
|
<BitField name="RTC" start="25" size="1" />
|
|
<BitField name="BOD_WDT" start="26" size="1" />
|
|
<BitField name="FLASH" start="27" size="1" />
|
|
<BitField name="DMA" start="28" size="1" />
|
|
<BitField name="USBWAKEUP" start="30" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
|
|
<BitField name="PIN_INT0" start="0" size="1" />
|
|
<BitField name="PIN_INT1" start="1" size="1" />
|
|
<BitField name="PIN_INT2" start="2" size="1" />
|
|
<BitField name="PIN_INT3" start="3" size="1" />
|
|
<BitField name="PIN_INT4" start="4" size="1" />
|
|
<BitField name="PIN_INT5" start="5" size="1" />
|
|
<BitField name="PIN_INT6" start="6" size="1" />
|
|
<BitField name="PIN_INT7" start="7" size="1" />
|
|
<BitField name="GINT0" start="8" size="1" />
|
|
<BitField name="GINT1" start="9" size="1" />
|
|
<BitField name="I2C1" start="10" size="1" />
|
|
<BitField name="USART1_4" start="11" size="1" />
|
|
<BitField name="USART2_3" start="12" size="1" />
|
|
<BitField name="SCT0_1" start="13" size="1" />
|
|
<BitField name="SSP1" start="14" size="1" />
|
|
<BitField name="I2C0" start="15" size="1" />
|
|
<BitField name="CT16B0" start="16" size="1" />
|
|
<BitField name="CT16B1" start="17" size="1" />
|
|
<BitField name="CT32B0" start="18" size="1" />
|
|
<BitField name="CT32B1" start="19" size="1" />
|
|
<BitField name="SSP0" start="20" size="1" />
|
|
<BitField name="USART" start="21" size="1" />
|
|
<BitField name="USB" start="22" size="1" />
|
|
<BitField name="USB_FIQ" start="23" size="1" />
|
|
<BitField name="ADC_A" start="24" size="1" />
|
|
<BitField name="RTC" start="25" size="1" />
|
|
<BitField name="BOD_WDT" start="26" size="1" />
|
|
<BitField name="FLASH" start="27" size="1" />
|
|
<BitField name="DMA" start="28" size="1" />
|
|
<BitField name="USBWAKEUP" start="30" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
|
|
<BitField name="PIN_INT0" start="0" size="1" />
|
|
<BitField name="PIN_INT1" start="1" size="1" />
|
|
<BitField name="PIN_INT2" start="2" size="1" />
|
|
<BitField name="PIN_INT3" start="3" size="1" />
|
|
<BitField name="PIN_INT4" start="4" size="1" />
|
|
<BitField name="PIN_INT5" start="5" size="1" />
|
|
<BitField name="PIN_INT6" start="6" size="1" />
|
|
<BitField name="PIN_INT7" start="7" size="1" />
|
|
<BitField name="GINT0" start="8" size="1" />
|
|
<BitField name="GINT1" start="9" size="1" />
|
|
<BitField name="I2C1" start="10" size="1" />
|
|
<BitField name="USART1_4" start="11" size="1" />
|
|
<BitField name="USART2_3" start="12" size="1" />
|
|
<BitField name="SCT0_1" start="13" size="1" />
|
|
<BitField name="SSP1" start="14" size="1" />
|
|
<BitField name="I2C0" start="15" size="1" />
|
|
<BitField name="CT16B0" start="16" size="1" />
|
|
<BitField name="CT16B1" start="17" size="1" />
|
|
<BitField name="CT32B0" start="18" size="1" />
|
|
<BitField name="CT32B1" start="19" size="1" />
|
|
<BitField name="SSP0" start="20" size="1" />
|
|
<BitField name="USART" start="21" size="1" />
|
|
<BitField name="USB" start="22" size="1" />
|
|
<BitField name="USB_FIQ" start="23" size="1" />
|
|
<BitField name="ADC_A" start="24" size="1" />
|
|
<BitField name="RTC" start="25" size="1" />
|
|
<BitField name="BOD_WDT" start="26" size="1" />
|
|
<BitField name="FLASH" start="27" size="1" />
|
|
<BitField name="DMA" start="28" size="1" />
|
|
<BitField name="USBWAKEUP" start="30" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
|
|
<BitField name="PIN_INT0" start="0" size="1" />
|
|
<BitField name="PIN_INT1" start="1" size="1" />
|
|
<BitField name="PIN_INT2" start="2" size="1" />
|
|
<BitField name="PIN_INT3" start="3" size="1" />
|
|
<BitField name="PIN_INT4" start="4" size="1" />
|
|
<BitField name="PIN_INT5" start="5" size="1" />
|
|
<BitField name="PIN_INT6" start="6" size="1" />
|
|
<BitField name="PIN_INT7" start="7" size="1" />
|
|
<BitField name="GINT0" start="8" size="1" />
|
|
<BitField name="GINT1" start="9" size="1" />
|
|
<BitField name="I2C1" start="10" size="1" />
|
|
<BitField name="USART1_4" start="11" size="1" />
|
|
<BitField name="USART2_3" start="12" size="1" />
|
|
<BitField name="SCT0_1" start="13" size="1" />
|
|
<BitField name="SSP1" start="14" size="1" />
|
|
<BitField name="I2C0" start="15" size="1" />
|
|
<BitField name="CT16B0" start="16" size="1" />
|
|
<BitField name="CT16B1" start="17" size="1" />
|
|
<BitField name="CT32B0" start="18" size="1" />
|
|
<BitField name="CT32B1" start="19" size="1" />
|
|
<BitField name="SSP0" start="20" size="1" />
|
|
<BitField name="USART" start="21" size="1" />
|
|
<BitField name="USB" start="22" size="1" />
|
|
<BitField name="USB_FIQ" start="23" size="1" />
|
|
<BitField name="ADC_A" start="24" size="1" />
|
|
<BitField name="RTC" start="25" size="1" />
|
|
<BitField name="BOD_WDT" start="26" size="1" />
|
|
<BitField name="FLASH" start="27" size="1" />
|
|
<BitField name="DMA" start="28" size="1" />
|
|
<BitField name="USBWAKEUP" start="30" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
|
|
<BitField name="PIN_INT0" start="0" size="1" />
|
|
<BitField name="PIN_INT1" start="1" size="1" />
|
|
<BitField name="PIN_INT2" start="2" size="1" />
|
|
<BitField name="PIN_INT3" start="3" size="1" />
|
|
<BitField name="PIN_INT4" start="4" size="1" />
|
|
<BitField name="PIN_INT5" start="5" size="1" />
|
|
<BitField name="PIN_INT6" start="6" size="1" />
|
|
<BitField name="PIN_INT7" start="7" size="1" />
|
|
<BitField name="GINT0" start="8" size="1" />
|
|
<BitField name="GINT1" start="9" size="1" />
|
|
<BitField name="I2C1" start="10" size="1" />
|
|
<BitField name="USART1_4" start="11" size="1" />
|
|
<BitField name="USART2_3" start="12" size="1" />
|
|
<BitField name="SCT0_1" start="13" size="1" />
|
|
<BitField name="SSP1" start="14" size="1" />
|
|
<BitField name="I2C0" start="15" size="1" />
|
|
<BitField name="CT16B0" start="16" size="1" />
|
|
<BitField name="CT16B1" start="17" size="1" />
|
|
<BitField name="CT32B0" start="18" size="1" />
|
|
<BitField name="CT32B1" start="19" size="1" />
|
|
<BitField name="SSP0" start="20" size="1" />
|
|
<BitField name="USART" start="21" size="1" />
|
|
<BitField name="USB" start="22" size="1" />
|
|
<BitField name="USB_FIQ" start="23" size="1" />
|
|
<BitField name="ADC_A" start="24" size="1" />
|
|
<BitField name="RTC" start="25" size="1" />
|
|
<BitField name="BOD_WDT" start="26" size="1" />
|
|
<BitField name="FLASH" start="27" size="1" />
|
|
<BitField name="DMA" start="28" size="1" />
|
|
<BitField name="USBWAKEUP" start="30" size="1" />
|
|
</Register>
|
|
<Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
|
|
<BitField name="PIN_INT0" start="4" size="4" />
|
|
<BitField name="PIN_INT1" start="12" size="4" />
|
|
<BitField name="PIN_INT2" start="20" size="4" />
|
|
<BitField name="PIN_INT3" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
|
|
<BitField name="PIN_INT4" start="4" size="4" />
|
|
<BitField name="PIN_INT5" start="12" size="4" />
|
|
<BitField name="PIN_INT6" start="20" size="4" />
|
|
<BitField name="PIN_INT7" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
|
|
<BitField name="GINT0" start="4" size="4" />
|
|
<BitField name="GINT1" start="12" size="4" />
|
|
<BitField name="I2C1" start="20" size="4" />
|
|
<BitField name="USART1_4" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
|
|
<BitField name="USART2_3" start="4" size="4" />
|
|
<BitField name="SCT0_1" start="12" size="4" />
|
|
<BitField name="SSP1" start="20" size="4" />
|
|
<BitField name="I2C0" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
|
|
<BitField name="CT16B0" start="4" size="4" />
|
|
<BitField name="CT16B1" start="12" size="4" />
|
|
<BitField name="CT32B0" start="20" size="4" />
|
|
<BitField name="CT32B1" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
|
|
<BitField name="SSP0" start="4" size="4" />
|
|
<BitField name="USART" start="12" size="4" />
|
|
<BitField name="USB" start="20" size="4" />
|
|
<BitField name="USB_FIQ" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
|
|
<BitField name="ADC_A" start="4" size="4" />
|
|
<BitField name="RTC" start="12" size="4" />
|
|
<BitField name="BOD_WDT" start="20" size="4" />
|
|
<BitField name="FLASH" start="28" size="4" />
|
|
</Register>
|
|
<Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
|
|
<BitField name="DMA" start="4" size="4" />
|
|
<BitField name="USBWAKEUP" start="20" size="4" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SysTick" start="0xe000e010" description="24-bit System Timer">
|
|
<Register name="SYST_CSR" start="0xe000e010" description="SysTick Control and Status Register">
|
|
<BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
|
|
<BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
|
|
<BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
|
|
<BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
|
|
</Register>
|
|
<Register name="SYST_RVR" start="0xe000e014" description="SysTick Reload Value Register">
|
|
<BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
|
|
</Register>
|
|
<Register name="SYST_CVR" start="0xe000e018" description="SysTick Current Value Register Register">
|
|
<BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
|
|
</Register>
|
|
<Register name="SYST_CALIB" start="0xe000e01c" access="ReadOnly" description="SysTick Calibration Value Register">
|
|
<BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
|
|
<BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
|
|
<BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
<RegisterGroup name="SCB" start="0xe000e000" description="System Control Block">
|
|
<Register name="CPUID" start="0xe000ed00" access="ReadOnly" description="CPUID Register">
|
|
<BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
|
|
<BitField name="VARIANT" start="20" size="4" description="Variant Number" />
|
|
<BitField name="PARTNO" start="4" size="12" description="Part Number" />
|
|
<BitField name="REVISION" start="0" size="4" description="Revision Number" />
|
|
</Register>
|
|
<Register name="ICSR" start="0xe000ed04" description="Interrupt Control and State Register">
|
|
<BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
|
|
<BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
|
|
<BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
|
|
<BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
|
|
<BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
|
|
<BitField name="ISRPREEMPT" start="23" size="1" description="" />
|
|
<BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
|
|
<BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
|
|
<BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
|
|
</Register>
|
|
<Register name="VTOR" start="0xe000ed08" description="Vector Table Offset Register">
|
|
<BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
|
|
</Register>
|
|
<Register name="AIRCR" start="0xe000ed0c" description="Application Interrupt and Reset Control Register">
|
|
<BitField name="VECTKEY" start="16" size="16" description="Register key" />
|
|
<BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
|
|
<BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
|
|
<BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
|
|
</Register>
|
|
<Register name="SCR" start="0xe000ed10" description="System Control Register">
|
|
<BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
|
|
<BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
|
|
<BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
|
|
</Register>
|
|
<Register name="CCR" start="0xe000ed14" access="ReadOnly" description="Configuration and Control Register">
|
|
<BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
|
|
<BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
|
|
</Register>
|
|
<Register name="SHPR2" start="0xe000ed1c" description="System Handler Priority Register 2">
|
|
<BitField name="PRI_11(SVCall)" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
|
|
</Register>
|
|
<Register name="SHPR3" start="0xe000ed20" description="System Handler Priority Register 3">
|
|
<BitField name="PRI_15(SysTick)" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
|
|
<BitField name="PRI_14(PendSV)" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
|
|
</Register>
|
|
<Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
|
|
<BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
|
|
</Register>
|
|
<Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
|
|
<BitField name="EXTERNAL" start="4" size="1" description="" />
|
|
<BitField name="VCATCH" start="3" size="1" description="" />
|
|
<BitField name="DWTTRAP" start="2" size="1" description="" />
|
|
<BitField name="BKPT" start="1" size="1" description="" />
|
|
<BitField name="HALTED" start="0" size="1" description="" />
|
|
</Register>
|
|
</RegisterGroup>
|
|
</Processor>
|