482 lines
14 KiB
C
482 lines
14 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018, hathach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if CFG_TUSB_MCU == OPT_MCU_SAMG
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#include "sam.h"
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#include "device/dcd.h"
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// TODO should support (SAM3S || SAM4S || SAM4E || SAMG55)
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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#define EP_COUNT 6
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// Transfer descriptor
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typedef struct
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{
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uint8_t* buffer;
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uint16_t total_len;
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volatile uint16_t actual_len;
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uint16_t epsize;
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} xfer_desc_t;
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// Endpoint 0-5, each can only be either OUT or In
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xfer_desc_t _dcd_xfer[EP_COUNT];
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// Indicate that DATA Toggle for Control Status is incorrect, which must always be DATA1 by USB Specs.
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// However SAMG DToggle is read-only, therefore we must duplicate the status phase ( D0 then D1 )
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// as walk-around to resolve this. The D0 status packet is likely to be discarded by USB Host safely.
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// Note: Only needed for IN Status e.g CDC_SET_LINE_CODING, since out data is sent by host
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volatile bool _walkaround_incorrect_dtoggle_control_status;
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void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize)
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{
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xfer->epsize = epsize;
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}
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void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes)
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{
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xfer->buffer = buffer;
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xfer->total_len = total_bytes;
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xfer->actual_len = 0;
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}
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void xfer_end(xfer_desc_t* xfer)
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{
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xfer->buffer = NULL;
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xfer->total_len = 0;
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xfer->actual_len = 0;
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}
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uint16_t xfer_packet_len(xfer_desc_t* xfer)
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{
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// also cover zero-length packet
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return tu_min16(xfer->total_len - xfer->actual_len, xfer->epsize);
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}
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void xfer_packet_done(xfer_desc_t* xfer)
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{
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uint16_t const xact_len = xfer_packet_len(xfer);
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xfer->buffer += xact_len;
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xfer->actual_len += xact_len;
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}
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//------------- Transaction helpers -------------//
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// Write data to EP FIFO, return number of written bytes
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static void xact_ep_write(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
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{
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for(uint16_t i=0; i<xact_len; i++)
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{
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UDP->UDP_FDR[epnum] = (uint32_t) buffer[i];
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}
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}
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// Read data from EP FIFO
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static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
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{
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for(uint16_t i=0; i<xact_len; i++)
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{
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buffer[i] = (uint8_t) UDP->UDP_FDR[epnum];
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}
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}
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/*------------------------------------------------------------------*/
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/* Device API
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*------------------------------------------------------------------*/
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// Set up endpoint 0, clear all other endpoints
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static void bus_reset(void)
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{
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_walkaround_incorrect_dtoggle_control_status = false;
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tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
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xfer_epsize_set(&_dcd_xfer[0], CFG_TUD_ENDPOINT0_SIZE);
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// Enable EP0 control
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UDP->UDP_CSR[0] = UDP_CSR_EPEDS_Msk;
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// Enable interrupt : EP0, Suspend, Resume, Wakeup
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UDP->UDP_IER = UDP_IER_EP0INT_Msk | UDP_IER_RXSUSP_Msk | UDP_IER_RXRSM_Msk | UDP_IER_WAKEUP_Msk;
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// Enable transceiver
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UDP->UDP_TXVC &= ~UDP_TXVC_TXVDIS_Msk;
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}
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// Initialize controller to device mode
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void dcd_init (uint8_t rhport)
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{
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(void) rhport;
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tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
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}
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// Enable device interrupt
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void dcd_int_enable (uint8_t rhport)
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{
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(void) rhport;
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NVIC_EnableIRQ(UDP_IRQn);
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}
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// Disable device interrupt
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void dcd_int_disable (uint8_t rhport)
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{
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(void) rhport;
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NVIC_DisableIRQ(UDP_IRQn);
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}
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// Receive Set Address request, mcu port must also include status IN response
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void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
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{
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(void) rhport;
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(void) dev_addr;
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// Response with zlp status
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dcd_edpt_xfer(rhport, 0x80, NULL, 0);
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// DCD can only set address after status for this request is complete.
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// do it at dcd_edpt0_status_complete()
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}
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// Receive Set Configure request
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void dcd_set_config (uint8_t rhport, uint8_t config_num)
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{
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(void) rhport;
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(void) config_num;
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// Configured State
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// UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG_Msk;
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}
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// Wake up host
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void dcd_remote_wakeup (uint8_t rhport)
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{
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(void) rhport;
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}
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void dcd_connect(uint8_t rhport)
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{
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(void) rhport;
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// Enable pull-up, disable transceiver
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UDP->UDP_TXVC = UDP_TXVC_PUON | UDP_TXVC_TXVDIS_Msk;
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}
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void dcd_disconnect(uint8_t rhport)
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{
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(void) rhport;
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// disable both pullup and transceiver
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UDP->UDP_TXVC = UDP_TXVC_TXVDIS_Msk;
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}
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//--------------------------------------------------------------------+
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// Endpoint API
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//--------------------------------------------------------------------+
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// Invoked when a control transfer's status stage is complete.
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// May help DCD to prepare for next control transfer, this API is optional.
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void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
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{
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(void) rhport;
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if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
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request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
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{
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if (request->bRequest == TUSB_REQ_SET_ADDRESS)
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{
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uint8_t const dev_addr = (uint8_t) request->wValue;
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// Enable addressed state
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UDP->UDP_GLB_STAT |= UDP_GLB_STAT_FADDEN_Msk;
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// Set new address & Function enable bit
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UDP->UDP_FADDR = UDP_FADDR_FEN_Msk | UDP_FADDR_FADD(dev_addr);
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}
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else if (request->bRequest == TUSB_REQ_SET_CONFIGURATION)
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{
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// Configured State
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UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG_Msk;
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}
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}
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}
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// Configure endpoint's registers according to descriptor
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// SAMG doesn't support a same endpoint number with IN and OUT
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// e.g EP1 OUT & EP1 IN cannot exist together
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bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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{
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(void) rhport;
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uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
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uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress);
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// TODO Isochronous is not supported yet
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TU_VERIFY(ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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TU_VERIFY(epnum < EP_COUNT);
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// Must not already enabled
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TU_ASSERT((UDP->UDP_CSR[epnum] & UDP_CSR_EPEDS_Msk) == 0);
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xfer_epsize_set(&_dcd_xfer[epnum], ep_desc->wMaxPacketSize.size);
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// Configure type and eanble EP
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UDP->UDP_CSR[epnum] = UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4*dir);
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// Enable EP Interrupt for IN
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if (dir == TUSB_DIR_IN) UDP->UDP_IER |= (1 << epnum);
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return true;
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}
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// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
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bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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(void) rhport;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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xfer_desc_t* xfer = &_dcd_xfer[epnum];
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xfer_begin(xfer, buffer, total_bytes);
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if (dir == TUSB_DIR_OUT)
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{
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// Clear EP0 direction bit
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if (epnum == 0) UDP->UDP_CSR[epnum] &= ~UDP_CSR_DIR_Msk;
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// Enable interrupt when starting OUT transfer
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if (epnum != 0) UDP->UDP_IER |= (1 << epnum);
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}
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else
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{
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if (epnum == 0)
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{
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// Previous EP0 direction is OUT --> This transfer is ZLP control status.
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if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DIR_Msk) )
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{
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// Set EP0 dir bit
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UDP->UDP_CSR[epnum] |= UDP_CSR_DIR_Msk;
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// DATA Toggle is 0, USB Specs requires Status Stage must be DATA1
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// Since SAMG DToggle is read-only, we mark this and implement the walk-around
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if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DTGLE_Msk) )
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{
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TU_LOG2("Incorrect DATA TOGGLE, Control Status must be DATA1\n");
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// DTGLE is read-only on SAMG, this statement has no effect
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UDP->UDP_CSR[epnum] |= UDP_CSR_DTGLE_Msk;
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// WALKROUND: duplicate IN transfer to send DATA1 status packet
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// set flag for irq to skip reporting first incorrect packet
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_walkaround_incorrect_dtoggle_control_status = true;
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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while ( UDP->UDP_CSR[epnum] & UDP_CSR_TXPKTRDY_Msk ) {}
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_walkaround_incorrect_dtoggle_control_status = false;
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}
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}
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}
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xact_ep_write(epnum, xfer->buffer, xfer_packet_len(xfer));
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// TX ready for transfer
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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}
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return true;
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}
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// Stall endpoint
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void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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// Set force stall bit
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UDP->UDP_CSR[epnum] |= UDP_CSR_FORCESTALL_Msk;
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}
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// clear stall, data toggle is also reset to DATA0
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void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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// clear stall
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_FORCESTALL_Msk;
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// must also reset EP to clear data toggle
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UDP->UDP_RST_EP = tu_bit_set(UDP->UDP_RST_EP, epnum);
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UDP->UDP_RST_EP = tu_bit_clear(UDP->UDP_RST_EP, epnum);
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}
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//--------------------------------------------------------------------+
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// ISR
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//--------------------------------------------------------------------+
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void dcd_int_handler(uint8_t rhport)
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{
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uint32_t const intr_mask = UDP->UDP_IMR;
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uint32_t const intr_status = UDP->UDP_ISR & intr_mask;
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// clear interrupt
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UDP->UDP_ICR = intr_status;
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// Bus reset
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if (intr_status & UDP_ISR_ENDBUSRES_Msk)
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{
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bus_reset();
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dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
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}
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// SOF
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// if (intr_status & UDP_ISR_SOFINT_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
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// Suspend
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if (intr_status & UDP_ISR_RXSUSP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
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// Resume
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if (intr_status & UDP_ISR_RXRSM_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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// Wakeup
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if (intr_status & UDP_ISR_WAKEUP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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//------------- Endpoints -------------//
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if ( intr_status & TU_BIT(0) )
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{
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// setup packet
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if (UDP->UDP_CSR[0] & UDP_CSR_RXSETUP)
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{
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// get setup from FIFO
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uint8_t setup[8];
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for(uint8_t i=0; i<sizeof(setup); i++)
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{
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setup[i] = (uint8_t) UDP->UDP_FDR[0];
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}
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// notify usbd
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dcd_event_setup_received(rhport, setup, true);
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// Set EP direction bit according to DATA stage
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if (setup[0] & 0x80)
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{
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UDP->UDP_CSR[0] |= UDP_CSR_DIR_Msk;
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}else
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{
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UDP->UDP_CSR[0] &= ~UDP_CSR_DIR_Msk;
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}
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// Clear Setup bit & stall bit if needed
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UDP->UDP_CSR[0] &= ~(UDP_CSR_RXSETUP_Msk | UDP_CSR_FORCESTALL_Msk);
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return;
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}
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}
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for(uint8_t epnum = 0; epnum < EP_COUNT; epnum++)
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{
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if ( intr_status & TU_BIT(epnum) )
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{
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xfer_desc_t* xfer = &_dcd_xfer[epnum];
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//------------- Endpoint IN -------------//
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if (UDP->UDP_CSR[epnum] & UDP_CSR_TXCOMP_Msk)
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{
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xfer_packet_done(xfer);
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uint16_t const xact_len = xfer_packet_len(xfer);
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if (xact_len)
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{
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// write to EP fifo
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xact_ep_write(epnum, xfer->buffer, xact_len);
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// TX ready for transfer
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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}else
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{
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// WALKAROUND: Skip reporting this incorrect DATA Toggle status IN transfer
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if ( !(_walkaround_incorrect_dtoggle_control_status && (epnum == 0) && (xfer->actual_len == 0)) )
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{
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// xfer is complete
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dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
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// Required since control OUT can happen right after before stack handle this event
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xfer_end(xfer);
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}
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}
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// Clear TX Complete bit
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_TXCOMP_Msk;
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}
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//------------- Endpoint OUT -------------//
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// Ping-Pong is a MUST for Bulk/Iso
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// NOTE: When both Bank0 and Bank1 are both set, there is no way to know which one comes first
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uint32_t const banks_complete = UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk);
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if (banks_complete)
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{
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uint16_t const xact_len = (uint16_t) ((UDP->UDP_CSR[epnum] & UDP_CSR_RXBYTECNT_Msk) >> UDP_CSR_RXBYTECNT_Pos);
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// Read from EP fifo
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xact_ep_read(epnum, xfer->buffer, xact_len);
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xfer_packet_done(xfer);
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if ( 0 == xfer_packet_len(xfer) )
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{
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// Disable OUT EP interrupt when transfer is complete
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if (epnum != 0) UDP->UDP_IDR |= (1 << epnum);
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dcd_event_xfer_complete(rhport, epnum, xfer->actual_len, XFER_RESULT_SUCCESS, true);
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xfer_end(xfer);
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}
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// Clear DATA Bank0/1 bit
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UDP->UDP_CSR[epnum] &= ~banks_complete;
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}
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// Stall sent to host
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if (UDP->UDP_CSR[epnum] & UDP_CSR_STALLSENT_Msk)
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{
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_STALLSENT_Msk;
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}
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}
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}
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}
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#endif
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