531 lines
19 KiB
C
531 lines
19 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || \
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CFG_TUSB_MCU == OPT_MCU_LPC43XX || \
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CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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#include "common/tusb_common.h"
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#include "device/dcd.h"
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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#include "fsl_device_registers.h"
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#define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
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IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn, USB_OTG2_IRQn };
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#else
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#include "chip.h"
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#define DCD_REGS_BASE { (dcd_registers_t*) LPC_USB0_BASE, (dcd_registers_t*) LPC_USB1_BASE }
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IRQn_Type DCD_IRQn[] = { USB0_IRQn, USB1_IRQn };
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#endif
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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// ENDPTCTRL
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enum {
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ENDPTCTRL_STALL = TU_BIT(0),
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ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
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ENDPTCTRL_TOGGLE_RESET = TU_BIT(6),
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ENDPTCTRL_ENABLE = TU_BIT(7)
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};
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// USBCMD
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enum {
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USBCMD_RUN_STOP = TU_BIT(0),
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USBCMD_RESET = TU_BIT(1),
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USBCMD_SETUP_TRIPWIRE = TU_BIT(13),
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USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
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};
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// Interrupt Threshold bit 23:16
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// USBSTS, USBINTR
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enum {
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INTR_USB = TU_BIT(0),
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INTR_ERROR = TU_BIT(1),
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INTR_PORT_CHANGE = TU_BIT(2),
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INTR_RESET = TU_BIT(6),
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INTR_SOF = TU_BIT(7),
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INTR_SUSPEND = TU_BIT(8),
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INTR_NAK = TU_BIT(16)
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};
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// PORTSC1
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enum {
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PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0),
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PORTSC1_FORCE_PORT_RESUME = TU_BIT(6),
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PORTSC1_SUSPEND = TU_BIT(7),
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PORTSC1_FORCE_FULL_SPEED = TU_BIT(24),
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};
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// OTGSC
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enum {
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OTGSC_VBUS_DISCHARGE = TU_BIT(0),
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OTGSC_VBUS_CHARGE = TU_BIT(1),
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// OTGSC_HWASSIST_AUTORESET = TU_BIT(2),
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OTGSC_OTG_TERMINATION = TU_BIT(3), ///< Must set to 1 when OTG go to device mode
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OTGSC_DATA_PULSING = TU_BIT(4),
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OTGSC_ID_PULLUP = TU_BIT(5),
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// OTGSC_HWASSIT_DATA_PULSE = TU_BIT(6),
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// OTGSC_HWASSIT_BDIS_ACONN = TU_BIT(7),
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OTGSC_ID = TU_BIT(8), ///< 0 = A device, 1 = B Device
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OTGSC_A_VBUS_VALID = TU_BIT(9),
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OTGSC_A_SESSION_VALID = TU_BIT(10),
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OTGSC_B_SESSION_VALID = TU_BIT(11),
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OTGSC_B_SESSION_END = TU_BIT(12),
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OTGSC_1MS_TOGGLE = TU_BIT(13),
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OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14),
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};
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// USBMode
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enum {
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USBMODE_CM_DEVICE = 2,
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USBMODE_CM_HOST = 3,
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USBMODE_SLOM = TU_BIT(3),
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USBMODE_SDIS = TU_BIT(4),
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USBMODE_VBUS_POWER_SELCT = TU_BIT(5), // Enable for LPC18XX/43XX in host most only
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};
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// Device Registers
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typedef struct
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{
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//------------- ID + HW Parameter Registers-------------//
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__I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
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//------------- Capability Registers-------------//
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__I uint8_t CAPLENGTH; ///< Capability Registers Length
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__I uint8_t TU_RESERVED[1];
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__I uint16_t HCIVERSION; ///< Host Controller Interface Version
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__I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters
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__I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters
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__I uint32_t TU_RESERVED[5];
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__I uint16_t DCIVERSION; ///< Device Controller Interface Version
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__I uint8_t TU_RESERVED[2];
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__I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters
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__I uint32_t TU_RESERVED[6];
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//------------- Operational Registers -------------//
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__IO uint32_t USBCMD; ///< USB Command Register
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__IO uint32_t USBSTS; ///< USB Status Register
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__IO uint32_t USBINTR; ///< Interrupt Enable Register
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__IO uint32_t FRINDEX; ///< USB Frame Index
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__I uint32_t TU_RESERVED;
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__IO uint32_t DEVICEADDR; ///< Device Address
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__IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address
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__I uint32_t TU_RESERVED;
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__IO uint32_t BURSTSIZE; ///< Programmable Burst Size
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__IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning
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uint32_t TU_RESERVED[4];
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__IO uint32_t ENDPTNAK; ///< Endpoint NAK
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__IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable
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__I uint32_t TU_RESERVED;
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__IO uint32_t PORTSC1; ///< Port Status & Control
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__I uint32_t TU_RESERVED[7];
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__IO uint32_t OTGSC; ///< On-The-Go Status & control
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__IO uint32_t USBMODE; ///< USB Device Mode
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__IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status
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__IO uint32_t ENDPTPRIME; ///< Endpoint Prime
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__IO uint32_t ENDPTFLUSH; ///< Endpoint Flush
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__I uint32_t ENDPTSTAT; ///< Endpoint Status
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__IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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__IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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} dcd_registers_t;
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// Queue Transfer Descriptor
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typedef struct
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{
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// Word 0: Next QTD Pointer
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uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
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// Word 1: qTQ Token
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uint32_t : 3 ;
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volatile uint32_t xact_err : 1 ;
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uint32_t : 1 ;
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volatile uint32_t buffer_err : 1 ;
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volatile uint32_t halted : 1 ;
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volatile uint32_t active : 1 ;
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uint32_t : 2 ;
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uint32_t iso_mult_override : 2 ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
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uint32_t : 3 ;
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uint32_t int_on_complete : 1 ;
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volatile uint32_t total_bytes : 15 ;
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uint32_t : 0 ;
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// Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
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uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
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//------------- DCD Area -------------//
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uint16_t expected_bytes;
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uint8_t reserved[2];
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} dcd_qtd_t;
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TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
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// Queue Head
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typedef struct
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{
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// Word 0: Capabilities and Characteristics
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uint32_t : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
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uint32_t int_on_setup : 1 ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
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uint32_t max_package_size : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
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uint32_t : 2 ;
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uint32_t zero_length_termination : 1 ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
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uint32_t iso_mult : 2 ; ///<
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uint32_t : 0 ;
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// Word 1: Current qTD Pointer
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volatile uint32_t qtd_addr;
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// Word 2-9: Transfer Overlay
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volatile dcd_qtd_t qtd_overlay;
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// Word 10-11: Setup request (control OUT only)
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volatile tusb_control_request_t setup_request;
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//--------------------------------------------------------------------+
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/// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
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/// thus there are 16 bytes padding free that we can make use of.
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//--------------------------------------------------------------------+
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uint8_t reserved[16];
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} dcd_qhd_t;
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TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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//--------------------------------------------------------------------+
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// Variables
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//--------------------------------------------------------------------+
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#define QHD_MAX 12
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#define QTD_NEXT_INVALID 0x01
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typedef struct {
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// Must be at 2K alignment
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dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
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dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32);
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}dcd_data_t;
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static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
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static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
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//--------------------------------------------------------------------+
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// CONTROLLER API
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//--------------------------------------------------------------------+
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/// follows LPC43xx User Manual 23.10.3
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static void bus_reset(uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = DCD_REGS[rhport];
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// The reset value for all endpoint types is the control endpoint. If one endpoint
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// direction is enabled and the paired endpoint of opposite direction is disabled, then the
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// endpoint type of the unused direction must bechanged from the control type to any other
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// type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
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// for the data PID tracking on the active endpoint.
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// USB0 has 5 but USB1 only has 3 non-control endpoints
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for( int i=1; i < (rhport ? 6 : 4); i++)
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{
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dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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}
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//------------- Clear All Registers -------------//
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dcd_reg->ENDPTNAK = dcd_reg->ENDPTNAK;
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dcd_reg->ENDPTNAKEN = 0;
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dcd_reg->USBSTS = dcd_reg->USBSTS;
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dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
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dcd_reg->ENDPTCOMPLETE = dcd_reg->ENDPTCOMPLETE;
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while (dcd_reg->ENDPTPRIME);
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dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
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while (dcd_reg->ENDPTFLUSH);
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// read reset bit in portsc
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//------------- Queue Head & Queue TD -------------//
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tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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//------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
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_dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
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_dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
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_dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
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_dcd_data.qhd[0].int_on_setup = 1; // OUT only
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}
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void dcd_init(uint8_t rhport)
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{
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tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
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// Reset controller
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dcd_reg->USBCMD |= USBCMD_RESET;
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while( dcd_reg->USBCMD & USBCMD_RESET ) {}
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// Set mode to device, must be set immediately after reset
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dcd_reg->USBMODE = USBMODE_CM_DEVICE;
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dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
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// TODO Force fullspeed on non-highspeed port
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// dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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dcd_reg->USBSTS = dcd_reg->USBSTS;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF;
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dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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dcd_reg->USBCMD |= TU_BIT(0); // connect
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}
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void dcd_int_enable(uint8_t rhport)
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{
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NVIC_EnableIRQ(DCD_IRQn[rhport]);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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NVIC_DisableIRQ(DCD_IRQn[rhport]);
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}
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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{
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// Response with status first before changing device address
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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DCD_REGS[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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}
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void dcd_set_config(uint8_t rhport, uint8_t config_num)
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{
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(void) rhport;
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(void) config_num;
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// nothing to do
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}
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void dcd_remote_wakeup(uint8_t rhport)
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{
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(void) rhport;
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}
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//--------------------------------------------------------------------+
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// HELPER
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//--------------------------------------------------------------------+
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// index to bit position in register
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static inline uint8_t ep_idx2bit(uint8_t ep_idx)
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{
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return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
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}
|
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static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
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{
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tu_memclr(p_qtd, sizeof(dcd_qtd_t));
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p_qtd->next = QTD_NEXT_INVALID;
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p_qtd->active = 1;
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p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
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if (data_ptr != NULL)
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{
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p_qtd->buffer[0] = (uint32_t) data_ptr;
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for(uint8_t i=1; i<5; i++)
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{
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p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
|
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}
|
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}
|
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}
|
||
|
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//--------------------------------------------------------------------+
|
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// DCD Endpoint Port
|
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//--------------------------------------------------------------------+
|
||
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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{
|
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
|
||
|
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
|
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}
|
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|
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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|
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// data toggle also need to be reset
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
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DCD_REGS[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0));
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}
|
||
|
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
|
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{
|
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// TODO not support ISO yet
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TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
|
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|
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uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
|
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uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
|
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uint8_t const ep_idx = 2*epnum + dir;
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|
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// USB0 has 5, USB1 has 3 non-control endpoints
|
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TU_ASSERT( epnum <= (rhport ? 3 : 5) );
|
||
|
||
//------------- Prepare Queue Head -------------//
|
||
dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
|
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tu_memclr(p_qhd, sizeof(dcd_qhd_t));
|
||
|
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p_qhd->zero_length_termination = 1;
|
||
p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
|
||
p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
|
||
|
||
// Enable EP Control
|
||
DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
|
||
|
||
return true;
|
||
}
|
||
|
||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
||
{
|
||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||
uint8_t const ep_idx = 2*epnum + dir;
|
||
|
||
if ( epnum == 0 )
|
||
{
|
||
// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
|
||
// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
|
||
while(DCD_REGS[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
|
||
}
|
||
|
||
dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
|
||
dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
|
||
|
||
//------------- Prepare qtd -------------//
|
||
qtd_init(p_qtd, buffer, total_bytes);
|
||
p_qtd->int_on_complete = true;
|
||
p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
|
||
|
||
// start transfer
|
||
DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
|
||
|
||
return true;
|
||
}
|
||
|
||
//--------------------------------------------------------------------+
|
||
// ISR
|
||
//--------------------------------------------------------------------+
|
||
void dcd_isr(uint8_t rhport)
|
||
{
|
||
dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
|
||
|
||
uint32_t const int_enable = dcd_reg->USBINTR;
|
||
uint32_t const int_status = dcd_reg->USBSTS & int_enable;
|
||
dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt
|
||
|
||
// disabled interrupt sources
|
||
if (int_status == 0) return;
|
||
|
||
if (int_status & INTR_RESET)
|
||
{
|
||
bus_reset(rhport);
|
||
dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
|
||
}
|
||
|
||
if (int_status & INTR_SUSPEND)
|
||
{
|
||
if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
|
||
{
|
||
// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
|
||
if ((dcd_reg->DEVICEADDR >> 25) & 0x0f)
|
||
{
|
||
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
|
||
}
|
||
}
|
||
}
|
||
|
||
// TODO disconnection does not generate interrupt !!!!!!
|
||
// if (int_status & INTR_PORT_CHANGE)
|
||
// {
|
||
// if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) )
|
||
// {
|
||
// dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
|
||
// dcd_event_handler(&event, true);
|
||
// }
|
||
// }
|
||
|
||
if (int_status & INTR_USB)
|
||
{
|
||
uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
|
||
dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
|
||
|
||
if (dcd_reg->ENDPTSETUPSTAT)
|
||
{
|
||
//------------- Set up Received -------------//
|
||
// 23.10.10.2 Operational model for setup transfers
|
||
dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;// acknowledge
|
||
|
||
dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0].setup_request, true);
|
||
}
|
||
|
||
if ( edpt_complete )
|
||
{
|
||
for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
|
||
{
|
||
if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
|
||
{
|
||
// 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
|
||
dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
|
||
|
||
uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
|
||
( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
|
||
|
||
uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
|
||
dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
if (int_status & INTR_SOF)
|
||
{
|
||
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
||
}
|
||
|
||
if (int_status & INTR_NAK) {}
|
||
if (int_status & INTR_ERROR) TU_ASSERT(false, );
|
||
}
|
||
|
||
#endif
|