356 lines
10 KiB
C
356 lines
10 KiB
C
/*
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* @brief LPCSPIFILIB hardware definitions and functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licenser disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __SPIFILIB_CHIPHW_H_
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#define __SPIFILIB_CHIPHW_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Define for inline */
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#ifndef INLINE
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#ifdef __CC_ARM
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#define INLINE __inline
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#else
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#define INLINE inline
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#endif /* __CC_ARM */
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#endif /* !INLINE */
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#ifdef __CC_ARM
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#pragma anon_unions
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#endif
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/** @defgroup LPCSPIFILIB_HW_API LPCSPIFILIB hardware definitions and API functions
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* @ingroup LPCSPIFILIB
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* @{
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*/
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/**
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* @brief SPIFI controller hardware register structure
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*/
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typedef struct LPC_SPIFI_CHIPHW {
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volatile uint32_t CTRL; /**< SPIFI control register */
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volatile uint32_t CMD; /**< SPIFI command register */
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volatile uint32_t ADDR; /**< SPIFI address register */
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volatile uint32_t DATINTM; /**< SPIFI intermediate data register */
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volatile uint32_t CACHELIMIT; /**< SPIFI cache limit register */
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union {
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volatile uint8_t DAT8; /**< SPIFI 8 bit data */
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volatile uint16_t DAT16; /**< SPIFI 16 bit data */
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volatile uint32_t DAT32; /**< SPIFI 32 bit data */
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};
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volatile uint32_t MEMCMD; /**< SPIFI memory command register */
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volatile uint32_t STAT; /**< SPIFI status register */
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} LPC_SPIFI_T;
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/** @defgroup LPCSPIFILIB_HW_PRIM LPCSPIFILIB primative API functions
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* @{
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*/
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/**
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* @brief SPIFI controller control register bit definitions
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*/
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#define SPIFI_CTRL_TO(t) ((t) << 0) /**< SPIFI timeout */
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#define SPIFI_CTRL_CSHI(c) ((c) << 16) /**< SPIFI chip select minimum high time */
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#define SPIFI_CTRL_DATA_PREFETCH_DISABLE(d) ((d) << 21) /**< SPIFI memMode prefetch enable*/
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#define SPIFI_CTRL_INTEN(i) ((i) << 22) /**< SPIFI cmdComplete irq enable */
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#define SPIFI_CTRL_MODE3(m) ((m) << 23) /**< SPIFI mode3 config */
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#define SPIFI_CTRL_PREFETCH_DISABLE(d) ((d) << 27) /**< SPIFI cache prefetch enable */
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#define SPIFI_CTRL_DUAL(d) ((d) << 28) /**< SPIFI enable dual */
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#define SPIFI_CTRL_RFCLK(m) ((m) << 29) /**< SPIFI clock edge config */
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#define SPIFI_CTRL_FBCLK(m) ((m) << 30) /**< SPIFI feedback clock select */
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#define SPIFI_CTRL_DMAEN(m) ((m) << 31) /**< SPIFI dma enable */
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/**
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* @brief Write SPIFI controller control register
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* @param pSpifi : Base address of SPIFI controller
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* @param ctrl : Control value to write
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* @return Nothing
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*/
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static INLINE void spifi_HW_SetCtrl(LPC_SPIFI_T *pSpifi, uint32_t ctrl)
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{
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pSpifi->CTRL = ctrl;
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}
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/**
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* @brief Read SPIFI controller control register
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* @param pSpifi : Base address of SPIFI controller
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* @return Current CTRL register values
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*/
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static INLINE uint32_t spifi_HW_GetCtrl(LPC_SPIFI_T *pSpifi)
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{
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return pSpifi->CTRL;
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}
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/**
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* @brief SPIFI controller status register bit definitions
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*/
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#define SPIFI_STAT_RESET (1 << 4) /**< SPIFI reset */
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#define SPIFI_STAT_INTRQ (1 << 5) /**< SPIFI interrupt request */
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#define SPIFI_STAT_CMD (1 << 1) /**< SPIFI command in progress */
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#define SPIFI_STAT_MCINIT (1) /**< SPIFI MCINIT */
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/**
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* @brief Write SPIFI controller status register
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* @param pSpifi : Base address of SPIFI controller
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* @param stat : Status bits to write
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* @return Nothing
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*/
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static INLINE void spifi_HW_SetStat(LPC_SPIFI_T *pSpifi, uint32_t stat)
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{
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pSpifi->STAT = stat;
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}
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/**
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* @brief Read SPIFI controller status register
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* @param pSpifi : Base address of SPIFI controller
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* @return Current STAT register values
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*/
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static INLINE uint32_t spifi_HW_GetStat(LPC_SPIFI_T *pSpifi)
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{
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return pSpifi->STAT;
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}
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/**
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* @brief SPIFI controller command register bit definitions
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*/
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#define SPIFI_CMD_DATALEN(l) ((l) << 0) /**< SPIFI bytes to send or receive */
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#define SPIFI_CMD_POLLRS(p) ((p) << 14) /**< SPIFI enable poll */
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#define SPIFI_CMD_DOUT(d) ((d) << 15) /**< SPIFI data direction is out */
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#define SPIFI_CMD_INTER(i) ((i) << 16) /**< SPIFI intermediate bit length */
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#define SPIFI_CMD_FIELDFORM(p) ((p) << 19) /**< SPIFI 2 bit data/cmd mode control */
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#define SPIFI_CMD_FRAMEFORM(f) ((f) << 21) /**< SPIFI op and adr field config */
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#define SPIFI_CMD_OPCODE(o) ((uint32_t) (o) << 24) /**< SPIFI 8-bit command code */
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/**
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* @brief frame form definitions
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*/
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typedef enum {
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SPIFI_FRAMEFORM_OP = 1,
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SPIFI_FRAMEFORM_OP_1ADDRESS = 2,
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SPIFI_FRAMEFORM_OP_2ADDRESS = 3,
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SPIFI_FRAMEFORM_OP_3ADDRESS = 4,
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SPIFI_FRAMEFORM_OP_4ADDRESS = 5,
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SPIFI_FRAMEFORM_NOOP_3ADDRESS = 6,
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SPIFI_FRAMEFORM_NOOP_4ADDRESS = 7
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} SPIFI_FRAMEFORM_T;
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/**
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* @brief serial type definitions
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*/
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typedef enum {
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SPIFI_FIELDFORM_ALL_SERIAL = 0,
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SPIFI_FIELDFORM_SERIAL_OPCODE_ADDRESS = 1,
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SPIFI_FIELDFORM_SERIAL_OPCODE = 2,
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SPIFI_FIELDFORM_NO_SERIAL = 3
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} SPIFI_FIELDFORM_T;
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/**
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* @brief Read SPIFI controller command register
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* @param pSpifi : Base address of SPIFI controller
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* @return 32-bit value read from the command register
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*/
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static INLINE uint32_t spifi_HW_GetCmd(LPC_SPIFI_T *pSpifi)
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{
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return pSpifi->CMD;
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}
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/**
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* @brief Write SPIFI controller command register
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* @param pSpifi : Base address of SPIFI controller
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* @param cmd : Command to write
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* @return Nothing
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*/
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static INLINE void spifi_HW_SetCmd(LPC_SPIFI_T *pSpifi, uint32_t cmd)
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{
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pSpifi->CMD = cmd;
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}
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/**
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* @brief Write SPIFI controller address register
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* @param pSpifi : Base address of SPIFI controller
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* @param addr : address (offset) to write
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* @return Nothing
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*/
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static INLINE void spifi_HW_SetAddr(LPC_SPIFI_T *pSpifi, uint32_t addr)
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{
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pSpifi->ADDR = addr;
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}
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/**
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* @brief Read an 8-bit value from the controller data register
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* @param pSpifi : Base address of SPIFI controller
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* @return 8-bit value read from the data register
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*/
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static INLINE uint8_t spifi_HW_GetData8(LPC_SPIFI_T *pSpifi)
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{
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return pSpifi->DAT8;
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}
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/**
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* @brief Read an 16-bit value from the controller data register
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* @param pSpifi : Base address of SPIFI controller
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* @return 16-bit value read from the data register
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*/
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static INLINE uint16_t spifi_HW_GetData16(LPC_SPIFI_T *pSpifi)
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{
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return pSpifi->DAT16;
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}
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/**
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* @brief Read an 32-bit value from the controller data register
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* @param pSpifi : Base address of SPIFI controller
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* @return 32-bit value read from the data register
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*/
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static INLINE uint32_t spifi_HW_GetData32(LPC_SPIFI_T *pSpifi)
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{
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return pSpifi->DAT32;
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}
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/**
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* @brief Write an 8-bit value from the controller data register
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* @param pSpifi : Base address of SPIFI controller
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* @param data : 8-bit data value to write
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* @return Nothing
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*/
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static INLINE void spifi_HW_SetData8(LPC_SPIFI_T *pSpifi, uint8_t data)
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{
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pSpifi->DAT8 = data;
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}
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/**
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* @brief Write an 16-bit value from the controller data register
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* @param pSpifi : Base address of SPIFI controller
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* @param data : 16-bit data value to write
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* @return Nothing
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*/
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static INLINE void spifi_HW_SetData16(LPC_SPIFI_T *pSpifi, uint16_t data)
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{
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pSpifi->DAT16 = data;
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}
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/**
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* @brief Write an 32-bit value from the controller data register
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* @param pSpifi : Base address of SPIFI controller
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* @param data : 32-bit data value to write
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* @return Nothing
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*/
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static INLINE void spifi_HW_SetData32(LPC_SPIFI_T *pSpifi, uint32_t data)
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{
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pSpifi->DAT32 = data;
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}
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/**
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* @brief Write IDATA register
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* @param pSpifi : Base address of SPIFI controller
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* @param mode : value to write. Used to specify value used for intermediate
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data value when enabled.
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* @return Nothing
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*/
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static INLINE void spifi_HW_SetIDATA(LPC_SPIFI_T *pSpifi, uint32_t mode)
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{
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pSpifi->DATINTM = mode;
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}
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/**
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* @brief Write MEMCMD register
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* @param pSpifi : Base address of SPIFI controller
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* @param cmd : Command value to write
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* @return Nothing
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*/
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static INLINE void spifi_HW_SetMEMCMD(LPC_SPIFI_T *pSpifi, uint32_t cmd)
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{
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pSpifi->MEMCMD = cmd;
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}
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/**
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* @}
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*/
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/** @defgroup LPCSPIFILIB_HW_L2 LPCSPIFILIB hardware support API functions
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* @{
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*/
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/**
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* @brief Reset SPIFI controller
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* @param pSpifi : Base address of SPIFI controller
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* @return Nothing
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*/
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static INLINE void spifi_HW_ResetController(LPC_SPIFI_T *pSpifi)
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{
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pSpifi->STAT = SPIFI_STAT_RESET;
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while ((pSpifi->STAT & SPIFI_STAT_RESET) != 0) {}
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}
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/**
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* @brief Wait for a command to complete
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* @param pSpifi : Base address of SPIFI controller
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* @return Nothing
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*/
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static INLINE void spifi_HW_WaitCMD(LPC_SPIFI_T *pSpifi)
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{
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while ((spifi_HW_GetStat(pSpifi) & SPIFI_STAT_CMD) != 0) {}
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}
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/**
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* @brief Wait for a RESET bit to clear
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* @param pSpifi : Base address of SPIFI controller
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* @return Nothing
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*/
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static INLINE void spifi_HW_WaitRESET(LPC_SPIFI_T *pSpifi)
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{
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while ((spifi_HW_GetStat(pSpifi) & SPIFI_STAT_RESET) != 0) {}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SPIFILIB_CHIPHW_H_ */
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