430 lines
15 KiB
C
430 lines
15 KiB
C
/*
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* @brief LPC18xx/43xx State Configurable Timer (SCT) driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licenser disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __SCT_18XX_43XX_H_
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#define __SCT_18XX_43XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup SCT_18XX_43XX CHIP: LPC18xx/43xx State Configurable Timer driver
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* @ingroup CHIP_18XX_43XX_Drivers
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* @{
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*/
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/*
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* @brief SCT Module configuration
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*/
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#define CONFIG_SCT_nEV (16) /*!< Number of events */
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#define CONFIG_SCT_nRG (16) /*!< Number of match/compare registers */
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#define CONFIG_SCT_nOU (16) /*!< Number of outputs */
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/**
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* @brief State Configurable Timer register block structure
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*/
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typedef struct {
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__IO uint32_t CONFIG; /*!< Configuration Register */
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union {
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__IO uint32_t CTRL_U; /*!< Control Register */
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struct {
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__IO uint16_t CTRL_L; /*!< Low control register */
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__IO uint16_t CTRL_H; /*!< High control register */
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};
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};
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__IO uint16_t LIMIT_L; /*!< limit register for counter L */
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__IO uint16_t LIMIT_H; /*!< limit register for counter H */
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__IO uint16_t HALT_L; /*!< halt register for counter L */
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__IO uint16_t HALT_H; /*!< halt register for counter H */
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__IO uint16_t STOP_L; /*!< stop register for counter L */
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__IO uint16_t STOP_H; /*!< stop register for counter H */
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__IO uint16_t START_L; /*!< start register for counter L */
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__IO uint16_t START_H; /*!< start register for counter H */
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uint32_t RESERVED1[10]; /*!< 0x03C reserved */
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union {
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__IO uint32_t COUNT_U; /*!< counter register */
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struct {
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__IO uint16_t COUNT_L; /*!< counter register for counter L */
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__IO uint16_t COUNT_H; /*!< counter register for counter H */
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};
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};
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__IO uint16_t STATE_L; /*!< state register for counter L */
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__IO uint16_t STATE_H; /*!< state register for counter H */
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__I uint32_t INPUT; /*!< input register */
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__IO uint16_t REGMODE_L; /*!< match - capture registers mode register L */
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__IO uint16_t REGMODE_H; /*!< match - capture registers mode register H */
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__IO uint32_t OUTPUT; /*!< output register */
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__IO uint32_t OUTPUTDIRCTRL; /*!< output counter direction Control Register */
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__IO uint32_t RES; /*!< conflict resolution register */
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__IO uint32_t DMA0REQUEST; /*!< DMA0 Request Register */
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__IO uint32_t DMA1REQUEST; /*!< DMA1 Request Register */
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uint32_t RESERVED2[35];
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__IO uint32_t EVEN; /*!< event enable register */
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__IO uint32_t EVFLAG; /*!< event flag register */
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__IO uint32_t CONEN; /*!< conflict enable register */
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__IO uint32_t CONFLAG; /*!< conflict flag register */
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union {
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__IO union { /*!< ... Match / Capture value */
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uint32_t U; /*!< SCTMATCH[i].U Unified 32-bit register */
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struct {
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uint16_t L; /*!< SCTMATCH[i].L Access to L value */
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uint16_t H; /*!< SCTMATCH[i].H Access to H value */
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};
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} MATCH[CONFIG_SCT_nRG];
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__I union {
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uint32_t U; /*!< SCTCAP[i].U Unified 32-bit register */
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struct {
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uint16_t L; /*!< SCTCAP[i].L Access to L value */
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uint16_t H; /*!< SCTCAP[i].H Access to H value */
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};
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} CAP[CONFIG_SCT_nRG];
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};
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uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /*!< ...-0x17C reserved */
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union {
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__IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /*!< 0x180-... Match Value L counter */
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__I uint16_t CAP_L[CONFIG_SCT_nRG]; /*!< 0x180-... Capture Value L counter */
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};
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uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /*!< ...-0x1BE reserved */
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union {
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__IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Match Value H counter */
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__I uint16_t CAP_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Capture Value H counter */
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};
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uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /*!< ...-0x1FE reserved */
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union {
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__IO union { /*!< 0x200-... Match Reload / Capture Control value */
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uint32_t U; /*!< SCTMATCHREL[i].U Unified 32-bit register */
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struct {
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uint16_t L; /*!< SCTMATCHREL[i].L Access to L value */
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uint16_t H; /*!< SCTMATCHREL[i].H Access to H value */
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};
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} MATCHREL[CONFIG_SCT_nRG];
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__IO union {
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uint32_t U; /*!< SCTCAPCTRL[i].U Unified 32-bit register */
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struct {
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uint16_t L; /*!< SCTCAPCTRL[i].L Access to L value */
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uint16_t H; /*!< SCTCAPCTRL[i].H Access to H value */
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};
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} CAPCTRL[CONFIG_SCT_nRG];
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};
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uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /*!< ...-0x27C reserved */
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union {
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__IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Match Reload value L counter */
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__IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Capture Control value L counter */
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};
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uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /*!< ...-0x2BE reserved */
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union {
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__IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Match Reload value H counter */
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__IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Capture Control value H counter */
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};
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uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /*!< ...-0x2FE reserved */
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__IO struct { /*!< 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
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uint32_t STATE; /*!< Event State Register */
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uint32_t CTRL; /*!< Event Control Register */
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} EVENT[CONFIG_SCT_nEV];
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uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /*!< ...-0x4FC reserved */
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__IO struct { /*!< 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
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uint32_t SET; /*!< Output n Set Register */
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uint32_t CLR; /*!< Output n Clear Register */
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} OUT[CONFIG_SCT_nOU];
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uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /*!< ...-0x7F8 reserved */
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__I uint32_t MODULECONTENT; /*!< 0x7FC Module Content */
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} LPC_SCT_T;
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/*
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* @brief Macro defines for SCT configuration register
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*/
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#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /*!< Operate as 2 16-bit counters */
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#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /*!< Operate as 1 32-bit counter */
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#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /*!< Bus clock */
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#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /*!< SCT clock */
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#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /*!< Input clock selected in CLKSEL field */
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#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /*!< Input clock edge selected in CLKSEL field */
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#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /*!< Operate as 1 32-bit counter */
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#define SCT_CONFIG_NORELOADH (0x1 << 8) /*!< Operate as 1 32-bit counter */
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#define SCT_CONFIG_AUTOLIMIT_L (0x1 << 17) /*!< Limits counter(L) based on MATCH0 */
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#define SCT_CONFIG_AUTOLIMIT_H (0x1 << 18) /*!< Limits counter(L) based on MATCH0 */
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/*
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* @brief Macro defines for SCT control register
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*/
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#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for low or unified counter */
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#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
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#define SCT_CTRL_STOP_L (1 << 1) /*!< Stop low counter */
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#define SCT_CTRL_HALT_L (1 << 2) /*!< Halt low counter */
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#define SCT_CTRL_CLRCTR_L (1 << 3) /*!< Clear low or unified counter */
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#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /*!< Bidirectional bit */
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#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /*!< Prescale clock for low or unified counter */
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#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for high counter */
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#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
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#define SCT_CTRL_STOP_H (1 << 17) /*!< Stop high counter */
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#define SCT_CTRL_HALT_H (1 << 18) /*!< Halt high counter */
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#define SCT_CTRL_CLRCTR_H (1 << 19) /*!< Clear high counter */
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#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
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#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /*!< Prescale clock for high counter */
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/*
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* @brief Macro defines for SCT Conflict resolution register
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*/
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#define SCT_RES_NOCHANGE (0)
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#define SCT_RES_SET_OUTPUT (1)
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#define SCT_RES_CLEAR_OUTPUT (2)
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#define SCT_RES_TOGGLE_OUTPUT (3)
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/**
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* SCT Match register values enum
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*/
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typedef enum CHIP_SCT_MATCH_REG {
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SCT_MATCH_0 = 0, /*!< SCT Match register 0 */
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SCT_MATCH_1 = 1, /*!< SCT Match register 1 */
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SCT_MATCH_2 = 2, /*!< SCT Match register 2 */
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SCT_MATCH_3 = 3, /*!< SCT Match register 3 */
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SCT_MATCH_4 = 4 /*!< SCT Match register 4 */
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} CHIP_SCT_MATCH_REG_T;
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/**
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* SCT Event values enum
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*/
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typedef enum CHIP_SCT_EVENT {
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SCT_EVT_0 = (1 << 0), /*!< Event 0 */
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SCT_EVT_1 = (1 << 1), /*!< Event 1 */
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SCT_EVT_2 = (1 << 2), /*!< Event 2 */
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SCT_EVT_3 = (1 << 3), /*!< Event 3 */
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SCT_EVT_4 = (1 << 4) /*!< Event 4 */
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} CHIP_SCT_EVENT_T;
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/**
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* @brief Configures the State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param value : The 32-bit CONFIG register value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_Config(LPC_SCT_T *pSCT, uint32_t value)
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{
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pSCT->CONFIG = value;
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}
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/**
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* @brief Set or Clear the Control register
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* @param pSCT : Pointer to SCT register block
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* @param value : SCT Control register value
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* @param ena : ENABLE - To set the fields specified by value
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* : DISABLE - To clear the field specified by value
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* @return Nothing
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* Set or clear the control register bits as specified by the \a value
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* parameter. If \a ena is set to ENABLE, the mentioned register fields
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* will be set. If \a ena is set to DISABLE, the mentioned register
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* fields will be cleared
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*/
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void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena);
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/**
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* @brief Set the conflict resolution
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* @param pSCT : Pointer to SCT register block
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* @param outnum : Output number
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* @param value : Output value
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* - SCT_RES_NOCHANGE :No change
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* - SCT_RES_SET_OUTPUT :Set output
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* - SCT_RES_CLEAR_OUTPUT :Clear output
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* - SCT_RES_TOGGLE_OUTPUT :Toggle output
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* : SCT_RES_NOCHANGE
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* : DISABLE - To clear the field specified by value
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* @return Nothing
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* Set conflict resolution for the output \a outnum
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*/
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void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value);
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/**
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* @brief Set unified count value in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param count : The 32-bit count value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_SetCount(LPC_SCT_T *pSCT, uint32_t count)
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{
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pSCT->COUNT_U = count;
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}
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/**
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* @brief Set lower count value in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param count : The 16-bit count value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_SetCountL(LPC_SCT_T *pSCT, uint16_t count)
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{
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pSCT->COUNT_L = count;
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}
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/**
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* @brief Set higher count value in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param count : The 16-bit count value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_SetCountH(LPC_SCT_T *pSCT, uint16_t count)
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{
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pSCT->COUNT_H = count;
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}
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/**
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* @brief Set unified match count value in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param n : Match register value
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* @param value : The 32-bit match count value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_SetMatchCount(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value)
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{
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pSCT->MATCH[n].U = value;
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}
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/**
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* @brief Set control register in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param value : Value (ORed value of SCT_CTRL_* bits)
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_SetControl(LPC_SCT_T *pSCT, uint32_t value)
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{
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pSCT->CTRL_U |= value;
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}
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/**
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* @brief Clear control register in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param value : Value (ORed value of SCT_CTRL_* bits)
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_ClearControl(LPC_SCT_T *pSCT, uint32_t value)
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{
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pSCT->CTRL_U &= ~(value);
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}
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/**
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* @brief Set unified match reload count value in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param n : Match register value
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* @param value : The 32-bit match count reload value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_SetMatchReload(LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value)
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{
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pSCT->MATCHREL[n].U = value;
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}
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/**
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* @brief Enable the interrupt for the specified event in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param evt : Event value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_EnableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt)
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{
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pSCT->EVEN |= evt;
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}
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/**
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* @brief Disable the interrupt for the specified event in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param evt : Event value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_DisableEventInt(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt)
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{
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pSCT->EVEN &= ~(evt);
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}
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/**
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* @brief Clear the specified event flag in State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @param evt : Event value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SCT_ClearEventFlag(LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt)
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{
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pSCT->EVFLAG |= evt;
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}
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/**
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* @brief Initializes the State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @return Nothing
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*/
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void Chip_SCT_Init(LPC_SCT_T *pSCT);
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/**
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* @brief Deinitializes the State Configurable Timer
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* @param pSCT : The base of SCT peripheral on the chip
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* @return Nothing
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*/
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void Chip_SCT_DeInit(LPC_SCT_T *pSCT);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SCT_18XX_43XX_H_ */
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