582 lines
24 KiB
C
582 lines
24 KiB
C
/*
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* @brief LPC18xx/43xx High speed ADC driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __HSADC_18XX_43XX_H_
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#define __HSADC_18XX_43XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup HSADC_18XX_43XX CHIP: LPC18xx/43xx High speed ADC driver
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* @ingroup CHIP_18XX_43XX_Drivers
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* @{
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*/
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/**
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* @brief High speed ADC interrupt control structure
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*/
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typedef struct {
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__O uint32_t CLR_EN; /*!< Interrupt clear mask */
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__O uint32_t SET_EN; /*!< Interrupt set mask */
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__I uint32_t MASK; /*!< Interrupt mask */
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__I uint32_t STATUS; /*!< Interrupt status */
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__O uint32_t CLR_STAT; /*!< Interrupt clear status */
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__O uint32_t SET_STAT; /*!< Interrupt set status */
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uint32_t RESERVED[2];
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} HSADCINTCTRL_T;
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/**
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* @brief HSADC register block structure
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*/
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typedef struct { /*!< HSADC Structure */
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__O uint32_t FLUSH; /*!< Flushes FIFO */
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__IO uint32_t DMA_REQ; /*!< Set or clear DMA write request */
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__I uint32_t FIFO_STS; /*!< Indicates FIFO fill level status */
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__IO uint32_t FIFO_CFG; /*!< Configures FIFO fill level */
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__O uint32_t TRIGGER; /*!< Enable software trigger to start descriptor processing */
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__IO uint32_t DSCR_STS; /*!< Indicates active descriptor table and descriptor entry */
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__IO uint32_t POWER_DOWN; /*!< Set or clear power down mode */
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__IO uint32_t CONFIG; /*!< Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down */
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__IO uint32_t THR[2]; /*!< Configures window comparator A or B levels */
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__I uint32_t LAST_SAMPLE[6]; /*!< Contains last converted sample of input M [M=0..5) and result of window comparator */
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uint32_t RESERVED0[49];
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__IO uint32_t ADC_SPEED; /*!< ADC speed control */
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__IO uint32_t POWER_CONTROL; /*!< Configures ADC power vs. speed, DC-in biasing, output format and power gating */
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uint32_t RESERVED1[61];
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__I uint32_t FIFO_OUTPUT[16]; /*!< FIFO output mapped to 16 consecutive address locations */
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uint32_t RESERVED2[48];
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__IO uint32_t DESCRIPTOR[2][8]; /*!< Table 0 and 1 descriptors */
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uint32_t RESERVED3[752];
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HSADCINTCTRL_T INTS[2]; /*!< Interrupt 0 and 1 control and status registers */
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} LPC_HSADC_T;
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#define HSADC_MAX_SAMPLEVAL 0xFFF
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/**
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* @brief Initialize the High speed ADC
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return Nothing
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*/
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void Chip_HSADC_Init(LPC_HSADC_T *pHSADC);
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/**
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* @brief Shutdown HSADC
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return Nothing
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*/
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void Chip_HSADC_DeInit(LPC_HSADC_T *pHSADC);
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/**
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* @brief Flush High speed ADC FIFO
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return Nothing
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*/
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STATIC INLINE void Chip_HSADC_FlushFIFO(LPC_HSADC_T *pHSADC)
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{
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pHSADC->FLUSH = 1;
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}
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/**
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* @brief Load a descriptor table from memory by requesting a DMA write
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return Nothing
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* @note WHat is this used for?
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*/
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STATIC INLINE void Chip_HSADC_LoadDMADesc(LPC_HSADC_T *pHSADC)
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{
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pHSADC->DMA_REQ = 1;
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}
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/**
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* @brief Returns current HSADC FIFO fill level
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return FIFO level, 0 for empty, 1 to 15, or 16 for full
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* @note WHat is this used for?
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*/
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STATIC INLINE uint32_t Chip_HSADC_GetFIFOLevel(LPC_HSADC_T *pHSADC)
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{
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return pHSADC->FIFO_STS;
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}
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/**
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* @brief Sets up HSADC FIFO trip level and packing
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @param trip : HSADC FIFO trip point (1 to 15 samples)
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* @param packed : true to pack samples, false for no packing
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* @return Nothing
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* @note The FIFO trip point is used for the DMA or interrupt level.
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* Sample packging allows packing 2 samples into a single 32-bit
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* word.
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*/
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void Chip_HSADC_SetupFIFO(LPC_HSADC_T *pHSADC, uint8_t trip, bool packed);
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/**
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* @brief Starts a manual (software) trigger of HSADC descriptors
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return Nothing
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*/
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STATIC INLINE void Chip_HSADC_SWTrigger(LPC_HSADC_T *pHSADC)
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{
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pHSADC->TRIGGER = 1;
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}
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/**
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* @brief Set active table descriptor index and number
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @param table : Table index, 0 or 1
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* @param desc : Descriptor index, 0 to 7
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* @return Nothing
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* @note This function can be used to set active descriptor table and
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* active descriptor entry values. The new values will be updated
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* immediately. This should only be updated when descriptors are
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* not running (halted).
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*/
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STATIC INLINE void Chip_HSADC_SetActiveDescriptor(LPC_HSADC_T *pHSADC, uint8_t table, uint8_t desc)
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{
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pHSADC->DSCR_STS = (uint32_t) ((desc << 1) | table);
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}
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/**
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* @brief Returns currently active descriptor index being processed
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return the current active descriptor index, 0 to 7
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*/
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STATIC INLINE uint8_t Chip_HSADC_GetActiveDescriptorIndex(LPC_HSADC_T *pHSADC)
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{
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return (uint8_t) ((pHSADC->DSCR_STS >> 1) & 0x7);
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}
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/**
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* @brief Returns currently active descriptor table being processed
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return the current active descriptor table, 0 or 1
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*/
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STATIC INLINE uint8_t Chip_HSADC_GetActiveDescriptorTable(LPC_HSADC_T *pHSADC)
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{
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return (uint8_t) (pHSADC->DSCR_STS & 1);
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}
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/**
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* @brief Enables ADC power down mode
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return Nothing
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* @note In most cases, this function doesn't need to be used as
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* the descriptors control power as needed.
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*/
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STATIC INLINE void Chip_HSADC_EnablePowerDownMode(LPC_HSADC_T *pHSADC)
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{
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pHSADC->POWER_DOWN = 1;
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}
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/**
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* @brief Disables ADC power down mode
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @return Nothing
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* @note In most cases, this function doesn't need to be used as
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* the descriptors control power as needed.
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*/
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STATIC INLINE void Chip_HSADC_DisablePowerDownMode(LPC_HSADC_T *pHSADC)
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{
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pHSADC->POWER_DOWN = 0;
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}
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/* HSADC trigger configuration mask types */
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typedef enum {
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HSADC_CONFIG_TRIGGER_OFF = 0, /*!< ADCHS triggers off */
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HSADC_CONFIG_TRIGGER_SW = 1, /*!< ADCHS software trigger only */
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HSADC_CONFIG_TRIGGER_EXT = 2, /*!< ADCHS external trigger only */
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HSADC_CONFIG_TRIGGER_BOTH = 3 /*!< ADCHS both software and external triggers allowed */
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} HSADC_TRIGGER_MASK_T;
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/* HSADC trigger configuration mode types */
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typedef enum {
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HSADC_CONFIG_TRIGGER_RISEEXT = (0 << 2), /*!< ADCHS rising external trigger */
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HSADC_CONFIG_TRIGGER_FALLEXT = (1 << 2), /*!< ADCHS falling external trigger */
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HSADC_CONFIG_TRIGGER_LOWEXT = (2 << 2), /*!< ADCHS low external trigger */
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HSADC_CONFIG_TRIGGER_HIGHEXT = (3 << 2) /*!< ADCHS high external trigger */
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} HSADC_TRIGGER_MODE_T;
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/* HSADC trigger configuration sync types */
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typedef enum {
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HSADC_CONFIG_TRIGGER_NOEXTSYNC = (0 << 4), /*!< do not synchronize external trigger input */
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HSADC_CONFIG_TRIGGER_EXTSYNC = (1 << 4), /*!< synchronize external trigger input */
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} HSADC_TRIGGER_SYNC_T;
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/* HSADC trigger configuration channel ID */
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typedef enum {
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HSADC_CHANNEL_ID_EN_NONE = (0 << 5), /*!< do not add channel ID to FIFO output data */
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HSADC_CHANNEL_ID_EN_ADD = (1 << 5), /*!< add channel ID to FIFO output data */
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} HSADC_CHANNEL_ID_EN_T;
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/**
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* @brief Configure HSADC trigger source and recovery time
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @param mask : HSADC trigger configuration mask type
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* @param mode : HSADC trigger configuration mode type
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* @param sync : HSADC trigger configuration sync type
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* @param chID : HSADC trigger configuration channel ID enable
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* @param recoveryTime : ADC recovery time (in HSADC clocks) from powerdown (255 max)
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* @return Nothing
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*/
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STATIC INLINE void Chip_HSADC_ConfigureTrigger(LPC_HSADC_T *pHSADC,
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HSADC_TRIGGER_MASK_T mask,
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HSADC_TRIGGER_MODE_T mode,
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HSADC_TRIGGER_SYNC_T sync,
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HSADC_CHANNEL_ID_EN_T chID, uint16_t recoveryTime)
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{
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pHSADC->CONFIG = (uint32_t) mask | (uint32_t) mode | (uint32_t) sync |
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(uint32_t) chID | (uint32_t) (recoveryTime << 6);
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}
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/**
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* @brief Set HSADC Threshold low value
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @param thrnum : Threshold register value (0 for threshold register A, 1 for threshold register B)
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* @param value : Threshold low data value (should be 12-bit value)
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* @return None
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*/
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void Chip_HSADC_SetThrLowValue(LPC_HSADC_T *pHSADC, uint8_t thrnum, uint16_t value);
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/**
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* @brief Set HSADC Threshold high value
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* @param pHSADC : The base of HSADC peripheral on the chip
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* @param thrnum : Threshold register value (0 for threshold register A, 1 for threshold register B)
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* @param value : Threshold high data value (should be 12-bit value)
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* @return None
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*/
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void Chip_HSADC_SetThrHighValue(LPC_HSADC_T *pHSADC, uint8_t thrnum, uint16_t value);
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/** HSADC last sample registers bit fields */
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#define HSADC_LS_DONE (1 << 0) /*!< Sample conversion complete bit */
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#define HSADC_LS_OVERRUN (1 << 1) /*!< Sample overrun bit */
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#define HSADC_LS_RANGE_IN (0 << 2) /*!< Threshold range comparison is in range */
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#define HSADC_LS_RANGE_BELOW (1 << 2) /*!< Threshold range comparison is below range */
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#define HSADC_LS_RANGE_ABOVE (2 << 2) /*!< Threshold range comparison is above range */
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#define HSADC_LS_RANGE(val) ((val) & 0xC) /*!< Mask for threshold crossing comparison result */
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#define HSADC_LS_CROSSING_NONE (0 << 4) /*!< No threshold crossing detected */
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#define HSADC_LS_CROSSING_DOWN (1 << 4) /*!< Downward threshold crossing detected */
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#define HSADC_LS_CROSSING_UP (2 << 4) /*!< Upward threshold crossing detected */
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#define HSADC_LS_CROSSING(val) ((val) & 0x30) /*!< Mask for threshold crossing comparison result */
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#define HSADC_LS_DATA(val) ((val) >> 6) /*!< Mask data value out of sample */
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/**
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* @brief Read a ADC last sample register
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param channel : Last sample register to read, 0-5
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* @return Current raw value of the indexed last sample register
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* @note This function returns the raw value of the indexed last sample register
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* and clears the sample's DONE and OVERRUN statuses if set. You can determine
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* the overrun and datavalid status for the sample by masking the return value
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* with HSADC_LS_DONE or HSADC_LS_OVERRUN. To get the data value for the sample,
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* use the HSADC_LS_DATA(sample) macro. The threshold range and crossing results
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* can be determined by using the HSADC_LS_RANGE(sample) and
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* HSADC_LS_CROSSING(sample) macros and comparing the result against the
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* HSADC_LS_RANGE_* or HSADC_LS_CROSSING_* definitions.<br>
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*/
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STATIC INLINE uint32_t Chip_HSADC_GetLastSample(LPC_HSADC_T *pHSADC, uint8_t channel)
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{
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return pHSADC->LAST_SAMPLE[channel];
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}
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/**
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* @brief Setup speed for a input channel
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param channel : Input to set, 0-5
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* @param speed : Speed value to set (0xF, 0xE, or 0x0), see user manual
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* @return Nothing
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* @note It is recommended not to use this function, as the values needed
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* for this register will be setup with the Chip_HSADC_SetPowerSpeed() function.
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*/
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void Chip_HSADC_SetSpeed(LPC_HSADC_T *pHSADC, uint8_t channel, uint8_t speed);
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/**
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* @brief Setup (common) HSADC power and speed settings
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param comp2 : True sets up for 2's complement, false sets up for offset binary data format
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* @return Nothing
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* @note This function sets up the HSADC current/power/speed settings that
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* apply to all HSADC channels (inputs). Based on the HSADC clock rate, it will
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* automatically setup the best current setting (CRS) and speed settings (DGEC)
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* for all channels. (See user manual).<br>
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* This function is also used to set the data format of the sampled data. It is
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* recommended to call this function if the HSADC sample rate changes.
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*/
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void Chip_HSADC_SetPowerSpeed(LPC_HSADC_T *pHSADC, bool comp2);
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/* AC-DC coupling selection for vin_neg and vin_pos sides */
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typedef enum {
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HSADC_CHANNEL_NODCBIAS = 0, /*!< No DC bias */
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HSADC_CHANNEL_DCBIAS = 1, /*!< DC bias on vin_neg side */
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} HSADC_DCBIAS_T;
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/**
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* @brief Setup AC-DC coupling selection for a channel
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param channel : Input to set, 0-5
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* @param dcInNeg : AC-DC coupling selection on vin_neg side
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* @param dcInPos : AC-DC coupling selection on vin_pos side
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* @return Nothing
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* @note This function sets up the HSADC current/power/speed settings that
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* apply to all HSADC channels (inputs). Based on the HSADC clock rate, it will
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* automatically setup the best current setting (CRS) and speed settings (DGEC)
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* for all channels. (See user manual).<br>
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* This function is also used to set the data format of the sampled data. It is
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* recommended to call this function if the HSADC sample rate changes.
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*/
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void Chip_HSADC_SetACDCBias(LPC_HSADC_T *pHSADC, uint8_t channel,
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HSADC_DCBIAS_T dcInNeg, HSADC_DCBIAS_T dcInPos);
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/**
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* @brief Enable HSADC power control and band gap reference
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* @param pHSADC : The base of ADC peripheral on the chip
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* @return Nothing
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* @note This function enables both the HSADC power and band gap
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* reference.
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*/
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STATIC INLINE void Chip_HSADC_EnablePower(LPC_HSADC_T *pHSADC)
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{
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pHSADC->POWER_CONTROL |= (1 << 17) | (1 << 18);
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}
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/**
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* @brief Disable HSADC power control and band gap reference
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* @param pHSADC : The base of ADC peripheral on the chip
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* @return Nothing
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* @note This function disables both the HSADC power and band gap
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* reference.
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*/
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STATIC INLINE void Chip_HSADC_DisablePower(LPC_HSADC_T *pHSADC)
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{
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pHSADC->POWER_CONTROL &= ~((1 << 17) | (1 << 18));
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}
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/** HSADC FIFO registers bit fields for unpacked sample in lower 16 bits */
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#define HSADC_FIFO_SAMPLE_MASK (0xFFF) /*!< 12-bit sample mask (unpacked) */
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#define HSADC_FIFO_SAMPLE(val) ((val) & 0xFFF) /*!< Macro for stripping out unpacked sample data */
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#define HSADC_FIFO_CHAN_ID_MASK (0x7000) /*!< Channel ID mask */
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#define HSADC_FIFO_CHAN_ID(val) (((val) >> 12) & 0x7) /*!< Macro for stripping out sample data */
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#define HSADC_FIFO_EMPTY (0x1 << 15) /*!< FIFO empty (invalid sample) */
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#define HSADC_FIFO_SHIFTPACKED(val) ((val) >> 16) /*!< Shifts the packed FIFO sample into the lower 16-bits of a word */
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#define HSADC_FIFO_PACKEDMASK (1UL << 31) /*!< Packed sample check mask */
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/**
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* @brief Reads the HSADC FIFO
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* @param pHSADC : The base of ADC peripheral on the chip
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* @return HSADC FIFO value
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* @note This function reads and pops the HSADC FIFO. The FIFO
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* contents can be determined by using the HSADC_FIFO_* macros. If
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* FIFO packing is enabled, this may contain 2 samples. Use the
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* HSADC_FIFO_SHIFTPACKED macro to shift packed sample data into a
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* variable that can be used with the HSADC_FIFO_* macros. Note that
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* even if packing is enabled, the packed sample may not be valid.
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*/
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STATIC INLINE uint32_t Chip_HSADC_GetFIFO(LPC_HSADC_T *pHSADC)
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{
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return pHSADC->FIFO_OUTPUT[0];
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}
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/** HSADC descriptor registers bit fields and support macros */
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#define HSADC_DESC_CH(ch) (ch) /*!< Converter input channel */
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#define HSADC_DESC_HALT (1 << 3) /*!< Descriptor halt after conversion bit */
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#define HSADC_DESC_INT (1 << 4) /*!< Raise interrupt when ADC result is available bit */
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#define HSADC_DESC_POWERDOWN (1 << 5) /*!< Power down after this conversion bit */
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#define HSADC_DESC_BRANCH_NEXT (0 << 6) /*!< Continue with next descriptor */
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#define HSADC_DESC_BRANCH_FIRST (1 << 6) /*!< Branch to the first descriptor */
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#define HSADC_DESC_BRANCH_SWAP (2 << 6) /*!< Swap tables and branch to the first descriptor of the new table */
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#define HSADC_DESC_MATCH(val) ((val) << 8) /*!< Match value used to trigger a descriptor */
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#define HSADC_DESC_THRESH_NONE (0 << 22) /*!< No threshold detection performed */
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#define HSADC_DESC_THRESH_A (1 << 22) /*!< Use A threshold detection */
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#define HSADC_DESC_THRESH_B (2 << 22) /*!< Use B threshold detection */
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#define HSADC_DESC_RESET_TIMER (1 << 24) /*!< Reset descriptor timer */
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#define HSADC_DESC_UPDATE_TABLE (1UL << 31) /*!< Update table with all 8 descriptors of this table */
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/**
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* @brief Sets up a raw HSADC descriptor entry
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param table : Descriptor table number, 0 or 1
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* @param descNo : Descriptor number to setup, 0 to 7
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* @param desc : Raw descriptor value (see notes)
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* @return Nothing
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* @note This function sets up a descriptor table entry. To setup
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* a descriptor entry, select a OR'ed combination of the HSADC_DESC_CH,
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* HSADC_DESC_HALT, HSADC_DESC_INT, HSADC_DESC_POWERDOWN, one of
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* HSADC_DESC_BRANCH_*, HSADC_DESC_MATCH, one of HSADC_DESC_THRESH_*, and
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* HSADC_DESC_RESET_TIMER definitions.<br>
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* Example for setting up a table 0, descriptor number 4 entry for input 0:<br>
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* Chip_HSADC_SetupDescEntry(LPC_HSADC, 0, 4, (HSADC_DESC_CH(0) | HSADC_DESC_HALT |
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* HSADC_DESC_INT));
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*/
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STATIC INLINE void Chip_HSADC_SetupDescEntry(LPC_HSADC_T *pHSADC, uint8_t table,
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uint8_t descNo, uint32_t desc)
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{
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pHSADC->DESCRIPTOR[table][descNo] = desc;
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}
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/**
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* @brief Update all descriptors of a table
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param table : Descriptor table number, 0 or 1
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* @return Nothing
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* @note Updates descriptor table with all 8 descriptors. This
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* function should be used after all descriptors are setup with
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* the Chip_HSADC_SetupDescEntry() function.
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*/
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STATIC INLINE void Chip_HSADC_UpdateDescTable(LPC_HSADC_T *pHSADC, uint8_t table)
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{
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pHSADC->DESCRIPTOR[table][0] |= HSADC_DESC_UPDATE_TABLE;
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}
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/* Interrupt selection for interrupt 0 set - these interrupts and statuses
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should only be used with the interrupt 0 register set */
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#define HSADC_INT0_FIFO_FULL (1 << 0) /*!< number of samples in FIFO is more than FIFO_LEVEL */
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#define HSADC_INT0_FIFO_EMPTY (1 << 1) /*!< FIFO is empty */
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#define HSADC_INT0_FIFO_OVERFLOW (1 << 2) /*!< FIFO was full; conversion sample is not stored and lost */
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#define HSADC_INT0_DSCR_DONE (1 << 3) /*!< The descriptor INTERRUPT field was enabled and its sample is converted */
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#define HSADC_INT0_DSCR_ERROR (1 << 4) /*!< The ADC was not fully woken up when a sample was converted and the conversion results is unreliable */
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#define HSADC_INT0_ADC_OVF (1 << 5) /*!< Converted sample value was over range of the 12 bit output code */
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#define HSADC_INT0_ADC_UNF (1 << 6) /*!< Converted sample value was under range of the 12 bit output code */
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/* Interrupt selection for interrupt 1 set - these interrupts and statuses
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should only be used with the interrupt 1 register set */
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#define HSADC_INT1_THCMP_BRANGE(ch) (1 << ((ch * 5) + 0)) /*!< Input channel result below range */
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#define HSADC_INT1_THCMP_ARANGE(ch) (1 << ((ch * 5) + 1)) /*!< Input channel result above range */
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#define HSADC_INT1_THCMP_DCROSS(ch) (1 << ((ch * 5) + 2)) /*!< Input channel result downward threshold crossing detected */
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#define HSADC_INT1_THCMP_UCROSS(ch) (1 << ((ch * 5) + 3)) /*!< Input channel result upward threshold crossing detected */
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#define HSADC_INT1_OVERRUN(ch) (1 << ((ch * 5) + 4)) /*!< New conversion on channel completed and has overwritten the previous contents of register LAST_SAMPLE [0] before it has been read */
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/**
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* @brief Enable an interrupt for HSADC interrupt group 0 or 1
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param intGrp : Interrupt group 0 or 1
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* @param intMask : Interrupts to enable, use HSADC_INT0_* for group 0
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* and HSADC_INT1_* values for group 1
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* @return Nothing
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*/
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STATIC INLINE void Chip_HSADC_EnableInts(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t intMask)
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{
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pHSADC->INTS[intGrp].SET_EN = intMask;
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}
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/**
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* @brief Disables an interrupt for HSADC interrupt group 0 or 1
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param intGrp : Interrupt group 0 or 1
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* @param intMask : Interrupts to disable, use HSADC_INT0_* for group 0
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* and HSADC_INT1_* values for group 1
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* @return Nothing
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*/
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STATIC INLINE void Chip_HSADC_DisableInts(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t intMask)
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{
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pHSADC->INTS[intGrp].CLR_EN = intMask;
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}
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/**
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* @brief Returns enabled interrupt for HSADC interrupt group 0 or 1
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param intGrp : Interrupt group 0 or 1
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* @return enabled interrupts for the selected group
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* @note Mask the return value with a HSADC_INT0_* macro for group 0
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* or HSADC_INT1_* values for group 1 to determine which interrupts are enabled.
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*/
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STATIC INLINE uint32_t Chip_HSADC_GetEnabledInts(LPC_HSADC_T *pHSADC, uint8_t intGrp)
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{
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return pHSADC->INTS[intGrp].MASK;
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}
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/**
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* @brief Returns status for HSADC interrupt group 0 or 1
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* @param pHSADC : The base of ADC peripheral on the chip
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* @param intGrp : Interrupt group 0 or 1
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* @return interrupt (pending) status for the selected group
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* @note Mask the return value with a HSADC_INT0_* macro for group 0
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* or HSADC_INT1_* values for group 1 to determine which statuses are active.
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*/
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STATIC INLINE uint32_t Chip_HSADC_GetIntStatus(LPC_HSADC_T *pHSADC, uint8_t intGrp)
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{
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return pHSADC->INTS[intGrp].STATUS;
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}
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/**
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|
* @brief Clear a status for HSADC interrupt group 0 or 1
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* @param pHSADC : The base of ADC peripheral on the chip
|
|
* @param intGrp : Interrupt group 0 or 1
|
|
* @param stsMask : Statuses to clear, use HSADC_INT0_* for group 0
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|
* and HSADC_INT1_* values for group 1
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* @return Nothing
|
|
*/
|
|
STATIC INLINE void Chip_HSADC_ClearIntStatus(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t stsMask)
|
|
{
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|
pHSADC->INTS[intGrp].CLR_STAT = stsMask;
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|
}
|
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|
|
/**
|
|
* @brief Sets a status for HSADC interrupt group 0 or 1
|
|
* @param pHSADC : The base of ADC peripheral on the chip
|
|
* @param intGrp : Interrupt group 0 or 1
|
|
* @param stsMask : Statuses to set, use HSADC_INT0_* for group 0
|
|
* and HSADC_INT1_* values for group 1
|
|
* @return Nothing
|
|
*/
|
|
STATIC INLINE void Chip_HSADC_SetIntStatus(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t stsMask)
|
|
{
|
|
pHSADC->INTS[intGrp].SET_STAT = stsMask;
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|
}
|
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|
|
/**
|
|
* @brief Returns the clock rate in Hz for the HSADC
|
|
* @param pHSADC : The base of HSADC peripheral on the chip
|
|
* @return clock rate in Hz for the HSADC
|
|
*/
|
|
STATIC INLINE uint32_t Chip_HSADC_GetBaseClockRate(LPC_HSADC_T *pHSADC)
|
|
{
|
|
(void) pHSADC;
|
|
|
|
/* Return computed sample rate for the high speed ADC peripheral */
|
|
return Chip_Clock_GetRate(CLK_ADCHS);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
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|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
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|
|
#endif /* __HSADC_18XX_43XX_H_ */
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