245 lines
8.1 KiB
C
245 lines
8.1 KiB
C
/*
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* @brief LPC18XX/43XX CREG control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CREG_18XX_43XX_H_
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#define __CREG_18XX_43XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver
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* @ingroup CHIP_18XX_43XX_Drivers
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* @{
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*/
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/**
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* @brief CREG Register Block
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*/
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typedef struct { /*!< CREG Structure */
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__I uint32_t RESERVED0;
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__IO uint32_t CREG0; /*!< Chip configuration register 32 kHz oscillator output and BOD control register. */
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__I uint32_t RESERVED1[62];
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__IO uint32_t MXMEMMAP; /*!< ARM Cortex-M3/M4 memory mapping */
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#if defined(CHIP_LPC18XX)
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__I uint32_t RESERVED2[5];
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#else
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__I uint32_t RESERVED2;
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__I uint32_t CREG1; /*!< Configuration Register 1 */
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__I uint32_t CREG2; /*!< Configuration Register 2 */
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__I uint32_t CREG3; /*!< Configuration Register 3 */
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__I uint32_t CREG4; /*!< Configuration Register 4 */
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#endif
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__IO uint32_t CREG5; /*!< Chip configuration register 5. Controls JTAG access. */
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__IO uint32_t DMAMUX; /*!< DMA muxing control */
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__IO uint32_t FLASHCFGA; /*!< Flash accelerator configuration register for flash bank A */
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__IO uint32_t FLASHCFGB; /*!< Flash accelerator configuration register for flash bank B */
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__IO uint32_t ETBCFG; /*!< ETB RAM configuration */
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__IO uint32_t CREG6; /*!< Chip configuration register 6. */
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#if defined(CHIP_LPC18XX)
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__I uint32_t RESERVED4[52];
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#else
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__IO uint32_t M4TXEVENT; /*!< M4 IPC event register */
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__I uint32_t RESERVED4[51];
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#endif
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__I uint32_t CHIPID; /*!< Part ID */
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#if defined(CHIP_LPC18XX)
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__I uint32_t RESERVED5[191];
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#else
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__I uint32_t RESERVED5[65];
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__IO uint32_t M0SUBMEMMAP; /*!< M0SUB IPC Event memory mapping */
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__I uint32_t RESERVED6[2];
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__IO uint32_t M0SUBTXEVENT; /*!< M0SUB IPC Event register */
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__I uint32_t RESERVED7[58];
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__IO uint32_t M0APPTXEVENT; /*!< M0APP IPC Event register */
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__IO uint32_t M0APPMEMMAP; /*!< ARM Cortex M0APP memory mapping */
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__I uint32_t RESERVED8[62];
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#endif
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__IO uint32_t USB0FLADJ; /*!< USB0 frame length adjust register */
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__I uint32_t RESERVED9[63];
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__IO uint32_t USB1FLADJ; /*!< USB1 frame length adjust register */
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} LPC_CREG_T;
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/**
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* @brief Identifies whether on-chip flash is present
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* @return true if on chip flash is available, otherwise false
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*/
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STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void)
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{
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return LPC_CREG->CHIPID != 0x3284E02B;
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}
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/**
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* @brief Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts.
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* @param Hz : Current frequency in Hz of the CPU
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* @return Nothing
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* This function should be called with the higher frequency before the clock frequency is
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* increased and it should be called with the new lower value after the clock frequency is
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* decreased.
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*/
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STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz)
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{
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uint32_t FAValue = Hz / 21510000;
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LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
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LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
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}
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/**
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* @brief FLASH Access time definitions
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*/
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typedef enum {
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FLASHTIM_20MHZ_CPU = 0, /*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock */
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FLASHTIM_40MHZ_CPU = 1, /*!< Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock */
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FLASHTIM_60MHZ_CPU = 2, /*!< Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock */
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FLASHTIM_80MHZ_CPU = 3, /*!< Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock */
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FLASHTIM_100MHZ_CPU = 4, /*!< Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock */
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FLASHTIM_120MHZ_CPU = 5, /*!< Flash accesses use 6 CPU clocks. Use for up to 120 MHz CPU clock */
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FLASHTIM_150MHZ_CPU = 6, /*!< Flash accesses use 7 CPU clocks. Use for up to 150 Mhz CPU clock */
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FLASHTIM_170MHZ_CPU = 7, /*!< Flash accesses use 8 CPU clocks. Use for up to 170 MHz CPU clock */
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FLASHTIM_190MHZ_CPU = 8, /*!< Flash accesses use 9 CPU clocks. Use for up to 190 MHz CPU clock */
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FLASHTIM_SAFE_SETTING = 9, /*!< Flash accesses use 10 CPU clocks. Safe setting for any allowed conditions */
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} CREG_FLASHTIM_T;
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/**
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* @brief Set FLASH memory access time in clocks
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* @param clks : FLASH access speed rating
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* @return Nothing
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*/
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STATIC INLINE void Chip_CREG_SetFLASHAccess(CREG_FLASHTIM_T clks)
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{
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uint32_t tmpA, tmpB;
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/* Don't alter lower bits */
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tmpA = LPC_CREG->FLASHCFGA & ~(0xF << 12);
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LPC_CREG->FLASHCFGA = tmpA | ((uint32_t) clks << 12);
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tmpB = LPC_CREG->FLASHCFGB & ~(0xF << 12);
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LPC_CREG->FLASHCFGB = tmpB | ((uint32_t) clks << 12);
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}
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/**
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* @brief Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts
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* @return Nothing
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* @note The USB0 PLL & clock should be configured before calling this function. This function
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* should be called before the USB0 registers are accessed.
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*/
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STATIC INLINE void Chip_CREG_EnableUSB0Phy(void)
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{
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LPC_CREG->CREG0 &= ~(1 << 5);
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}
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/**
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* @brief Disable the USB0 high-speed PHY on LPC18xx/LPC43xx parts
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* @return Nothing
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* @note The USB0 PLL & clock should be configured before calling this function. This function
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* should be called before the USB0 registers are accessed.
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*/
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STATIC INLINE void Chip_CREG_DisableUSB0Phy(void)
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{
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LPC_CREG->CREG0 |= (1 << 5);
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}
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/**
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* @brief Configures the BOD and Reset on LPC18xx/LPC43xx parts.
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* @param BODVL : Brown-Out Detect voltage level (0-3)
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* @param BORVL : Brown-Out Reset voltage level (0-3)
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* @return Nothing
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*/
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STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)
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{
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LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
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}
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#if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
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/**
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* @brief Configures base address of image to be run in the Cortex M0APP Core.
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* @param memaddr : Address of the image (must be aligned to 4K)
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* @return Nothing
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*/
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STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
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{
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LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
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}
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/**
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* @brief Configures base address of image to be run in the Cortex M0SUB Core.
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* @param memaddr : Address of the image (must be aligned to 4K)
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* @return Nothing
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*/
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STATIC INLINE void Chip_CREG_SetM0SubMemMap(uint32_t memaddr)
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{
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LPC_CREG->M0SUBMEMMAP = memaddr & ~0xFFF;
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}
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/**
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* @brief Clear M4 IPC Event
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* @return Nothing
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*/
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STATIC INLINE void Chip_CREG_ClearM4Event(void)
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{
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LPC_CREG->M4TXEVENT = 0;
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}
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/**
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* @brief Clear M0APP IPC Event
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* @return Nothing
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*/
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STATIC INLINE void Chip_CREG_ClearM0AppEvent(void)
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{
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LPC_CREG->M0APPTXEVENT = 0;
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}
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/**
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* @brief Clear M0APP IPC Event
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* @return Nothing
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*/
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STATIC INLINE void Chip_CREG_ClearM0SubEvent(void)
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{
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LPC_CREG->M0SUBTXEVENT = 0;
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}
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#endif
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CREG_18XX_43XX_H_ */
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