152 lines
6.7 KiB
C
152 lines
6.7 KiB
C
/*
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* @brief Basic CMSIS include file for LPC43XX
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CMSIS_43XX_H_
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#define __CMSIS_43XX_H_
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#ifndef __CMSIS_H_
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#error "cmsis_43xx.h should not be included directly use cmsis.h instead"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx CMSIS include file
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* @ingroup CHIP_18XX_43XX_Drivers
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* @{
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*/
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#if defined(__ARMCC_VERSION)
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#pragma diag_suppress 2525
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#pragma push
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#pragma anon_unions
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#elif defined(__CWCC__)
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#pragma push
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#pragma cpp_extensions on
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/** @defgroup CMSIS_43XX_M0_COMMON CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions
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* @{
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*/
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 0 /*!< FPU present or not */
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/**
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* @}
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*/
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/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers
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* @{
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*/
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typedef enum {
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/* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */
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Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
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SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
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PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
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SysTick_IRQn = -1, /*!< 15 System Tick Timer */
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/* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
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DAC_IRQn = 0,/*!< 0 DAC */
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M4_IRQn = 1,/*!< 1 M0a */
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DMA_IRQn = 2,/*!< 2 DMA */
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RESERVED1_IRQn = 3,/*!< 3 */
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SGPIO_INPUT_IRQn = 4,/*!< 4 SGPIO Input bit match */
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SGPIO_MATCH_IRQn = 5,/*!< 5 SGPIO Pattern Match */
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SGPIO_SHIFT_IRQn = 6,/*!< 6 SGPIO Shift Clock */
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SGPIO_POS_IRQn = 7,/*!< 7 SGPIO Capture Clock */
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USB0_IRQn = 8,/*!< 8 USB0 */
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USB1_IRQn = 9,/*!< 9 USB1 */
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SCT_IRQn = 10,/*!< 10 SCT */
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RITIMER_IRQn = 11,/*!< 11 RITIMER */
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GINT1_IRQn = 12,/*!< 12 GINT1 */
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TIMER1_IRQn = 13,/*!< 13 TIMER1 */
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TIMER2_IRQn = 14,/*!< 14 TIMER2 */
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PIN_INT5_IRQn = 15,/*!< 15 GPIO Pin interrupt 5 */
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MCPWM_IRQn = 16,/*!< 16 MCPWM */
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ADC0_IRQn = 17,/*!< 17 ADC0 */
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I2C0_IRQn = 18,/*!< 18 I2C0 */
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I2C1_IRQn = 19,/*!< 19 I2C1 */
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SPI_INT_IRQn = 20,/*!< 20 SPI_INT */
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ADC1_IRQn = 21,/*!< 21 ADC1 */
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SSP0_IRQn = 22,/*!< 22 ORed SSP0, SSP1 */
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SSP1_IRQn = 22,/*!< 22 ORed SSP0, SSP1 */
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EVENTROUTER_IRQn = 23,/*!< 23 EVENTROUTER */
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USART0_IRQn = 24,/*!< 24 USART0 */
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UART1_IRQn = 25,/*!< 25 UART1 */
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USART2_IRQn = 26,/*!< 26 ORed USART2/C_CAN1 */
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C_CAN1_IRQn = 26,/*!< 26 ORed USART2/C_CAN1 */
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USART3_IRQn = 27,/*!< 27 USART3 */
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I2S0_IRQn = 28,/*!< 28 ORed I2S0, I2S1 */
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I2S1_IRQn = 28,/*!< 28 ORed I2S0, I2S1 */
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C_CAN0_IRQn = 29,/*!< 29 C_CAN0 */
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ADCHS_IRQn = 30,/*!< 30 ADCHS interrupt */
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M0APP_IRQn = 31,/*!< 31 M0SUB */
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} LPC43XX_M0_IRQn_Type;
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/**
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* @}
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*/
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typedef LPC43XX_M0_IRQn_Type IRQn_Type;
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/* Cortex-M4 processor and core peripherals */
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#include "core_cm0.h"
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* ifndef __CMSIS_43XX_H_ */
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