259 lines
11 KiB
C
259 lines
11 KiB
C
/*
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* @brief LPC18xx/43xx chip clock list used by CGU and CCU drivers
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CHIP_CLOCKS_H_
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#define __CHIP_CLOCKS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @ingroup CLOCK_18XX_43XX
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* @{
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*/
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/**
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* @brief CGU clock input list
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* These are possible input clocks for the CGU and can come
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* from both external (crystal) and internal (PLL) sources. These
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* clock inputs can be routed to the base clocks (@ref CHIP_CGU_BASE_CLK_T).
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*/
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typedef enum CHIP_CGU_CLKIN {
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CLKIN_32K, /*!< External 32KHz input */
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CLKIN_IRC, /*!< Internal IRC (12MHz) input */
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CLKIN_ENET_RX, /*!< External ENET_RX pin input */
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CLKIN_ENET_TX, /*!< External ENET_TX pin input */
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CLKIN_CLKIN, /*!< External GPCLKIN pin input */
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CLKIN_RESERVED1,
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CLKIN_CRYSTAL, /*!< External (main) crystal pin input */
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CLKIN_USBPLL, /*!< Internal USB PLL input */
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CLKIN_AUDIOPLL, /*!< Internal Audio PLL input */
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CLKIN_MAINPLL, /*!< Internal Main PLL input */
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CLKIN_RESERVED2,
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CLKIN_RESERVED3,
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CLKIN_IDIVA, /*!< Internal divider A input */
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CLKIN_IDIVB, /*!< Internal divider B input */
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CLKIN_IDIVC, /*!< Internal divider C input */
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CLKIN_IDIVD, /*!< Internal divider D input */
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CLKIN_IDIVE, /*!< Internal divider E input */
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CLKINPUT_PD /*!< External 32KHz input */
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} CHIP_CGU_CLKIN_T;
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/**
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* @brief CGU base clocks
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* CGU base clocks are clocks that are associated with a single input clock
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* and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
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* clock can be configured to use the CLKIN_MAINPLL input clock, which will in
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* turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
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* CLK_PERIPH_SGPIO periphral clocks.
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*/
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typedef enum CHIP_CGU_BASE_CLK {
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CLK_BASE_SAFE, /*!< Base clock for WDT oscillator, IRC input only */
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CLK_BASE_USB0, /*!< Base USB clock for USB0, USB PLL input only */
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#if defined(CHIP_LPC43XX)
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CLK_BASE_PERIPH, /*!< Base clock for SGPIO */
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#else
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CLK_BASE_RESERVED1,
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#endif
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CLK_BASE_USB1, /*!< Base USB clock for USB1 */
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CLK_BASE_MX, /*!< Base clock for CPU core */
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CLK_BASE_SPIFI, /*!< Base clock for SPIFI */
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#if defined(CHIP_LPC43XX)
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CLK_BASE_SPI, /*!< Base clock for SPI */
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#else
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CLK_BASE_RESERVED2,
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#endif
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CLK_BASE_PHY_RX, /*!< Base clock for PHY RX */
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CLK_BASE_PHY_TX, /*!< Base clock for PHY TX */
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CLK_BASE_APB1, /*!< Base clock for APB1 group */
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CLK_BASE_APB3, /*!< Base clock for APB3 group */
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CLK_BASE_LCD, /*!< Base clock for LCD pixel clock */
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#if defined(CHIP_LPC43XX)
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CLK_BASE_ADCHS, /*!< Base clock for ADCHS */
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#else
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CLK_BASE_RESERVED3,
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#endif
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CLK_BASE_SDIO, /*!< Base clock for SDIO */
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CLK_BASE_SSP0, /*!< Base clock for SSP0 */
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CLK_BASE_SSP1, /*!< Base clock for SSP1 */
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CLK_BASE_UART0, /*!< Base clock for UART0 */
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CLK_BASE_UART1, /*!< Base clock for UART1 */
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CLK_BASE_UART2, /*!< Base clock for UART2 */
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CLK_BASE_UART3, /*!< Base clock for UART3 */
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CLK_BASE_OUT, /*!< Base clock for CLKOUT pin */
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CLK_BASE_RESERVED4,
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CLK_BASE_RESERVED5,
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CLK_BASE_RESERVED6,
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CLK_BASE_RESERVED7,
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CLK_BASE_APLL, /*!< Base clock for audio PLL */
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CLK_BASE_CGU_OUT0, /*!< Base clock for CGUOUT0 pin */
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CLK_BASE_CGU_OUT1, /*!< Base clock for CGUOUT1 pin */
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CLK_BASE_LAST,
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CLK_BASE_NONE = CLK_BASE_LAST
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} CHIP_CGU_BASE_CLK_T;
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/**
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* @brief CGU dividers
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* CGU dividers provide an extra clock state where a specific clock can be
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* divided before being routed to a peripheral group. A divider accepts an
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* input clock and then divides it. To use the divided clock for a base clock
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* group, use the divider as the input clock for the base clock (for example,
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* use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
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*/
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typedef enum CHIP_CGU_IDIV {
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CLK_IDIV_A, /*!< CGU clock divider A */
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CLK_IDIV_B, /*!< CGU clock divider B */
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CLK_IDIV_C, /*!< CGU clock divider A */
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CLK_IDIV_D, /*!< CGU clock divider D */
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CLK_IDIV_E, /*!< CGU clock divider E */
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CLK_IDIV_LAST
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} CHIP_CGU_IDIV_T;
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#define CHIP_CGU_IDIV_MASK(x) ("\x03\x0F\x0F\x0F\xFF"[x])
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/**
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* @brief Peripheral clocks
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* Peripheral clocks are individual clocks routed to peripherals. Although
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* multiple peripherals may share a same base clock, each peripheral's clock
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* can be enabled or disabled individually. Some peripheral clocks also have
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* additional dividers associated with them.
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*/
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typedef enum CHIP_CCU_CLK {
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/* CCU1 clocks */
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CLK_APB3_BUS, /*!< APB3 bus clock from base clock CLK_BASE_APB3 */
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CLK_APB3_I2C1, /*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
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CLK_APB3_DAC, /*!< DAC peripheral clock from base clock CLK_BASE_APB3 */
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CLK_APB3_ADC0, /*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
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CLK_APB3_ADC1, /*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
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CLK_APB3_CAN0, /*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
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CLK_APB1_BUS = 32, /*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */
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CLK_APB1_MOTOCON, /*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
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CLK_APB1_I2C0, /*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
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CLK_APB1_I2S, /*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */
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CLK_APB1_CAN1, /*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
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CLK_SPIFI = 64, /*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
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CLK_MX_BUS = 96, /*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */
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CLK_MX_SPIFI, /*!< SPIFI register clock from base clock CLK_BASE_MX */
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CLK_MX_GPIO, /*!< GPIO register clock from base clock CLK_BASE_MX */
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CLK_MX_LCD, /*!< LCD register clock from base clock CLK_BASE_MX */
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CLK_MX_ETHERNET, /*!< ETHERNET register clock from base clock CLK_BASE_MX */
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CLK_MX_USB0, /*!< USB0 register clock from base clock CLK_BASE_MX */
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CLK_MX_EMC, /*!< EMC clock from base clock CLK_BASE_MX */
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CLK_MX_SDIO, /*!< SDIO register clock from base clock CLK_BASE_MX */
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CLK_MX_DMA, /*!< DMA register clock from base clock CLK_BASE_MX */
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CLK_MX_MXCORE, /*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */
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RESERVED_ALIGN = CLK_MX_MXCORE + 3,
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CLK_MX_SCT, /*!< SCT register clock from base clock CLK_BASE_MX */
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CLK_MX_USB1, /*!< USB1 register clock from base clock CLK_BASE_MX */
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CLK_MX_EMC_DIV, /*!< ENC divider clock from base clock CLK_BASE_MX */
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CLK_MX_FLASHA, /*!< FLASHA bank clock from base clock CLK_BASE_MX */
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CLK_MX_FLASHB, /*!< FLASHB bank clock from base clock CLK_BASE_MX */
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#if defined(CHIP_LPC43XX)
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CLK_M4_M0APP, /*!< M0 app CPU core clock from base clock CLK_BASE_MX */
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CLK_MX_ADCHS, /*!< ADCHS clock from base clock CLK_BASE_ADCHS */
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#else
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CLK_RESERVED1,
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CLK_RESERVED2,
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#endif
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CLK_MX_EEPROM, /*!< EEPROM clock from base clock CLK_BASE_MX */
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CLK_MX_WWDT = 128, /*!< WWDT register clock from base clock CLK_BASE_MX */
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CLK_MX_UART0, /*!< UART0 register clock from base clock CLK_BASE_MX */
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CLK_MX_UART1, /*!< UART1 register clock from base clock CLK_BASE_MX */
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CLK_MX_SSP0, /*!< SSP0 register clock from base clock CLK_BASE_MX */
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CLK_MX_TIMER0, /*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
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CLK_MX_TIMER1, /*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
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CLK_MX_SCU, /*!< SCU register/perigheral clock from base clock CLK_BASE_MX */
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CLK_MX_CREG, /*!< CREG clock from base clock CLK_BASE_MX */
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CLK_MX_RITIMER = 160, /*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */
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CLK_MX_UART2, /*!< UART3 register clock from base clock CLK_BASE_MX */
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CLK_MX_UART3, /*!< UART4 register clock from base clock CLK_BASE_MX */
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CLK_MX_TIMER2, /*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
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CLK_MX_TIMER3, /*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
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CLK_MX_SSP1, /*!< SSP1 register clock from base clock CLK_BASE_MX */
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CLK_MX_QEI, /*!< QEI register/perigheral clock from base clock CLK_BASE_MX */
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#if defined(CHIP_LPC43XX)
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CLK_PERIPH_BUS = 192, /*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */
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CLK_RESERVED3,
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CLK_PERIPH_CORE, /*!< Peripheral core clock from base clock CLK_BASE_PERIPH */
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CLK_PERIPH_SGPIO, /*!< SGPIO clock from base clock CLK_BASE_PERIPH */
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#else
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CLK_RESERVED3 = 192,
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CLK_RESERVED3A,
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CLK_RESERVED4,
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CLK_RESERVED5,
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#endif
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CLK_USB0 = 224, /*!< USB0 clock from base clock CLK_BASE_USB0 */
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CLK_USB1 = 256, /*!< USB1 clock from base clock CLK_BASE_USB1 */
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#if defined(CHIP_LPC43XX)
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CLK_SPI = 288, /*!< SPI clock from base clock CLK_BASE_SPI */
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CLK_ADCHS = 320, /*!< ADCHS clock from base clock CLK_BASE_ADCHS */
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#else
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CLK_RESERVED7 = 320,
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CLK_RESERVED8,
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#endif
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CLK_CCU1_LAST,
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/* CCU2 clocks */
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CLK_CCU2_START,
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CLK_APLL = CLK_CCU2_START, /*!< Audio PLL clock from base clock CLK_BASE_APLL */
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RESERVED_ALIGNB = CLK_CCU2_START + 31,
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CLK_APB2_UART3, /*!< UART3 clock from base clock CLK_BASE_UART3 */
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RESERVED_ALIGNC = CLK_CCU2_START + 63,
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CLK_APB2_UART2, /*!< UART2 clock from base clock CLK_BASE_UART2 */
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RESERVED_ALIGND = CLK_CCU2_START + 95,
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CLK_APB0_UART1, /*!< UART1 clock from base clock CLK_BASE_UART1 */
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RESERVED_ALIGNE = CLK_CCU2_START + 127,
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CLK_APB0_UART0, /*!< UART0 clock from base clock CLK_BASE_UART0 */
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RESERVED_ALIGNF = CLK_CCU2_START + 159,
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CLK_APB2_SSP1, /*!< SSP1 clock from base clock CLK_BASE_SSP1 */
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RESERVED_ALIGNG = CLK_CCU2_START + 191,
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CLK_APB0_SSP0, /*!< SSP0 clock from base clock CLK_BASE_SSP0 */
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RESERVED_ALIGNH = CLK_CCU2_START + 223,
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CLK_APB2_SDIO, /*!< SDIO clock from base clock CLK_BASE_SDIO */
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CLK_CCU2_LAST
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} CHIP_CCU_CLK_T;
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CHIP_CLOCKS_H_ */
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