170 lines
5.4 KiB
C
170 lines
5.4 KiB
C
/*
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* @brief Chip inclusion selector file
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*
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CHIP_H_
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#define __CHIP_H_
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#include "sys_config.h"
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#include "cmsis.h"
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#if defined(CHIP_LPC18XX)
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#include "chip_lpc18xx.h"
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#elif defined(CHIP_LPC43XX)
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#include "chip_lpc43xx.h"
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#else
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#error CHIP_LPC18XX or CHIP_LPC43XX must be defined
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#endif
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/* Aliasing for Chip_USB_Init */
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#define Chip_USB_Init Chip_USB0_Init
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @ingroup CHIP_18XX_43XX_DRIVER_OPTIONS
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* @{
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*/
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/**
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* @brief System oscillator rate
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* This value is defined externally to the chip layer and contains
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* the value in Hz for the external oscillator for the board. If using the
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* internal oscillator, this rate can be 0.
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*/
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extern const uint32_t OscRateIn;
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/**
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* @brief Clock rate on the CLKIN pin
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* This value is defined externally to the chip layer and contains
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* the value in Hz for the CLKIN pin for the board. If this pin isn't used,
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* this rate can be 0.
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*/
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extern const uint32_t ExtRateIn;
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/**
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* @}
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*/
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/** @defgroup SUPPORT_18XX_43XX_FUNC CHIP: LPC18xx/43xx support functions
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* @ingroup CHIP_18XX_43XX_Drivers
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* @{
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*/
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/**
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* @brief Current system clock rate, mainly used for sysTick
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*/
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extern uint32_t SystemCoreClock;
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/**
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* @brief Update system core clock rate, should be called if the
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* system has a clock rate change
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* @return None
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*/
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void SystemCoreClockUpdate(void);
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/**
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* @brief USB0 Pin and clock initialization
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* Calling this function will initialize the USB0 pins and the clock
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* @note This function will assume that the chip is clocked by an
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* external crystal oscillator of frequency 12MHz
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*/
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void Chip_USB0_Init(void);
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/**
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* @brief USB1 Pin and clock initialization
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* Calling this function will initialize the USB0 pins and the clock
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* @note This function will assume that the chip is clocked by an
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* external crystal oscillator of frequency 12MHz
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*/
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void Chip_USB1_Init(void);
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/**
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* @brief Set up and initialize hardware prior to call to main()
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* @return None
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* @note Chip_SystemInit() is called prior to the application and sets up
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* system clocking prior to the application starting.
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*/
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void Chip_SystemInit(void);
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/**
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* @brief Clock and PLL initialization based input given in @a clkin
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* @param clkin : Input reference clock to PLL1 (MAINPLL) see #CHIP_CGU_CLKIN_T
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* @param core_freq : Desired output frequency of the PLL1 (Base clock to CPU Core)
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* @param setbase : Setup default base clock of peripherals (see notes)
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* @return None
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* @note This API will initialize the MAINPLL (PLL1) to the frequency given by
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* @a core_freq, and will use this PLL's output as the base clock for CPU
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* Core. If @a clkin is #CLKIN_CRYSTAL then External Crystal Oscillator
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* of frequency 12MHz will be used as the input reference clock to PLL1.<br>
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* Parameter @a setbase if true will set APB[1,3], SSP[0,1], UART[0,1,2,3],
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* SPI base clocks to MAINPLL's output clock. If @a setbase is false then
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* the base clock settings for the peripherals will not be modified, only
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* CPU Core's base clock will be updated to use clock generated by PLL1.
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*/
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void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbase);
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/**
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* @brief Clock and PLL initialization based on the external oscillator
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* @return None
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* @note This API will initialize the MAINPLL (PLL1) to the maximum
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* frequency (180MHz[LPC18xx] or 204MHz[LPC43xx]) and uses this
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* PLL's output as the base clock for CPU Core. External Crystal Oscillator
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* of frequency 12MHz will be used as the input reference clock to PLL1.
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*/
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void Chip_SetupXtalClocking(void);
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/**
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* @brief Clock and PLL initialization based on the internal oscillator
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* @return None
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* @note This API will initialize the MAINPLL (PLL1) to the maximum
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* frequency (180MHz[LPC18xx] or 204MHz[LPC43xx]) and uses this
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* PLL's output as the base clock for CPU Core. Internal RC Oscillator
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* will be used as the input reference clock to PLL1.
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*/
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void Chip_SetupIrcClocking(void);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CHIP_H_ */
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