513 lines
20 KiB
C
513 lines
20 KiB
C
/*
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* @brief LPC18xx/43xx CCAN driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CCAN_18XX_43XX_H_
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#define __CCAN_18XX_43XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CCAN_18XX_43XX CHIP: LPC18xx/43xx CCAN driver
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* @ingroup CHIP_18XX_43XX_Drivers
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* @{
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*/
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/**
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* @brief CCAN message interface register block structure
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*/
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typedef struct { /*!< C_CAN message interface Structure */
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__IO uint32_t CMDREQ; /*!< Message interface command request */
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__IO uint32_t CMDMSK; /*!< Message interface command mask*/
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__IO uint32_t MSK1; /*!< Message interface mask 1 */
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__IO uint32_t MSK2; /*!< Message interface mask 2 */
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__IO uint32_t ARB1; /*!< Message interface arbitration 1 */
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__IO uint32_t ARB2; /*!< Message interface arbitration 2 */
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__IO uint32_t MCTRL; /*!< Message interface message control */
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__IO uint32_t DA1; /*!< Message interface data A1 */
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__IO uint32_t DA2; /*!< Message interface data A2 */
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__IO uint32_t DB1; /*!< Message interface data B1 */
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__IO uint32_t DB2; /*!< Message interface data B2 */
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__I uint32_t RESERVED[13];
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} CCAN_IF_T;
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/**
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* @brief CCAN Controller Area Network register block structure
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*/
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typedef struct { /*!< C_CAN Structure */
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__IO uint32_t CNTL; /*!< CAN control */
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__IO uint32_t STAT; /*!< Status register */
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__I uint32_t EC; /*!< Error counter */
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__IO uint32_t BT; /*!< Bit timing register */
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__I uint32_t INT; /*!< Interrupt register */
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__IO uint32_t TEST; /*!< Test register */
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__IO uint32_t BRPE; /*!< Baud rate prescaler extension register */
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__I uint32_t RESERVED0;
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CCAN_IF_T IF[2];
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__I uint32_t RESERVED2[8];
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__I uint32_t TXREQ1; /*!< Transmission request 1 */
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__I uint32_t TXREQ2; /*!< Transmission request 2 */
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__I uint32_t RESERVED3[6];
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__I uint32_t ND1; /*!< New data 1 */
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__I uint32_t ND2; /*!< New data 2 */
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__I uint32_t RESERVED4[6];
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__I uint32_t IR1; /*!< Interrupt pending 1 */
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__I uint32_t IR2; /*!< Interrupt pending 2 */
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__I uint32_t RESERVED5[6];
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__I uint32_t MSGV1; /*!< Message valid 1 */
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__I uint32_t MSGV2; /*!< Message valid 2 */
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__I uint32_t RESERVED6[6];
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__IO uint32_t CLKDIV; /*!< CAN clock divider register */
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} LPC_CCAN_T;
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/* CCAN Control register bit definitions */
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#define CCAN_CTRL_INIT (1 << 0) /*!< Initialization is started. */
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#define CCAN_CTRL_IE (1 << 1) /*!< Module Interupt Enable. */
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#define CCAN_CTRL_SIE (1 << 2) /*!< Status Change Interupt Enable. */
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#define CCAN_CTRL_EIE (1 << 3) /*!< Error Interupt Enable. */
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#define CCAN_CTRL_DAR (1 << 5) /*!< Automatic retransmission disabled. */
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#define CCAN_CTRL_CCE (1 << 6) /*!< The CPU has write access to the CANBT register while the INIT bit is one.*/
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#define CCAN_CTRL_TEST (1 << 7) /*!< Test mode. */
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/* CCAN STAT register bit definitions */
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#define CCAN_STAT_LEC_MASK (0x07) /* Mask for Last Error Code */
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#define CCAN_STAT_TXOK (1 << 3) /* Transmitted a message successfully */
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#define CCAN_STAT_RXOK (1 << 4) /* Received a message successfully */
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#define CCAN_STAT_EPASS (1 << 5) /* The CAN controller is in the error passive state*/
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#define CCAN_STAT_EWARN (1 << 6) /*At least one of the error counters in the EC has reached the error warning limit of 96.*/
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#define CCAN_STAT_BOFF (1 << 7) /*The CAN controller is in busoff state.*/
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/**
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* @brief Last Error Code definition
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*/
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typedef enum {
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CCAN_LEC_NO_ERROR, /*!< No error */
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CCAN_LEC_STUFF_ERROR, /*!< More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */
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CCAN_LEC_FORM_ERROR, /*!< A fixed format part of a received frame has the wrong format */
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CCAN_LEC_ACK_ERROR, /*!< The message this CAN core transmitted was not acknowledged. */
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CCAN_LEC_BIT1_ERROR, /*!< During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level
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(bit of logical value "1"), but the monitored bus value was LOW/dominant. */
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CCAN_LEC_BIT0_ERROR, /*!< During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a
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LOW/dominant level (data or identifier bit logical value "0"), but the monitored Bus value was HIGH/recessive. During busoff recovery this
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status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables
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the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed). */
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CCAN_LEC_CRC_ERROR, /*!< The CRC checksum was incorrect in the message received. */
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} CCAN_LEC_T;
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/* CCAN INT register bit definitions */
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#define CCAN_INT_NO_PENDING 0 /*!< No interrupt pending */
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#define CCAN_INT_STATUS 0x8000 /*!< Status interrupt*/
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#define CCAN_INT_MSG_NUM(n) (n) /*!<Number of messages which caused interrupts */
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/* CCAN TEST register bit definitions */
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#define CCAN_TEST_BASIC_MODE (1 << 2) /*!<IF1 registers used as TX buffer, IF2 registers used as RX buffer. */
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#define CCAN_TEST_SILENT_MODE (1 << 3) /*!<The module is in silent mode. */
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#define CCAN_TEST_LOOPBACK_MODE (1 << 4) /*!<Loop back mode is enabled.*/
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#define CCAN_TEST_TD_CONTROLLED (0) /*!< Level at the TD pin is controlled by the CAN controller.*/
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#define CCAN_TEST_TD_MONITORED (1 << 5) /*!< The sample point can be monitored at the TD pin.*/
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#define CCAN_TEST_TD_DOMINANT (2 << 5) /*!< TD pin is driven LOW/dominant.*/
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#define CCAN_TEST_TD_RECESSIVE (3 << 5) /*!< TD pin is driven HIGH/recessive.*/
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#define CCAN_TEST_RD_DOMINANT (0) /*!< The CAN bus is dominant (RD = 0).*/
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#define CCAN_TEST_RD_RECESSIVE (1 << 7) /*!< The CAN bus is recessive (RD = 1).*/
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#define CCAN_SEG1_DEFAULT_VAL 5
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#define CCAN_SEG2_DEFAULT_VAL 4
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#define CCAN_SJW_DEFAULT_VAL 0
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/**
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* @brief CCAN Transfer direction definition
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*/
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typedef enum {
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CCAN_RX_DIR,
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CCAN_TX_DIR,
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} CCAN_TRANSFER_DIR_T;
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/**
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* @brief Enable CCAN Interrupts
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param mask : Interrupt mask, or-ed bit value of
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* - CCAN_CTRL_IE <br>
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* - CCAN_CTRL_SIE <br>
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* - CCAN_CTRL_EIE <br>
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* @return Nothing
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*/
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STATIC INLINE void Chip_CCAN_EnableInt(LPC_CCAN_T *pCCAN, uint32_t mask)
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{
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pCCAN->CNTL |= mask;
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}
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/**
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* @brief Disable CCAN Interrupts
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param mask : Interrupt mask, or-ed bit value of
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* - CCAN_CTRL_IE <br>
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* - CCAN_CTRL_SIE <br>
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* - CCAN_CTRL_EIE <br>
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* @return Nothing
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*/
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STATIC INLINE void Chip_CCAN_DisableInt(LPC_CCAN_T *pCCAN, uint32_t mask)
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{
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pCCAN->CNTL &= ~mask;
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}
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/**
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* @brief Get the source ID of an interrupt
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return Interrupt source ID
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*/
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STATIC INLINE uint32_t Chip_CCAN_GetIntID(LPC_CCAN_T *pCCAN)
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{
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return pCCAN->INT;
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}
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/**
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* @brief Get the CCAN status register
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return CCAN status register (or-ed bit value of CCAN_STAT_*)
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*/
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STATIC INLINE uint32_t Chip_CCAN_GetStatus(LPC_CCAN_T *pCCAN)
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{
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return pCCAN->STAT;
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}
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/**
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* @brief Set the CCAN status
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param val : Value to be set for status register (or-ed bit value of CCAN_STAT_*)
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* @return Nothing
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*/
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STATIC INLINE void Chip_CCAN_SetStatus(LPC_CCAN_T *pCCAN, uint32_t val)
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{
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pCCAN->STAT = val & 0x1F;
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}
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/**
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* @brief Clear the status of CCAN bus
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param val : Status to be cleared (or-ed bit value of CCAN_STAT_*)
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* @return Nothing
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*/
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void Chip_CCAN_ClearStatus(LPC_CCAN_T *pCCAN, uint32_t val);
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/**
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* @brief Get the current value of the transmit/receive error counter
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param dir : direction
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* @return Current value of the transmit/receive error counter
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* @note When @a dir is #CCAN_RX_DIR, then MSB (bit-7) indicates the
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* receiver error passive level, if the bit is High(1) then the reciever
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* counter has reached error passive level as specified in CAN2.0
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* specification; else if the bit is Low(0) it indicates that the
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* error counter is below the passive level. Bits from (bit6-0) has
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* the actual error count. When @a dir is #CCAN_TX_DIR, the complete
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* 8-bits indicates the number of tx errors.
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*/
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STATIC INLINE uint8_t Chip_CCAN_GetErrCounter(LPC_CCAN_T *pCCAN, CCAN_TRANSFER_DIR_T dir)
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{
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return (dir == CCAN_TX_DIR) ? (pCCAN->EC & 0x0FF) : ((pCCAN->EC >> 8) & 0x0FF);
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}
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/**
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* @brief Enable test mode in CCAN
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return Nothing
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*/
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STATIC INLINE void Chip_CCAN_EnableTestMode(LPC_CCAN_T *pCCAN)
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{
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pCCAN->CNTL |= CCAN_CTRL_TEST;
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}
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/**
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* @brief Enable test mode in CCAN
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return Nothing
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*/
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STATIC INLINE void Chip_CCAN_DisableTestMode(LPC_CCAN_T *pCCAN)
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{
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pCCAN->CNTL &= ~CCAN_CTRL_TEST;
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}
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/**
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* @brief Enable/Disable test mode in CCAN
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param cfg : Test function, or-ed bit values of CCAN_TEST_*
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* @return Nothing
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* @note Test Mode must be enabled before using Chip_CCAN_EnableTestMode function.
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*/
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STATIC INLINE void Chip_CCAN_ConfigTestMode(LPC_CCAN_T *pCCAN, uint32_t cfg)
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{
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pCCAN->TEST = cfg;
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}
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/**
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* @brief Enable automatic retransmission
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return Nothing
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*/
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STATIC INLINE void Chip_CCAN_EnableAutoRetransmit(LPC_CCAN_T *pCCAN)
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{
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pCCAN->CNTL &= ~CCAN_CTRL_DAR;
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}
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/**
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* @brief Disable automatic retransmission
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return Nothing
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*/
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STATIC INLINE void Chip_CCAN_DisableAutoRetransmit(LPC_CCAN_T *pCCAN)
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{
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pCCAN->CNTL |= CCAN_CTRL_DAR;
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}
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/**
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* @brief Get the transmit repuest bit in all message objects
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return A 32 bits value, each bit corresponds to transmit request bit in message objects
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*/
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STATIC INLINE uint32_t Chip_CCAN_GetTxRQST(LPC_CCAN_T *pCCAN)
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{
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return pCCAN->TXREQ1 | (pCCAN->TXREQ2 << 16);
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}
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/**
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* @brief Initialize the CCAN peripheral, free all message object in RAM
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return Nothing
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*/
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void Chip_CCAN_Init(LPC_CCAN_T *pCCAN);
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/**
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* @brief De-initialize the CCAN peripheral
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return Nothing
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*/
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void Chip_CCAN_DeInit(LPC_CCAN_T *pCCAN);
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/**
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* @brief Select bit rate for CCAN bus
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param bitRate : Bit rate to be set
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* @return SUCCESS/ERROR
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*/
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Status Chip_CCAN_SetBitRate(LPC_CCAN_T *pCCAN, uint32_t bitRate);
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/** Number of message objects in Message RAM */
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#define CCAN_MSG_MAX_NUM 32
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/**
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* @brief CAN message object structure
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*/
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typedef struct {
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uint32_t id; /**< ID of message, if bit 30 is set then this is extended frame */
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uint32_t dlc; /**< Message data length */
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uint8_t data[8]; /**< Message data */
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} CCAN_MSG_OBJ_T;
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typedef enum {
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CCAN_MSG_IF1 = 0,
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CCAN_MSG_IF2 = 1,
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} CCAN_MSG_IF_T;
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/* bit field of IF command request n register */
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#define CCAN_IF_CMDREQ_MSG_NUM(n) (n) /* Message number (1->20) */
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#define CCAN_IF_CMDREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when RD/WR done */
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/* bit field of IF command mask register */
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#define CCAN_IF_CMDMSK_DATAB (1 << 0) /** 1 is transfer data byte 4-7 to message object, 0 is not */
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#define CCAN_IF_CMDMSK_DATAA (1 << 1) /** 1 is transfer data byte 0-3 to message object, 0 is not */
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#define CCAN_IF_CMDMSK_W_TXRQST (1 << 2) /** Request a transmission. Set the TXRQST bit IF1/2_MCTRL. */
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#define CCAN_IF_CMDMSK_R_NEWDAT (1 << 2) /** Clear NEWDAT bit in the message object */
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#define CCAN_IF_CMDMSK_R_CLRINTPND (1 << 3) /** Clear INTPND bit in the message object. */
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#define CCAN_IF_CMDMSK_CTRL (1 << 4) /** 1 is transfer the CTRL bit to the message object, 0 is not */
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#define CCAN_IF_CMDMSK_ARB (1 << 5) /** 1 is transfer the ARB bits to the message object, 0 is not */
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#define CCAN_IF_CMDMSK_MASK (1 << 6) /** 1 is transfer the MASK bit to the message object, 0 is not */
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#define CCAN_IF_CMDMSK_WR (1 << 7) /* Tranfer direction: Write */
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#define CCAN_IF_CMDMSK_RD (0) /* Tranfer direction: Read */
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#define CCAN_IF_CMDMSK_TRANSFER_ALL (CCAN_IF_CMDMSK_CTRL | CCAN_IF_CMDMSK_MASK | CCAN_IF_CMDMSK_ARB | \
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CCAN_IF_CMDMSK_DATAB | CCAN_IF_CMDMSK_DATAA)
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/* bit field of IF mask 2 register */
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#define CCAN_IF_MASK2_MXTD (1 << 15) /* 1 is extended identifier bit is used in the RX filter unit, 0 is not */
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#define CCAN_IF_MASK2_MDIR(n) (((n) & 0x01) << 14) /* 1 is direction bit is used in the RX filter unit, 0 is not */
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/* bit field of IF arbitration 2 register */
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#define CCAN_IF_ARB2_DIR(n) (((n) & 0x01) << 13) /* 1: Dir = transmit, 0: Dir = receive */
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#define CCAN_IF_ARB2_XTD (1 << 14) /* Extended identifier bit is used*/
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#define CCAN_IF_ARB2_MSGVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */
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/* bit field of IF message control register */
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#define CCAN_IF_MCTRL_DLC_MSK 0x000F /* bit mask for DLC */
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#define CCAN_IF_MCTRL_EOB (1 << 7) /* End of buffer, always write to 1 */
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#define CCAN_IF_MCTRL_TXRQ (1 << 8) /* 1 is TxRqst enabled */
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#define CCAN_IF_MCTRL_RMTEN(n) (((n) & 1UL) << 9) /* 1 is remote frame enabled */
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#define CCAN_IF_MCTRL_RXIE (1 << 10) /* 1 is RX interrupt enabled */
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#define CCAN_IF_MCTRL_TXIE (1 << 11) /* 1 is TX interrupt enabled */
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#define CCAN_IF_MCTRL_UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */
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#define CCAN_IF_MCTRL_INTP (1 << 13) /* 1 indicates message object is an interrupt source */
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#define CCAN_IF_MCTRL_MLST (1 << 14) /* 1 indicates a message loss. */
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#define CCAN_IF_MCTRL_NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */
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#define CCAN_MSG_ID_STD_MASK 0x07FF
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#define CCAN_MSG_ID_EXT_MASK 0x1FFFFFFF
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/**
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* @brief Tranfer message object between IF registers and Message RAM
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param IFSel : The Message interface to be used
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* @param mask : command mask (or-ed bit value of CCAN_IF_CMDMSK_*)
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* @param msgNum : The number of message object in message RAM to be get
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* @return Nothing
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*/
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void Chip_CCAN_TransferMsgObject(LPC_CCAN_T *pCCAN,
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CCAN_MSG_IF_T IFSel,
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uint32_t mask,
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uint32_t msgNum);
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/**
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* @brief Set a message into the message object in message RAM
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param IFSel : The Message interface to be used
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* @param dir : transmit/receive
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* @param remoteFrame: Enable/Disable passives transmit by using remote frame
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* @param msgNum : Message number
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* @param pMsgObj : Pointer of message to be set
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* @return Nothing
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*/
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void Chip_CCAN_SetMsgObject (LPC_CCAN_T *pCCAN,
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CCAN_MSG_IF_T IFSel,
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CCAN_TRANSFER_DIR_T dir,
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bool remoteFrame,
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uint8_t msgNum,
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const CCAN_MSG_OBJ_T *pMsgObj);
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/**
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* @brief Get a message object in message RAM into the message buffer
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param IFSel : The Message interface to be used
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* @param msgNum : The number of message object in message RAM to be get
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* @param pMsgObj : Pointer of the message buffer
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* @return Nothing
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*/
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void Chip_CCAN_GetMsgObject(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum, CCAN_MSG_OBJ_T *pMsgObj);
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/**
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* @brief Enable/Disable the message object to valid
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param IFSel : The Message interface to be used
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* @param msgNum : Message number
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* @param valid : true: valid, false: invalide
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* @return Nothing
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*/
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void Chip_CCAN_SetValidMsg(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum, bool valid);
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/**
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* @brief Check the message objects is valid or not
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @return A 32 bits value, each bit corresponds to a message objects form 0 to 31 (1 is valid, 0 is invalid)
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*/
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STATIC INLINE uint32_t Chip_CCAN_GetValidMsg(LPC_CCAN_T *pCCAN)
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{
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return pCCAN->MSGV1 | (pCCAN->MSGV2 << 16);
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}
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/**
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* @brief Clear the pending message interrupt
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param IFSel : The Message interface to be used
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* @param msgNum : Message number
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* @param dir : Select transmit or receive interrupt to be cleared
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* @return Nothing
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*/
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STATIC INLINE void Chip_CCAN_ClearMsgIntPend(LPC_CCAN_T *pCCAN,
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CCAN_MSG_IF_T IFSel,
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uint8_t msgNum,
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CCAN_TRANSFER_DIR_T dir)
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{
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(void) dir;
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Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_CLRINTPND, msgNum);
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}
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/**
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* @brief Clear new data flag bit in the message object
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param IFSel : The Message interface to be used
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* @param msgNum : Message number
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* @return Nothing
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*/
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STATIC INLINE void Chip_CCAN_ClearNewDataFlag(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum)
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{
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Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_NEWDAT, msgNum);
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}
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/**
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* @brief Send a message
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param IFSel : The Message interface to be used
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* @param remoteFrame: Enable/Disable passives transmit by using remote frame
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* @param pMsgObj : Message to be transmitted
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* @return Nothing
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*/
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void Chip_CCAN_Send (LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, bool remoteFrame, CCAN_MSG_OBJ_T *pMsgObj);
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/**
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* @brief Register a message ID for receiving
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param IFSel : The Message interface to be used
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* @param id : Received message ID
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* @return Nothing
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*/
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void Chip_CCAN_AddReceiveID(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint32_t id);
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/**
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* @brief Remove a registered message ID from receiving
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* @param IFSel : The Message interface to be used
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* @param pCCAN : The base of CCAN peripheral on the chip
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* @param id : Received message ID to be removed
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* @return Nothing
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*/
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void Chip_CCAN_DeleteReceiveID(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint32_t id);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CCAN_18XX_43XX_H_ */
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