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espressif_tinyusb
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fix warning with lpcopen

This commit is contained in:
hathach 2018-12-07 13:22:12 +07:00
parent 89820a36a1
commit f769ecddaf
No known key found for this signature in database
GPG Key ID: 2FA891220FBFD581
35 changed files with 58 additions and 28 deletions
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4
hw/mcu/nxp/lpc_chip_11u6x/inc/lpc_types.h
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@ -82,10 +82,10 @@ typedef enum {
} TRANSFER_BLOCK_T; } TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */ /** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)(); //typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */ /** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)(); //typedef int32_t (*PFI)();
/** /**
* @} * @}

4
hw/mcu/nxp/lpc_chip_11u6x/inc/pinint_11u6x.h
View File

@ -123,14 +123,14 @@ typedef enum Chip_PININT_BITSLICE_CFG {
* @return Nothing * @return Nothing
* @note This function should be used after the Chip_GPIO_Init() function. * @note This function should be used after the Chip_GPIO_Init() function.
*/ */
STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) {} STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/** /**
* @brief De-Initialize Pin interrupt block * @brief De-Initialize Pin interrupt block
* @param pPININT : The base address of Pin interrupt block * @param pPININT : The base address of Pin interrupt block
* @return Nothing * @return Nothing
*/ */
STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) {} STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/** /**
* @brief Configure the pins as edge sensitive in Pin interrupt block * @brief Configure the pins as edge sensitive in Pin interrupt block

1
hw/mcu/nxp/lpc_chip_11u6x/inc/rtc_11u6x.h
View File

@ -207,6 +207,7 @@ STATIC INLINE void Chip_RTC_DisableWakeup(LPC_RTC_T *pRTC, uint32_t ints)
*/ */
STATIC INLINE uint32_t Chip_RTC_ClearStatus(LPC_RTC_T *pRTC, uint32_t stsMask) STATIC INLINE uint32_t Chip_RTC_ClearStatus(LPC_RTC_T *pRTC, uint32_t stsMask)
{ {
(void) stsMask;
return pRTC->CTRL; return pRTC->CTRL;
} }

2
hw/mcu/nxp/lpc_chip_11u6x/src/gpio_11u6x.c
View File

@ -50,12 +50,14 @@
/* Initialize GPIO block */ /* Initialize GPIO block */
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO); Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
} }
/* De-Initialize GPIO block */ /* De-Initialize GPIO block */
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO); Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
} }

1
hw/mcu/nxp/lpc_chip_11u6x/src/uart_0_11u6x.c
View File

@ -65,6 +65,7 @@ void Chip_UART0_Init(LPC_USART0_T *pUART)
/* De-initializes the pUART peripheral */ /* De-initializes the pUART peripheral */
void Chip_UART0_DeInit(LPC_USART0_T *pUART) void Chip_UART0_DeInit(LPC_USART0_T *pUART)
{ {
(void) pUART;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_UART0); Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_UART0);
} }

4
hw/mcu/nxp/lpc_chip_13xx/inc/lpc_types.h
View File

@ -82,10 +82,10 @@ typedef enum {
} TRANSFER_BLOCK_T; } TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */ /** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)(); // typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */ /** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)(); // typedef int32_t (*PFI)();
/** /**
* @} * @}

4
hw/mcu/nxp/lpc_chip_13xx/inc/pinint_13xx.h
View File

@ -78,14 +78,14 @@ typedef struct { /*!< PIN_INT Structure */
* @return Nothing * @return Nothing
* @note This function should be used after the Chip_GPIO_Init() function. * @note This function should be used after the Chip_GPIO_Init() function.
*/ */
STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) {} STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/** /**
* @brief De-Initialize Pin interrupt block * @brief De-Initialize Pin interrupt block
* @param pPININT : The base address of Pin interrupt block * @param pPININT : The base address of Pin interrupt block
* @return Nothing * @return Nothing
*/ */
STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) {} STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/** /**
* @brief Configure the pins as edge sensitive in Pin interrupt block * @brief Configure the pins as edge sensitive in Pin interrupt block

2
hw/mcu/nxp/lpc_chip_13xx/src/gpio_13xx_1.c
View File

@ -52,12 +52,14 @@
/* Initialize GPIO block */ /* Initialize GPIO block */
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO); Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
} }
/* De-Initialize GPIO block */ /* De-Initialize GPIO block */
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO); Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
} }

1
hw/mcu/nxp/lpc_chip_13xx/src/uart_13xx.c
View File

@ -66,6 +66,7 @@ void Chip_UART_Init(LPC_USART_T *pUART)
/* De-initializes the pUART peripheral */ /* De-initializes the pUART peripheral */
void Chip_UART_DeInit(LPC_USART_T *pUART) void Chip_UART_DeInit(LPC_USART_T *pUART)
{ {
(void) pUART;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_UART0); Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_UART0);
} }

4
hw/mcu/nxp/lpc_chip_175x_6x/inc/lpc_types.h
View File

@ -82,10 +82,10 @@ typedef enum {
} TRANSFER_BLOCK_T; } TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */ /** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)(void); // typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */ /** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)(void); // typedef int32_t (*PFI)();
/** /**
* @} * @}

1
hw/mcu/nxp/lpc_chip_175x_6x/src/clock_17xx_40xx.c
View File

@ -328,6 +328,7 @@ uint32_t Chip_Clock_GetSYSCLKRate(void)
case (uint32_t) SYSCTL_PLLCLKSRC_RTC: case (uint32_t) SYSCTL_PLLCLKSRC_RTC:
return Chip_Clock_GetRTCOscRate(); return Chip_Clock_GetRTCOscRate();
#endif #endif
default: break;
} }
return 0; return 0;
} }

1
hw/mcu/nxp/lpc_chip_18xx/inc/ccan_18xx_43xx.h
View File

@ -451,6 +451,7 @@ STATIC INLINE void Chip_CCAN_ClearMsgIntPend(LPC_CCAN_T *pCCAN,
uint8_t msgNum, uint8_t msgNum,
CCAN_TRANSFER_DIR_T dir) CCAN_TRANSFER_DIR_T dir)
{ {
(void) dir;
Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_CLRINTPND, msgNum); Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_CLRINTPND, msgNum);
} }

2
hw/mcu/nxp/lpc_chip_18xx/inc/enet_18xx_43xx.h
View File

@ -582,6 +582,7 @@ STATIC INLINE void Chip_ENET_RXDisable(LPC_ENET_T *pENET)
*/ */
STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET) STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET)
{ {
(void) pENET;
LPC_CREG->CREG6 |= 0x4; LPC_CREG->CREG6 |= 0x4;
} }
@ -595,6 +596,7 @@ STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET)
*/ */
STATIC INLINE void Chip_ENET_MIIEnable(LPC_ENET_T *pENET) STATIC INLINE void Chip_ENET_MIIEnable(LPC_ENET_T *pENET)
{ {
(void) pENET;
LPC_CREG->CREG6 &= ~0x7; LPC_CREG->CREG6 &= ~0x7;
} }

4
hw/mcu/nxp/lpc_chip_18xx/inc/lpc_types.h
View File

@ -88,10 +88,10 @@ typedef enum {
} TRANSFER_BLOCK_T; } TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */ /** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)(); // typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */ /** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)(); // typedef int32_t (*PFI)();
/** /**
* @} * @}

4
hw/mcu/nxp/lpc_chip_18xx/inc/pinint_18xx_43xx.h
View File

@ -77,14 +77,14 @@ typedef struct { /*!< PIN_INT Structure */
* @return Nothing * @return Nothing
* @note This function should be used after the Chip_GPIO_Init() function. * @note This function should be used after the Chip_GPIO_Init() function.
*/ */
STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) {} STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/** /**
* @brief De-Initialize Pin interrupt block * @brief De-Initialize Pin interrupt block
* @param pPININT : The base address of Pin interrupt block * @param pPININT : The base address of Pin interrupt block
* @return Nothing * @return Nothing
*/ */
STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) {} STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/** /**
* @brief Configure the pins as edge sensitive in Pin interrupt block * @brief Configure the pins as edge sensitive in Pin interrupt block

1
hw/mcu/nxp/lpc_chip_18xx/src/clock_18xx_43xx.c
View File

@ -194,6 +194,7 @@ static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t Test
/* Returns clock rate out of a divider */ /* Returns clock rate out of a divider */
static uint32_t Chip_Clock_GetDivRate(CHIP_CGU_CLKIN_T clock, CHIP_CGU_IDIV_T divider) static uint32_t Chip_Clock_GetDivRate(CHIP_CGU_CLKIN_T clock, CHIP_CGU_IDIV_T divider)
{ {
(void) clock;
CHIP_CGU_CLKIN_T input; CHIP_CGU_CLKIN_T input;
uint32_t div; uint32_t div;

2
hw/mcu/nxp/lpc_chip_18xx/src/gpio_18xx_43xx.c
View File

@ -50,11 +50,13 @@
/* Initialize GPIO block */ /* Initialize GPIO block */
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
} }
/* De-Initialize GPIO block */ /* De-Initialize GPIO block */
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
} }

2
hw/mcu/nxp/lpc_chip_18xx/src/sysinit_18xx_43xx.c
View File

@ -133,7 +133,7 @@ void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbas
/* Setup system base clocks and initial states. This won't enable and /* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */ each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { for (i = 0; i < (int) (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
} }

2
hw/mcu/nxp/lpc_chip_18xx/src/uart_18xx_43xx.c
View File

@ -132,6 +132,8 @@ void Chip_UART_Init(LPC_USART_T *pUART)
/* Disable fractional divider */ /* Disable fractional divider */
pUART->FDR = 0x10; pUART->FDR = 0x10;
(void) tmp;
} }
/* De-initializes the pUART peripheral */ /* De-initializes the pUART peripheral */

2
hw/mcu/nxp/lpc_chip_40xx/inc/gpio_17xx_40xx.h
View File

@ -63,6 +63,7 @@ typedef struct { /* GPIO_PORT Structure */
*/ */
STATIC INLINE void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) STATIC INLINE void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO); Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
} }
@ -73,6 +74,7 @@ STATIC INLINE void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
*/ */
STATIC INLINE void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) STATIC INLINE void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO); Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
} }

2
hw/mcu/nxp/lpc_chip_40xx/inc/gpioint_17xx_40xx.h
View File

@ -79,6 +79,7 @@ typedef enum {
*/ */
STATIC INLINE void Chip_GPIOINT_Init(LPC_GPIOINT_T *pGPIOINT) STATIC INLINE void Chip_GPIOINT_Init(LPC_GPIOINT_T *pGPIOINT)
{ {
(void) pGPIOINT;
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO); Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
} }
@ -92,6 +93,7 @@ STATIC INLINE void Chip_GPIOINT_Init(LPC_GPIOINT_T *pGPIOINT)
*/ */
STATIC INLINE void Chip_GPIOINT_DeInit(LPC_GPIOINT_T *pGPIOINT) STATIC INLINE void Chip_GPIOINT_DeInit(LPC_GPIOINT_T *pGPIOINT)
{ {
(void) pGPIOINT;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO); Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
} }

1
hw/mcu/nxp/lpc_chip_40xx/inc/iocon_17xx_40xx.h
View File

@ -150,6 +150,7 @@ typedef struct {
*/ */
STATIC INLINE void Chip_IOCON_Init(LPC_IOCON_T *pIOCON) STATIC INLINE void Chip_IOCON_Init(LPC_IOCON_T *pIOCON)
{ {
(void) pIOCON;
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO); Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
} }

4
hw/mcu/nxp/lpc_chip_40xx/inc/lpc_types.h
View File

@ -82,10 +82,10 @@ typedef enum {
} TRANSFER_BLOCK_T; } TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */ /** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)(); // typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */ /** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)(); // typedef int32_t (*PFI)();
/** /**
* @} * @}

2
hw/mcu/nxp/lpc_chip_40xx/inc/wwdt_17xx_40xx.h
View File

@ -101,7 +101,7 @@ void Chip_WWDT_Init(LPC_WWDT_T *pWWDT);
* @param pWWDT : The base of WatchDog Timer peripheral on the chip * @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None * @return None
*/ */
STATIC INLINE void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT) {} STATIC INLINE void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT) { (void) pWWDT; }
/** /**
* @brief Set WDT timeout constant value used for feed * @brief Set WDT timeout constant value used for feed

1
hw/mcu/nxp/lpc_chip_40xx/src/clock_17xx_40xx.c
View File

@ -328,6 +328,7 @@ uint32_t Chip_Clock_GetSYSCLKRate(void)
case (uint32_t) SYSCTL_PLLCLKSRC_RTC: case (uint32_t) SYSCTL_PLLCLKSRC_RTC:
return Chip_Clock_GetRTCOscRate(); return Chip_Clock_GetRTCOscRate();
#endif #endif
default: break;
} }
return 0; return 0;
} }

1
hw/mcu/nxp/lpc_chip_43xx/inc/ccan_18xx_43xx.h
View File

@ -451,6 +451,7 @@ STATIC INLINE void Chip_CCAN_ClearMsgIntPend(LPC_CCAN_T *pCCAN,
uint8_t msgNum, uint8_t msgNum,
CCAN_TRANSFER_DIR_T dir) CCAN_TRANSFER_DIR_T dir)
{ {
(void) dir;
Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_CLRINTPND, msgNum); Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_CLRINTPND, msgNum);
} }

2
hw/mcu/nxp/lpc_chip_43xx/inc/enet_18xx_43xx.h
View File

@ -582,6 +582,7 @@ STATIC INLINE void Chip_ENET_RXDisable(LPC_ENET_T *pENET)
*/ */
STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET) STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET)
{ {
(void) pENET;
LPC_CREG->CREG6 |= 0x4; LPC_CREG->CREG6 |= 0x4;
} }
@ -595,6 +596,7 @@ STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET)
*/ */
STATIC INLINE void Chip_ENET_MIIEnable(LPC_ENET_T *pENET) STATIC INLINE void Chip_ENET_MIIEnable(LPC_ENET_T *pENET)
{ {
(void) pENET;
LPC_CREG->CREG6 &= ~0x7; LPC_CREG->CREG6 &= ~0x7;
} }

4
hw/mcu/nxp/lpc_chip_43xx/inc/lpc_types.h
View File

@ -88,10 +88,10 @@ typedef enum {
} TRANSFER_BLOCK_T; } TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */ /** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)(); // typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */ /** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)(); // typedef int32_t (*PFI)();
/** /**
* @} * @}

4
hw/mcu/nxp/lpc_chip_43xx/inc/pinint_18xx_43xx.h
View File

@ -77,14 +77,14 @@ typedef struct { /*!< PIN_INT Structure */
* @return Nothing * @return Nothing
* @note This function should be used after the Chip_GPIO_Init() function. * @note This function should be used after the Chip_GPIO_Init() function.
*/ */
STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) {} STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/** /**
* @brief De-Initialize Pin interrupt block * @brief De-Initialize Pin interrupt block
* @param pPININT : The base address of Pin interrupt block * @param pPININT : The base address of Pin interrupt block
* @return Nothing * @return Nothing
*/ */
STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) {} STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/** /**
* @brief Configure the pins as edge sensitive in Pin interrupt block * @brief Configure the pins as edge sensitive in Pin interrupt block

1
hw/mcu/nxp/lpc_chip_43xx/src/clock_18xx_43xx.c
View File

@ -194,6 +194,7 @@ static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t Test
/* Returns clock rate out of a divider */ /* Returns clock rate out of a divider */
static uint32_t Chip_Clock_GetDivRate(CHIP_CGU_CLKIN_T clock, CHIP_CGU_IDIV_T divider) static uint32_t Chip_Clock_GetDivRate(CHIP_CGU_CLKIN_T clock, CHIP_CGU_IDIV_T divider)
{ {
(void) clock;
CHIP_CGU_CLKIN_T input; CHIP_CGU_CLKIN_T input;
uint32_t div; uint32_t div;

2
hw/mcu/nxp/lpc_chip_43xx/src/gpio_18xx_43xx.c
View File

@ -50,11 +50,13 @@
/* Initialize GPIO block */ /* Initialize GPIO block */
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO) void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
} }
/* De-Initialize GPIO block */ /* De-Initialize GPIO block */
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO) void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{ {
(void) pGPIO;
} }

6
hw/mcu/nxp/lpc_chip_43xx/src/i2c_18xx_43xx.c
View File

@ -197,11 +197,11 @@ int handleMasterXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
/* Rx handling */ /* Rx handling */
case 0x58: /* Data Received and NACK sent */ case 0x58: /* Data Received and NACK sent */
cclr &= ~I2C_CON_STO; cclr &= ~I2C_CON_STO;
/* FALLTHRU */
case 0x50: /* Data Received and ACK sent */ case 0x50: /* Data Received and ACK sent */
*xfer->rxBuff++ = pI2C->DAT; *xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--; xfer->rxSz--;
/* FALLTHRU */
case 0x40: /* SLA+R sent and ACK received */ case 0x40: /* SLA+R sent and ACK received */
if (xfer->rxSz > 1) { if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA; cclr &= ~I2C_CON_AA;
@ -292,7 +292,7 @@ int handleSlaveXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
case 0xA8: /* SLA+R received */ case 0xA8: /* SLA+R received */
case 0xB0: /* SLA+R received after losing arbitration */ case 0xB0: /* SLA+R received after losing arbitration */
xfer->slaveAddr = pI2C->DAT & ~1; xfer->slaveAddr = pI2C->DAT & ~1;
/* FALLTHRU */
case 0xB8: /* DATA sent and ACK received */ case 0xB8: /* DATA sent and ACK received */
pI2C->DAT = *xfer->txBuff++; pI2C->DAT = *xfer->txBuff++;
xfer->txSz--; xfer->txSz--;

4
hw/mcu/nxp/lpc_chip_43xx/src/i2cm_18xx_43xx.c
View File

@ -100,7 +100,7 @@ uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
cclr &= ~I2C_CON_STO; cclr &= ~I2C_CON_STO;
break; break;
} }
/* FALLTHRU */
case 0x18: /* SLA+W sent and ACK received */ case 0x18: /* SLA+W sent and ACK received */
case 0x28: /* DATA sent and ACK received */ case 0x28: /* DATA sent and ACK received */
if (!xfer->txSz) { if (!xfer->txSz) {
@ -124,7 +124,7 @@ uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
case 0x50: /* Data Received and ACK sent */ case 0x50: /* Data Received and ACK sent */
*xfer->rxBuff++ = pI2C->DAT; *xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--; xfer->rxSz--;
/* FALLTHRU */
case 0x40: /* SLA+R sent and ACK received */ case 0x40: /* SLA+R sent and ACK received */
if ((xfer->rxSz > 1) || (xfer->options & I2CM_XFER_OPTION_LAST_RX_ACK)) { if ((xfer->rxSz > 1) || (xfer->options & I2CM_XFER_OPTION_LAST_RX_ACK)) {
cclr &= ~I2C_CON_AA; cclr &= ~I2C_CON_AA;

2
hw/mcu/nxp/lpc_chip_43xx/src/sysinit_18xx_43xx.c
View File

@ -133,7 +133,7 @@ void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbas
/* Setup system base clocks and initial states. This won't enable and /* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */ each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { for (i = 0; i < (int) (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
} }

2
hw/mcu/nxp/lpc_chip_43xx/src/uart_18xx_43xx.c
View File

@ -132,6 +132,8 @@ void Chip_UART_Init(LPC_USART_T *pUART)
/* Disable fractional divider */ /* Disable fractional divider */
pUART->FDR = 0x10; pUART->FDR = 0x10;
(void) tmp;
} }
/* De-initializes the pUART peripheral */ /* De-initializes the pUART peripheral */