add dcd_pipe_control_read
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40b65b265c
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@ -94,7 +94,9 @@ tusb_error_t hidd_control_request(uint8_t coreid, tusb_std_request_t const * p_r
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case HID_REQUEST_CONTROL_SET_REPORT:
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case HID_REQUEST_CONTROL_SET_REPORT:
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// TODO hidd set report, has data phase
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// TODO hidd set report, has data phase
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// dcd_pipe_control_read(coreid, .....
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// TODO verify data read from control pipe
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// ; uint8_t hehe[10]= { 0 };
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// dcd_pipe_control_read(coreid, hehe, p_request->wLength);
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break;
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break;
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case HID_REQUEST_CONTROL_GET_REPORT:
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case HID_REQUEST_CONTROL_GET_REPORT:
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@ -63,7 +63,7 @@ void dcd_controller_connect(uint8_t coreid);
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void dcd_isr(uint8_t coreid);
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void dcd_isr(uint8_t coreid);
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tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_t length);
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tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_t length);
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tusb_error_t dcd_pipe_control_read(uint8_t coreid, void const * buffer, uint16_t length);
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tusb_error_t dcd_pipe_control_read(uint8_t coreid, void * buffer, uint16_t length);
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void dcd_pipe_control_write_zero_length(uint8_t coreid);
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void dcd_pipe_control_write_zero_length(uint8_t coreid);
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tusb_error_t dcd_endpoint_configure(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc) ATTR_WARN_UNUSED_RESULT;
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tusb_error_t dcd_endpoint_configure(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc) ATTR_WARN_UNUSED_RESULT;
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@ -101,7 +101,6 @@ static inline uint32_t sie_command_read (uint8_t cmd_code, uint8_t data_len)
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// IMPLEMENTATION
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// IMPLEMENTATION
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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void endpoint_control_isr(uint8_t coreid)
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void endpoint_control_isr(uint8_t coreid)
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{
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{
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(void) coreid; // suppress compiler warning
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(void) coreid; // suppress compiler warning
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@ -248,9 +247,9 @@ tusb_error_t dcd_endpoint_configure(uint8_t coreid, tusb_descriptor_endpoint_t c
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endpoint_set_max_packet_size(phy_ep, p_endpoint_desc->wMaxPacketSize.size);
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endpoint_set_max_packet_size(phy_ep, p_endpoint_desc->wMaxPacketSize.size);
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#ifndef _TEST_
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#ifndef _TEST_
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while ((LPC_USB->USBDevIntSt & DEV_INT_ENDPOINT_REALIZED_MASK) == 0) {} // TODO can be omitted
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while ((LPC_USB->USBDevIntSt & DEV_INT_ENDPOINT_REALIZED_MASK) == 0) {} // TODO can be omitted, or move to set max packet size
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#endif
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LPC_USB->USBDevIntClr = DEV_INT_ENDPOINT_REALIZED_MASK;
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LPC_USB->USBDevIntClr = DEV_INT_ENDPOINT_REALIZED_MASK;
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#endif
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//------------- DMA set up -------------//
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//------------- DMA set up -------------//
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memclr_(dcd_dd + phy_ep, sizeof(dcd_dma_descriptor_t));
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memclr_(dcd_dd + phy_ep, sizeof(dcd_dma_descriptor_t));
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@ -281,6 +280,12 @@ void dcd_device_set_configuration(uint8_t coreid, uint8_t config_num)
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sie_command_write(SIE_CMDCODE_CONFIGURE_DEVICE, 1, 1);
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sie_command_write(SIE_CMDCODE_CONFIGURE_DEVICE, 1, 1);
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}
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}
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static inline uint16_t length_unit_byte2dword(uint16_t length_in_bytes) ATTR_ALWAYS_INLINE ATTR_CONST;
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static inline uint16_t length_unit_byte2dword(uint16_t length_in_bytes)
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{
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return (length_in_bytes + 3) / 4; // length_in_dword
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}
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tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_t length)
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tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_t length)
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{
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{
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(void) coreid; // suppress compiler warning
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(void) coreid; // suppress compiler warning
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@ -290,7 +295,7 @@ tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_
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LPC_USB->USBCtrl = SLAVE_CONTROL_WRITE_ENABLE_MASK; // logical endpoint = 0
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LPC_USB->USBCtrl = SLAVE_CONTROL_WRITE_ENABLE_MASK; // logical endpoint = 0
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LPC_USB->USBTxPLen = length;
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LPC_USB->USBTxPLen = length;
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for (uint16_t count = 0; count < (length + 3) / 4; count++)
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for (uint16_t count = 0; count < length_unit_byte2dword(length); count++)
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{
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{
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LPC_USB->USBTxData = *((uint32_t *)buffer); // NOTE: cortex M3 have no problem with alignment
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LPC_USB->USBTxData = *((uint32_t *)buffer); // NOTE: cortex M3 have no problem with alignment
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buffer += 4;
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buffer += 4;
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@ -304,8 +309,20 @@ tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_
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return TUSB_ERROR_NONE;
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return TUSB_ERROR_NONE;
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}
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}
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tusb_error_t dcd_pipe_control_read(uint8_t coreid, void const * buffer, uint16_t length)
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tusb_error_t dcd_pipe_control_read(uint8_t coreid, void * buffer, uint16_t length)
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{
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{
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LPC_USB->USBCtrl = SLAVE_CONTROL_READ_ENABLE_MASK; // logical endpoint = 0
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while ((LPC_USB->USBRxPLen & SLAVE_RXPLEN_PACKET_READY_MASK) == 0) {}
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uint16_t actual_length = min16_of(length, (uint16_t) (LPC_USB->USBRxPLen & SLAVE_RXPLEN_PACKET_LENGTH_MASK) );
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uint32_t *p_read_data = (uint32_t*) buffer;
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for( uint16_t count=0; count < length_unit_byte2dword(actual_length); count++)
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{
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*p_read_data = LPC_USB->USBRxData;
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p_read_data++; // increase by 4 ( sizeof(uint32_t) )
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}
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LPC_USB->USBCtrl = 0;
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return TUSB_ERROR_NONE;
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return TUSB_ERROR_NONE;
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}
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}
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@ -72,10 +72,10 @@ static tusb_error_t usbd_string_descriptor_init(void);
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// APPLICATION INTERFACE
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// APPLICATION INTERFACE
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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//bool tusbd_is_configured(uint8_t coreid)
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bool tusbd_is_configured(uint8_t coreid)
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//{
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{
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//
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return usbd_devices[coreid].state == TUSB_DEVICE_STATE_CONFIGURED;
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//}
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}
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void usbd_bus_reset(uint32_t coreid)
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void usbd_bus_reset(uint32_t coreid)
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{
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{
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