Merge pull request #1220 from t123yh/master
Add support for Allwinner F1C100s family
This commit is contained in:
Ha Thach
GitHub
commit
eea19daac6
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@ -137,3 +137,6 @@
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[submodule "hw/mcu/infineon/mtb-xmclib-cat3"]
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path = hw/mcu/infineon/mtb-xmclib-cat3
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url = https://github.com/Infineon/mtb-xmclib-cat3.git
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[submodule "hw/mcu/allwinner"]
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path = hw/mcu/allwinner
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url = https://github.com/hathach/allwinner_driver.git
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@ -153,6 +153,12 @@ Notable contributors
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- Add new class driver for DFU Runtime
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`Tian Yunhao <https://github.com/t123yh>`__
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-------------------------------------------
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- Add new DCD port for Allwinner F1C100S/F1C200S
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- Add support for osal_rtx4
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`Timon Skerutsch <https://github.com/PTS93>`__
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----------------------------------------------
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@ -32,6 +32,7 @@ Supported MCUs
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The stack supports the following MCUs:
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- **Allwinner:** F1C100s/F1C200s
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- **Broadcom:** BCM2837, BCM2711
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- **Dialog:** DA1469x
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- **Espressif:** ESP32-S2, ESP32-S3
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@ -188,6 +188,13 @@ flash-jlink: $(BUILD)/$(PROJECT).hex
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flash-stlink: $(BUILD)/$(PROJECT).elf
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STM32_Programmer_CLI --connect port=swd --write $< --go
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$(BUILD)/$(PROJECT)-sunxi.bin: $(BUILD)/$(PROJECT).bin
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$(PYTHON) $(TOP)/tools/mksunxi.py $< $@
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flash-xfel: $(BUILD)/$(PROJECT)-sunxi.bin
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xfel spinor write 0 $<
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xfel reset
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# Flash using pyocd
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PYOCD_OPTION ?=
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flash-pyocd: $(BUILD)/$(PROJECT).hex
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@ -0,0 +1,20 @@
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# BSP support for F1Cx00s boards
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This folder contains necessary file and scripts to run TinyUSB examples on F1Cx00s boards.
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Currently tested on:
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- Lichee Pi Nano (F1C100s)
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- [Widora Tiny200 v2 (also called MangoPi-R3c)](https://mangopi.org/tiny200)
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## Flashing
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There are two options to put your code into the MCU: `flash` and `exec`. Both modes require you to install [xfel](https://github.com/xboot/xfel) tool to your PATH. You must enter FEL mode before any operation can be done. To enter FEL mode, press BOOT button, then press RESET once, and release BOOT button. You will find VID/PID=1f3a:efe8 on your PC.
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Exec: `make BOARD=f1c100s exec` will just upload the image to the DDR ram and execute it. It will not touch anything in the SPI flash.
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Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then reset the chip to execute it.
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## TODO
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* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX` high speed MCU check in examples (maybe we should extract the logic?)
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@ -0,0 +1 @@
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// Nothing valuable here
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@ -0,0 +1,52 @@
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DEPS_SUBMODULES += hw/mcu/allwinner
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DEFINES += -D__ARM32_ARCH__=5 -D__ARM926EJS__
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CFLAGS += \
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-ffreestanding \
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-std=gnu99 \
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-march=armv5te \
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-mtune=arm926ej-s \
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-mfloat-abi=soft \
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-marm \
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-mno-thumb-interwork \
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-Wno-unused-parameter \
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-Wno-float-equal \
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-DCFG_TUSB_MCU=OPT_MCU_F1C100S \
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-Wno-error=cast-align \
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-Wno-error=address-of-packed-member \
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$(DEFINES)
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LD_FILE = hw/mcu/allwinner/f1c100s/f1c100s.ld
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LDFLAGS += -nostdlib -lgcc
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MCU_DIR = hw/mcu/allwinner/f1c100s
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SRC_C += \
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src/portable/sunxi/dcd_sunxi_musb.c \
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$(MCU_DIR)/machine/sys-uart.c \
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$(MCU_DIR)/machine/exception.c \
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$(MCU_DIR)/machine/sys-clock.c \
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$(MCU_DIR)/machine/sys-copyself.c \
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$(MCU_DIR)/machine/sys-dram.c \
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$(MCU_DIR)/machine/sys-mmu.c \
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$(MCU_DIR)/machine/sys-spi-flash.c \
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$(MCU_DIR)/machine/f1c100s-intc.c \
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$(MCU_DIR)/lib/malloc.c \
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$(MCU_DIR)/lib/printf.c
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SRC_S += \
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$(MCU_DIR)/machine/start.S \
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$(MCU_DIR)/lib/memcpy.S \
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$(MCU_DIR)/lib/memset.S
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INC += \
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$(TOP)/$(MCU_DIR)/include \
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$(TOP)/$(BOARD_PATH)
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# flash target using xfel
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flash: flash-xfel
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exec: $(BUILD)/$(PROJECT).bin
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xfel ddr
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xfel write 0x80000000 $<
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xfel exec 0x80000000
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@ -0,0 +1,130 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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* copies of the Software, and to permit persons to whom the Software is
|
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include <stdint.h>
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#include <malloc.h>
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#include <irqflags.h>
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#include <f1c100s-irq.h>
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#include "bsp/board.h"
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#include "board.h"
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extern void sys_uart_putc(char c);
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//--------------------------------------------------------------------+
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// Board porting API
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//--------------------------------------------------------------------+
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static void timer_init(void);
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void board_init(void)
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{
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arch_local_irq_disable();
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do_init_mem_pool();
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f1c100s_intc_init();
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timer_init();
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printf("Timer INIT done\n");
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arch_local_irq_enable();
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}
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// No LED, no button
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void board_led_write(bool state)
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{
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}
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uint32_t board_button_read(void)
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{
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return 0;
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}
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int board_uart_read(uint8_t* buf, int len)
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{
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return 0;
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}
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int board_uart_write(void const * buf, int len)
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{
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int txsize = len;
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while (txsize--) {
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sys_uart_putc(*(uint8_t const*)buf);
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buf++;
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}
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return len;
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}
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#if CFG_TUSB_OS == OPT_OS_NONE
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volatile uint32_t system_ticks = 0;
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uint32_t board_millis(void)
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{
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return system_ticks;
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}
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static void timer_handler(void)
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{
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volatile uint32_t *temp_addr = (uint32_t *)(0x01C20C00 + 0x04);
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/* clear timer */
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*temp_addr |= 0x01;
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system_ticks++;
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}
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static void timer_init(void) {
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uint32_t temp;
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volatile uint32_t *temp_addr;
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/* reload value */
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temp = 12000000 / 1000;
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temp_addr = (uint32_t *)(0x01C20C00 + 0x14);
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*temp_addr = temp;
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/* continuous | /2 | 24Mhz | reload*/
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temp = (0x00 << 7) | (0x01 << 4) | (0x01 << 2) | (0x00 << 1);
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temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
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*temp_addr &= 0xffffff00;
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*temp_addr |= temp;
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/* open timer irq */
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temp = 0x01 << 0;
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temp_addr = (uint32_t *)(0x01C20C00);
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*temp_addr |= temp;
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/* set init value */
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temp_addr = (uint32_t *)(0x01C20C00 + 0x18);
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*temp_addr = 0;
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/* begin run timer */
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temp = 0x01 << 0;
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temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
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*temp_addr |= temp;
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f1c100s_intc_set_isr(F1C100S_IRQ_TIMER0, timer_handler);
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f1c100s_intc_enable_irq(F1C100S_IRQ_TIMER0);
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}
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#else
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static void timer_init(void) { }
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#endif
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@ -0,0 +1 @@
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Subproject commit 8e5e89e8e132c0fd90e72d5422e5d3d68232b756
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@ -137,9 +137,11 @@
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#define TU_BSWAP16(u16) (__builtin_bswap16(u16))
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#define TU_BSWAP32(u32) (__builtin_bswap32(u32))
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#ifndef __ARMCC_VERSION
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// List of obsolete callback function that is renamed and should not be defined.
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// Put it here since only gcc support this pragma
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#pragma GCC poison tud_vendor_control_request_cb
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#pragma GCC poison tud_vendor_control_request_cb
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#endif
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#elif defined(__TI_COMPILER_VERSION__)
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#define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))
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@ -106,12 +106,12 @@ typedef struct TU_ATTR_ALIGNED(4)
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void dcd_init (uint8_t rhport);
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// Interrupt Handler
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#if __GNUC__
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#if __GNUC__ && !defined(__ARMCC_VERSION)
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wredundant-decls"
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#endif
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void dcd_int_handler(uint8_t rhport);
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#if __GNUC__
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#if __GNUC__ && !defined(__ARMCC_VERSION)
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#pragma GCC diagnostic pop
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#endif
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@ -208,6 +208,10 @@
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#elif TU_CHECK_MCU(OPT_MCU_FT93X)
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#define DCD_ATTR_ENDPOINT_MAX 16
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//------------ Allwinner -------------//
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#elif TU_CHECK_MCU(OPT_MCU_F1C100S)
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#define DCD_ATTR_ENDPOINT_MAX 4
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#else
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#warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
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#define DCD_ATTR_ENDPOINT_MAX 8
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@ -1008,7 +1008,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
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return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t));
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}
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}
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break;
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// break; // unreachable
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case TUSB_DESC_BOS:
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{
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@ -1025,7 +1025,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
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return tud_control_xfer(rhport, p_request, (void*) desc_bos, total_len);
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}
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break;
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// break; // unreachable
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case TUSB_DESC_CONFIGURATION:
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case TUSB_DESC_OTHER_SPEED_CONFIG:
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@ -1051,7 +1051,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
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return tud_control_xfer(rhport, p_request, (void*) desc_config, total_len);
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}
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break;
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// break; // unreachable
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case TUSB_DESC_STRING:
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{
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@ -1064,7 +1064,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
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// first byte of descriptor is its size
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return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_str, tu_desc_len(desc_str));
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}
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break;
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// break; // unreachable
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case TUSB_DESC_DEVICE_QUALIFIER:
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{
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@ -1078,7 +1078,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
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// first byte of descriptor is its size
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return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_qualifier, tu_desc_len(desc_qualifier));
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}
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break;
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// break; // unreachable
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default: return false;
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}
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@ -57,6 +57,8 @@ typedef void (*osal_task_func_t)( void * );
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#include "osal_pico.h"
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#elif CFG_TUSB_OS == OPT_OS_RTTHREAD
|
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#include "osal_rtthread.h"
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#elif CFG_TUSB_OS == OPT_OS_RTX4
|
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#include "osal_rtx4.h"
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#elif CFG_TUSB_OS == OPT_OS_CUSTOM
|
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#include "tusb_os_custom.h" // implemented by application
|
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#else
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@ -67,7 +69,7 @@ typedef void (*osal_task_func_t)( void * );
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// OSAL Porting API
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//--------------------------------------------------------------------+
|
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|
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#if __GNUC__
|
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#if __GNUC__ && !defined(__ARMCC_VERSION)
|
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#pragma GCC diagnostic push
|
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#pragma GCC diagnostic ignored "-Wredundant-decls"
|
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#endif
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||||
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@ -88,7 +90,7 @@ static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
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static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
|
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static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
|
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static inline bool osal_queue_empty(osal_queue_t qhdl);
|
||||
#if __GNUC__
|
||||
#if __GNUC__ && !defined(__ARMCC_VERSION)
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
|
|
|
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|
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@ -0,0 +1,170 @@
|
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/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021 Tian Yunhao (t123yh)
|
||||
* Copyright (c) 2019 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _TUSB_OSAL_RTX4_H_
|
||||
#define _TUSB_OSAL_RTX4_H_
|
||||
|
||||
#include <rtl.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// TASK API
|
||||
//--------------------------------------------------------------------+
|
||||
static inline void osal_task_delay(uint32_t msec)
|
||||
{
|
||||
uint16_t hi = msec >> 16;
|
||||
uint16_t lo = msec;
|
||||
while (hi--) {
|
||||
os_dly_wait(0xFFFE);
|
||||
}
|
||||
os_dly_wait(lo);
|
||||
}
|
||||
|
||||
static inline uint16_t msec2wait(uint32_t msec) {
|
||||
if (msec == OSAL_TIMEOUT_WAIT_FOREVER)
|
||||
return 0xFFFF;
|
||||
else if (msec >= 0xFFFE)
|
||||
return 0xFFFE;
|
||||
else
|
||||
return msec;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Semaphore API
|
||||
//--------------------------------------------------------------------+
|
||||
typedef OS_SEM osal_semaphore_def_t;
|
||||
typedef OS_ID osal_semaphore_t;
|
||||
|
||||
static inline OS_ID osal_semaphore_create(osal_semaphore_def_t* semdef) {
|
||||
os_sem_init(semdef, 0);
|
||||
return semdef;
|
||||
}
|
||||
|
||||
static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
|
||||
if ( !in_isr ) {
|
||||
os_sem_send(sem_hdl);
|
||||
} else {
|
||||
isr_sem_send(sem_hdl);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) {
|
||||
return os_sem_wait(sem_hdl, msec2wait(msec)) != OS_R_TMO;
|
||||
}
|
||||
|
||||
static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
|
||||
// TODO: implement
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MUTEX API (priority inheritance)
|
||||
//--------------------------------------------------------------------+
|
||||
typedef OS_MUT osal_mutex_def_t;
|
||||
typedef OS_ID osal_mutex_t;
|
||||
|
||||
static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
|
||||
{
|
||||
os_mut_init(mdef);
|
||||
return mdef;
|
||||
}
|
||||
|
||||
static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
|
||||
{
|
||||
return os_mut_wait(mutex_hdl, msec2wait(msec)) != OS_R_TMO;
|
||||
}
|
||||
|
||||
static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
|
||||
{
|
||||
return os_mut_release(mutex_hdl) == OS_R_OK;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// QUEUE API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// role device/host is used by OS NONE for mutex (disable usb isr) only
|
||||
#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
|
||||
os_mbx_declare(_name##__mbox, _depth); \
|
||||
_declare_box(_name##__pool, sizeof(_type), _depth); \
|
||||
osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox };
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t depth;
|
||||
uint16_t item_sz;
|
||||
U32* pool;
|
||||
U32* mbox;
|
||||
}osal_queue_def_t;
|
||||
|
||||
typedef osal_queue_def_t* osal_queue_t;
|
||||
|
||||
static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
|
||||
{
|
||||
os_mbx_init(qdef->mbox, (qdef->depth + 4) * 4);
|
||||
_init_box(qdef->pool, ((qdef->item_sz+3)/4)*(qdef->depth) + 3, qdef->item_sz);
|
||||
return qdef;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
|
||||
{
|
||||
void* buf;
|
||||
os_mbx_wait(qhdl->mbox, &buf, 0xFFFF);
|
||||
memcpy(data, buf, qhdl->item_sz);
|
||||
_free_box(qhdl->pool, buf);
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
|
||||
{
|
||||
void* buf = _alloc_box(qhdl->pool);
|
||||
memcpy(buf, data, qhdl->item_sz);
|
||||
if ( !in_isr )
|
||||
{
|
||||
os_mbx_send(qhdl->mbox, buf, 0xFFFF);
|
||||
}
|
||||
else
|
||||
{
|
||||
isr_mbx_send(qhdl->mbox, buf);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_empty(osal_queue_t qhdl)
|
||||
{
|
||||
return os_mbx_check(qhdl->mbox) == qhdl->depth;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_OSAL_FREERTOS_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,643 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021 Koji KITAYAMA
|
||||
* Copyright (c) 2021 Tian Yunhao (t123yh)
|
||||
* Copyright (c) 2021 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _TUSB_MUSB_DEF
|
||||
#define _TUSB_MUSB_DEF
|
||||
|
||||
|
||||
#define USBC_Readb(reg) (*(volatile unsigned char *)(reg))
|
||||
#define USBC_Readw(reg) (*(volatile unsigned short *)(reg))
|
||||
#define USBC_Readl(reg) (*(volatile unsigned long *)(reg))
|
||||
|
||||
#define USBC_Writeb(value, reg) (*(volatile unsigned char *)(reg) = (value))
|
||||
#define USBC_Writew(value, reg) (*(volatile unsigned short *)(reg) = (value))
|
||||
#define USBC_Writel(value, reg) (*(volatile unsigned long *)(reg) = (value))
|
||||
|
||||
|
||||
#define USBC_SetBit_Mask_b(reg,mask) do { \
|
||||
unsigned char _r = USBC_Readb(reg); \
|
||||
_r |= (unsigned char)(mask); \
|
||||
USBC_Writeb(_r,reg); \
|
||||
}while(0)
|
||||
#define USBC_SetBit_Mask_w(reg,mask) do { \
|
||||
unsigned short _r = USBC_Readw(reg); \
|
||||
_r |= (unsigned short)(mask); \
|
||||
USBC_Writew(_r,reg); \
|
||||
}while(0)
|
||||
#define USBC_SetBit_Mask_l(reg,mask) do { \
|
||||
unsigned int _r = USBC_Readl(reg); \
|
||||
_r |= (unsigned int)(mask); \
|
||||
USBC_Writel(_r,reg); \
|
||||
}while(0)
|
||||
|
||||
|
||||
#define USBC_ClrBit_Mask_b(reg,mask) do { \
|
||||
unsigned char _r = USBC_Readb(reg); \
|
||||
_r &= (~(unsigned char)(mask)); \
|
||||
USBC_Writeb(_r,reg); \
|
||||
}while(0);
|
||||
#define USBC_ClrBit_Mask_w(reg,mask) do { \
|
||||
unsigned short _r = USBC_Readw(reg); \
|
||||
_r &= (~(unsigned short)(mask)); \
|
||||
USBC_Writew(_r,reg); \
|
||||
}while(0)
|
||||
#define USBC_ClrBit_Mask_l(reg,mask) do { \
|
||||
unsigned int _r = USBC_Readl(reg); \
|
||||
_r &= (~(unsigned int)(mask)); \
|
||||
USBC_Writel(_r,reg); \
|
||||
}while(0)
|
||||
#define USBC_REG_test_bit_b(bp, reg) (USBC_Readb(reg) & (1 << (bp)))
|
||||
#define USBC_REG_test_bit_w(bp, reg) (USBC_Readw(reg) & (1 << (bp)))
|
||||
#define USBC_REG_test_bit_l(bp, reg) (USBC_Readl(reg) & (1 << (bp)))
|
||||
|
||||
#define USBC_REG_set_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) | (1 << (bp))) , (reg)))
|
||||
#define USBC_REG_set_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) | (1 << (bp))) , (reg)))
|
||||
#define USBC_REG_set_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) | (1 << (bp))) , (reg)))
|
||||
|
||||
#define USBC_REG_clear_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) & (~ (1 << (bp)))) , (reg)))
|
||||
#define USBC_REG_clear_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) & (~ (1 << (bp)))) , (reg)))
|
||||
#define USBC_REG_clear_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) & (~ (1 << (bp)))) , (reg)))
|
||||
|
||||
#define SW_UDC_EPNUMS 3
|
||||
|
||||
#define SUNXI_SRAMC_BASE 0x01c00000
|
||||
//---------------------------------------------------------------
|
||||
// reg base
|
||||
//---------------------------------------------------------------
|
||||
#define USBC0_BASE 0x01c13000
|
||||
#define USBC1_BASE 0x01c14000
|
||||
#define USBC2_BASE 0x01c1E000
|
||||
|
||||
//Some reg whithin musb
|
||||
#define USBPHY_CLK_REG 0x01c200CC
|
||||
#define USBPHY_CLK_RST_BIT 0
|
||||
#define USBPHY_CLK_GAT_BIT 1
|
||||
|
||||
#define BUS_CLK_RST_REG 0x01c202c0 //Bus Clock Reset Register Bit24 : USB CLK RST
|
||||
#define BUS_RST_USB_BIT 24
|
||||
|
||||
#define BUS_CLK_GATE0_REG 0x01c20060 //Bus Clock Gating Register Bit24 : USB CLK GATE 0: Mask 1 : Pass
|
||||
#define BUS_CLK_USB_BIT 24
|
||||
|
||||
//#define USB_INTR
|
||||
|
||||
#define NDMA_CFG_REG
|
||||
//-----------------------------------------------------------------------
|
||||
// musb reg offset
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define USBC_REG_o_FADDR 0x0098
|
||||
#define USBC_REG_o_PCTL 0x0040
|
||||
#define USBC_REG_o_INTTx 0x0044
|
||||
#define USBC_REG_o_INTRx 0x0046
|
||||
#define USBC_REG_o_INTTxE 0x0048
|
||||
#define USBC_REG_o_INTRxE 0x004A
|
||||
#define USBC_REG_o_INTUSB 0x004C
|
||||
#define USBC_REG_o_INTUSBE 0x0050
|
||||
#define USBC_REG_o_FRNUM 0x0054
|
||||
#define USBC_REG_o_EPIND 0x0042
|
||||
#define USBC_REG_o_TMCTL 0x007C
|
||||
|
||||
#define USBC_REG_o_TXMAXP 0x0080
|
||||
#define USBC_REG_o_CSR0 0x0082
|
||||
#define USBC_REG_o_TXCSR 0x0082
|
||||
#define USBC_REG_o_RXMAXP 0x0084
|
||||
#define USBC_REG_o_RXCSR 0x0086
|
||||
#define USBC_REG_o_COUNT0 0x0088
|
||||
#define USBC_REG_o_RXCOUNT 0x0088
|
||||
#define USBC_REG_o_EP0TYPE 0x008C
|
||||
#define USBC_REG_o_TXTYPE 0x008C
|
||||
#define USBC_REG_o_NAKLIMIT0 0x008D
|
||||
#define USBC_REG_o_TXINTERVAL 0x008D
|
||||
#define USBC_REG_o_RXTYPE 0x008E
|
||||
#define USBC_REG_o_RXINTERVAL 0x008F
|
||||
|
||||
//#define USBC_REG_o_CONFIGDATA 0x001F //
|
||||
|
||||
#define USBC_REG_o_EPFIFO0 0x0000
|
||||
#define USBC_REG_o_EPFIFO1 0x0004
|
||||
#define USBC_REG_o_EPFIFO2 0x0008
|
||||
#define USBC_REG_o_EPFIFO3 0x000C
|
||||
#define USBC_REG_o_EPFIFO4 0x0010
|
||||
#define USBC_REG_o_EPFIFO5 0x0014
|
||||
#define USBC_REG_o_EPFIFOx(n) (0x0000 + (n<<2))
|
||||
|
||||
#define USBC_REG_o_DEVCTL 0x0041
|
||||
|
||||
#define USBC_REG_o_TXFIFOSZ 0x0090
|
||||
#define USBC_REG_o_RXFIFOSZ 0x0094
|
||||
#define USBC_REG_o_TXFIFOAD 0x0092
|
||||
#define USBC_REG_o_RXFIFOAD 0x0096
|
||||
|
||||
#define USBC_REG_o_VEND0 0x0043
|
||||
#define USBC_REG_o_VEND1 0x007D
|
||||
#define USBC_REG_o_VEND3 0x007E
|
||||
|
||||
//#define USBC_REG_o_PHYCTL 0x006C
|
||||
#define USBC_REG_o_EPINFO 0x0078
|
||||
#define USBC_REG_o_RAMINFO 0x0079
|
||||
#define USBC_REG_o_LINKINFO 0x007A
|
||||
#define USBC_REG_o_VPLEN 0x007B
|
||||
#define USBC_REG_o_HSEOF 0x007C
|
||||
#define USBC_REG_o_FSEOF 0x007D
|
||||
#define USBC_REG_o_LSEOF 0x007E
|
||||
|
||||
//new
|
||||
#define USBC_REG_o_FADDR0 0x0098
|
||||
#define USBC_REG_o_HADDR0 0x009A
|
||||
#define USBC_REG_o_HPORT0 0x009B
|
||||
#define USBC_REG_o_TXFADDRx 0x0098
|
||||
#define USBC_REG_o_TXHADDRx 0x009A
|
||||
#define USBC_REG_o_TXHPORTx 0x009B
|
||||
#define USBC_REG_o_RXFADDRx 0x009C
|
||||
#define USBC_REG_o_RXHADDRx 0x009E
|
||||
#define USBC_REG_o_RXHPORTx 0x009F
|
||||
|
||||
|
||||
#define USBC_REG_o_RPCOUNT 0x008A
|
||||
|
||||
//new
|
||||
#define USBC_REG_o_ISCR 0x0400
|
||||
#define USBC_REG_o_PHYCTL 0x0404
|
||||
#define USBC_REG_o_PHYBIST 0x0408
|
||||
#define USBC_REG_o_PHYTUNE 0x040c
|
||||
|
||||
#define USBC_REG_o_CSR 0x0410
|
||||
|
||||
#define USBC_REG_o_PMU_IRQ 0x0800
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// registers
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define USBC_REG_FADDR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_FADDR )
|
||||
#define USBC_REG_PCTL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PCTL )
|
||||
#define USBC_REG_INTTx(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTTx )
|
||||
#define USBC_REG_INTRx(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTRx )
|
||||
#define USBC_REG_INTTxE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTTxE )
|
||||
#define USBC_REG_INTRxE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTRxE )
|
||||
#define USBC_REG_INTUSB(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTUSB )
|
||||
#define USBC_REG_INTUSBE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTUSBE )
|
||||
#define USBC_REG_FRNUM(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_FRNUM )
|
||||
#define USBC_REG_EPIND(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPIND )
|
||||
#define USBC_REG_TMCTL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TMCTL )
|
||||
#define USBC_REG_TXMAXP(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXMAXP )
|
||||
|
||||
#define USBC_REG_CSR0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_CSR0 )
|
||||
#define USBC_REG_TXCSR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXCSR )
|
||||
|
||||
#define USBC_REG_RXMAXP(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXMAXP )
|
||||
#define USBC_REG_RXCSR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXCSR )
|
||||
|
||||
#define USBC_REG_COUNT0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_COUNT0 )
|
||||
#define USBC_REG_RXCOUNT(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXCOUNT )
|
||||
|
||||
#define USBC_REG_EP0TYPE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EP0TYPE )
|
||||
#define USBC_REG_TXTYPE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXTYPE )
|
||||
|
||||
#define USBC_REG_NAKLIMIT0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_NAKLIMIT0 )
|
||||
#define USBC_REG_TXINTERVAL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXINTERVAL )
|
||||
|
||||
#define USBC_REG_RXTYPE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXTYPE )
|
||||
#define USBC_REG_RXINTERVAL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXINTERVAL )
|
||||
//#define USBC_REG_CONFIGDATA(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_CONFIGDATA )
|
||||
#define USBC_REG_EPFIFO0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO0 )
|
||||
#define USBC_REG_EPFIFO1(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO1 )
|
||||
#define USBC_REG_EPFIFO2(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO2 )
|
||||
#define USBC_REG_EPFIFO3(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO3 )
|
||||
#define USBC_REG_EPFIFO4(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO4 )
|
||||
#define USBC_REG_EPFIFO5(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO5 )
|
||||
#define USBC_REG_EPFIFOx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_EPFIFOx(n) )
|
||||
#define USBC_REG_DEVCTL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_DEVCTL )
|
||||
#define USBC_REG_TXFIFOSZ(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXFIFOSZ )
|
||||
#define USBC_REG_RXFIFOSZ(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXFIFOSZ )
|
||||
#define USBC_REG_TXFIFOAD(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXFIFOAD )
|
||||
#define USBC_REG_RXFIFOAD(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXFIFOAD )
|
||||
#define USBC_REG_VEND0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_VEND0 )
|
||||
#define USBC_REG_VEND1(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_VEND1 )
|
||||
#define USBC_REG_EPINFO(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPINFO )
|
||||
#define USBC_REG_RAMINFO(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RAMINFO )
|
||||
#define USBC_REG_LINKINFO(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_LINKINFO )
|
||||
#define USBC_REG_VPLEN(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_VPLEN )
|
||||
#define USBC_REG_HSEOF(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_HSEOF )
|
||||
#define USBC_REG_FSEOF(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_FSEOF )
|
||||
#define USBC_REG_LSEOF(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_LSEOF )
|
||||
|
||||
#define USBC_REG_FADDR0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_FADDR0 )
|
||||
#define USBC_REG_HADDR0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_HADDR0 )
|
||||
#define USBC_REG_HPORT0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_HPORT0 )
|
||||
|
||||
#define USBC_REG_TXFADDRx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_TXFADDRx )
|
||||
#define USBC_REG_TXHADDRx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_TXHADDRx )
|
||||
#define USBC_REG_TXHPORTx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_TXHPORTx )
|
||||
#define USBC_REG_RXFADDRx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_RXFADDRx )
|
||||
#define USBC_REG_RXHADDRx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_RXHADDRx )
|
||||
#define USBC_REG_RXHPORTx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_RXHPORTx )
|
||||
|
||||
#define USBC_REG_RPCOUNTx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_RPCOUNT )
|
||||
|
||||
#define USBC_REG_ISCR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_ISCR )
|
||||
#define USBC_REG_PHYCTL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PHYCTL )
|
||||
#define USBC_REG_PHYBIST(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PHYBIST )
|
||||
#define USBC_REG_PHYTUNE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PHYTUNE )
|
||||
#define USBC_REG_PMU_IRQ(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PMU_IRQ )
|
||||
#define USBC_REG_CSR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_CSR)
|
||||
//-----------------------------------------------------------------------
|
||||
// bit position
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
/* USB Power Control for Host only */
|
||||
#define USBC_BP_POWER_H_HIGH_SPEED_EN 5
|
||||
#define USBC_BP_POWER_H_HIGH_SPEED_FLAG 4
|
||||
#define USBC_BP_POWER_H_RESET 3
|
||||
#define USBC_BP_POWER_H_RESUME 2
|
||||
#define USBC_BP_POWER_H_SUSPEND 1
|
||||
#define USBC_BP_POWER_H_SUEPEND_EN 0
|
||||
|
||||
/* USB Power Control for device only */
|
||||
#define USBC_BP_POWER_D_ISO_UPDATE_EN 7
|
||||
#define USBC_BP_POWER_D_SOFT_CONNECT 6
|
||||
#define USBC_BP_POWER_D_HIGH_SPEED_EN 5
|
||||
#define USBC_BP_POWER_D_HIGH_SPEED_FLAG 4
|
||||
#define USBC_BP_POWER_D_RESET_FLAG 3
|
||||
#define USBC_BP_POWER_D_RESUME 2
|
||||
#define USBC_BP_POWER_D_SUSPEND 1
|
||||
#define USBC_BP_POWER_D_ENABLE_SUSPENDM 0
|
||||
|
||||
/* interrupt flags for ep0 and the Tx ep1~4 */
|
||||
#define USBC_BP_INTTx_FLAG_EP5 5
|
||||
#define USBC_BP_INTTx_FLAG_EP4 4
|
||||
#define USBC_BP_INTTx_FLAG_EP3 3
|
||||
#define USBC_BP_INTTx_FLAG_EP2 2
|
||||
#define USBC_BP_INTTx_FLAG_EP1 1
|
||||
#define USBC_BP_INTTx_FLAG_EP0 0
|
||||
|
||||
/* interrupt flags for Rx ep1~4 */
|
||||
#define USBC_BP_INTRx_FLAG_EP5 5
|
||||
#define USBC_BP_INTRx_FLAG_EP4 4
|
||||
#define USBC_BP_INTRx_FLAG_EP3 3
|
||||
#define USBC_BP_INTRx_FLAG_EP2 2
|
||||
#define USBC_BP_INTRx_FLAG_EP1 1
|
||||
|
||||
/* interrupt enable for Tx ep0~4 */
|
||||
#define USBC_BP_INTTxE_EN_EP5 5
|
||||
#define USBC_BP_INTTxE_EN_EP4 4
|
||||
#define USBC_BP_INTTxE_EN_EP3 3
|
||||
#define USBC_BP_INTTxE_EN_EP2 2
|
||||
#define USBC_BP_INTTxE_EN_EP1 1
|
||||
#define USBC_BP_INTTxE_EN_EP0 0
|
||||
|
||||
/* interrupt enable for Rx ep1~4 */
|
||||
#define USBC_BP_INTRxE_EN_EP5 5
|
||||
#define USBC_BP_INTRxE_EN_EP4 4
|
||||
#define USBC_BP_INTRxE_EN_EP3 3
|
||||
#define USBC_BP_INTRxE_EN_EP2 2
|
||||
#define USBC_BP_INTRxE_EN_EP1 1
|
||||
|
||||
/* USB interrupt */
|
||||
#define USBC_BP_INTUSB_VBUS_ERROR 7
|
||||
#define USBC_BP_INTUSB_SESSION_REQ 6
|
||||
#define USBC_BP_INTUSB_DISCONNECT 5
|
||||
#define USBC_BP_INTUSB_CONNECT 4
|
||||
#define USBC_BP_INTUSB_SOF 3
|
||||
#define USBC_BP_INTUSB_RESET 2
|
||||
#define USBC_BP_INTUSB_RESUME 1
|
||||
#define USBC_BP_INTUSB_SUSPEND 0
|
||||
|
||||
/* USB interrupt enable */
|
||||
#define USBC_BP_INTUSBE_EN_VBUS_ERROR 7
|
||||
#define USBC_BP_INTUSBE_EN_SESSION_REQ 6
|
||||
#define USBC_BP_INTUSBE_EN_DISCONNECT 5
|
||||
#define USBC_BP_INTUSBE_EN_CONNECT 4
|
||||
#define USBC_BP_INTUSBE_EN_SOF 3
|
||||
#define USBC_BP_INTUSBE_EN_RESET 2
|
||||
#define USBC_BP_INTUSBE_EN_RESUME 1
|
||||
#define USBC_BP_INTUSBE_EN_SUSPEND 0
|
||||
|
||||
/* Test Mode Control */
|
||||
#define USBC_BP_TMCTL_FORCE_HOST 7
|
||||
#define USBC_BP_TMCTL_FIFO_ACCESS 6
|
||||
#define USBC_BP_TMCTL_FORCE_FS 5
|
||||
#define USBC_BP_TMCTL_FORCE_HS 4
|
||||
#define USBC_BP_TMCTL_TEST_PACKET 3
|
||||
#define USBC_BP_TMCTL_TEST_K 2
|
||||
#define USBC_BP_TMCTL_TEST_J 1
|
||||
#define USBC_BP_TMCTL_TEST_SE0_NAK 0
|
||||
|
||||
/* Tx Max packet */
|
||||
#define USBC_BP_TXMAXP_PACKET_COUNT 11
|
||||
#define USBC_BP_TXMAXP_MAXIMUM_PAYLOAD 0
|
||||
|
||||
/* Control and Status Register for ep0 for Host only */
|
||||
#define USBC_BP_CSR0_H_DisPing 11
|
||||
#define USBC_BP_CSR0_H_FlushFIFO 8
|
||||
#define USBC_BP_CSR0_H_NAK_Timeout 7
|
||||
#define USBC_BP_CSR0_H_StatusPkt 6
|
||||
#define USBC_BP_CSR0_H_ReqPkt 5
|
||||
#define USBC_BP_CSR0_H_Error 4
|
||||
#define USBC_BP_CSR0_H_SetupPkt 3
|
||||
#define USBC_BP_CSR0_H_RxStall 2
|
||||
#define USBC_BP_CSR0_H_TxPkRdy 1
|
||||
#define USBC_BP_CSR0_H_RxPkRdy 0
|
||||
|
||||
/* Control and Status Register for ep0 for device only */
|
||||
#define USBC_BP_CSR0_D_FLUSH_FIFO 8
|
||||
#define USBC_BP_CSR0_D_SERVICED_SETUP_END 7
|
||||
#define USBC_BP_CSR0_D_SERVICED_RX_PKT_READY 6
|
||||
#define USBC_BP_CSR0_D_SEND_STALL 5
|
||||
#define USBC_BP_CSR0_D_SETUP_END 4
|
||||
#define USBC_BP_CSR0_D_DATA_END 3
|
||||
#define USBC_BP_CSR0_D_SENT_STALL 2
|
||||
#define USBC_BP_CSR0_D_TX_PKT_READY 1
|
||||
#define USBC_BP_CSR0_D_RX_PKT_READY 0
|
||||
|
||||
/* Tx ep Control and Status Register for Host only */
|
||||
#define USBC_BP_TXCSR_H_AUTOSET 15
|
||||
#define USBC_BP_TXCSR_H_RESERVED 14
|
||||
#define USBC_BP_TXCSR_H_MODE 13
|
||||
#define USBC_BP_TXCSR_H_DMA_REQ_EN 12
|
||||
#define USBC_BP_TXCSR_H_FORCE_DATA_TOGGLE 11
|
||||
#define USBC_BP_TXCSR_H_DMA_REQ_MODE 10
|
||||
#define USBC_BP_TXCSR_H_NAK_TIMEOUT 7
|
||||
#define USBC_BP_TXCSR_H_CLEAR_DATA_TOGGLE 6
|
||||
#define USBC_BP_TXCSR_H_TX_STALL 5
|
||||
#define USBC_BP_TXCSR_H_FLUSH_FIFO 3
|
||||
#define USBC_BP_TXCSR_H_ERROR 2
|
||||
#define USBC_BP_TXCSR_H_FIFO_NOT_EMPTY 1
|
||||
#define USBC_BP_TXCSR_H_TX_READY 0
|
||||
|
||||
/* Tx ep Control and Status Register for Device only */
|
||||
#define USBC_BP_TXCSR_D_AUTOSET 15
|
||||
#define USBC_BP_TXCSR_D_ISO 14
|
||||
#define USBC_BP_TXCSR_D_MODE 13
|
||||
#define USBC_BP_TXCSR_D_DMA_REQ_EN 12
|
||||
#define USBC_BP_TXCSR_D_FORCE_DATA_TOGGLE 11
|
||||
#define USBC_BP_TXCSR_D_DMA_REQ_MODE 10
|
||||
#define USBC_BP_TXCSR_D_INCOMPLETE 7
|
||||
#define USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE 6
|
||||
#define USBC_BP_TXCSR_D_SENT_STALL 5
|
||||
#define USBC_BP_TXCSR_D_SEND_STALL 4
|
||||
#define USBC_BP_TXCSR_D_FLUSH_FIFO 3
|
||||
#define USBC_BP_TXCSR_D_UNDER_RUN 2
|
||||
#define USBC_BP_TXCSR_D_FIFO_NOT_EMPTY 1
|
||||
#define USBC_BP_TXCSR_D_TX_READY 0
|
||||
|
||||
/* Rx Max Packet */
|
||||
#define USBC_BP_RXMAXP_PACKET_COUNT 11
|
||||
#define USBC_BP_RXMAXP_MAXIMUM_PAYLOAD 0
|
||||
|
||||
/* Rx ep Control and Status Register for Host only */
|
||||
#define USBC_BP_RXCSR_H_AUTO_CLEAR 15
|
||||
#define USBC_BP_RXCSR_H_AUTO_REQ 14
|
||||
#define USBC_BP_RXCSR_H_DMA_REQ_EN 13
|
||||
#define USBC_BP_RXCSR_H_PID_ERROR 12
|
||||
#define USBC_BP_RXCSR_H_DMA_REQ_MODE 11
|
||||
|
||||
#define USBC_BP_RXCSR_H_INCOMPLETE 8
|
||||
#define USBC_BP_RXCSR_H_CLEAR_DATA_TOGGLE 7
|
||||
#define USBC_BP_RXCSR_H_RX_STALL 6
|
||||
#define USBC_BP_RXCSR_H_REQ_PACKET 5
|
||||
#define USBC_BP_RXCSR_H_FLUSH_FIFO 4
|
||||
#define USBC_BP_RXCSR_H_NAK_TIMEOUT 3
|
||||
#define USBC_BP_RXCSR_H_ERROR 2
|
||||
#define USBC_BP_RXCSR_H_FIFO_FULL 1
|
||||
#define USBC_BP_RXCSR_H_RX_PKT_READY 0
|
||||
|
||||
/* Rx ep Control and Status Register for Device only */
|
||||
#define USBC_BP_RXCSR_D_AUTO_CLEAR 15
|
||||
#define USBC_BP_RXCSR_D_ISO 14
|
||||
#define USBC_BP_RXCSR_D_DMA_REQ_EN 13
|
||||
#define USBC_BP_RXCSR_D_DISABLE_NYET 12
|
||||
#define USBC_BP_RXCSR_D_DMA_REQ_MODE 11
|
||||
|
||||
#define USBC_BP_RXCSR_D_INCOMPLETE 8
|
||||
#define USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE 7
|
||||
#define USBC_BP_RXCSR_D_SENT_STALL 6
|
||||
#define USBC_BP_RXCSR_D_SEND_STALL 5
|
||||
#define USBC_BP_RXCSR_D_FLUSH_FIFO 4
|
||||
#define USBC_BP_RXCSR_D_DATA_ERROR 3
|
||||
#define USBC_BP_RXCSR_D_OVERRUN 2
|
||||
#define USBC_BP_RXCSR_D_FIFO_FULL 1
|
||||
#define USBC_BP_RXCSR_D_RX_PKT_READY 0
|
||||
|
||||
/* Tx Type Register for host only */
|
||||
#define USBC_BP_TXTYPE_SPEED 6 //new
|
||||
#define USBC_BP_TXTYPE_PROROCOL 4
|
||||
#define USBC_BP_TXTYPE_TARGET_EP_NUM 0
|
||||
|
||||
/* Rx Type Register for host only */
|
||||
#define USBC_BP_RXTYPE_SPEED 6 //new
|
||||
#define USBC_BP_RXTYPE_PROROCOL 4
|
||||
#define USBC_BP_RXTYPE_TARGET_EP_NUM 0
|
||||
|
||||
/* Core Configueation */
|
||||
#define USBC_BP_CONFIGDATA_MPRXE 7
|
||||
#define USBC_BP_CONFIGDATA_MPTXE 6
|
||||
#define USBC_BP_CONFIGDATA_BIGENDIAN 5
|
||||
#define USBC_BP_CONFIGDATA_HBRXE 4
|
||||
#define USBC_BP_CONFIGDATA_HBTXE 3
|
||||
#define USBC_BP_CONFIGDATA_DYNFIFO_SIZING 2
|
||||
#define USBC_BP_CONFIGDATA_SOFTCONE 1
|
||||
#define USBC_BP_CONFIGDATA_UTMI_DATAWIDTH 0
|
||||
|
||||
/* OTG Device Control */
|
||||
#define USBC_BP_DEVCTL_B_DEVICE 7
|
||||
#define USBC_BP_DEVCTL_FS_DEV 6
|
||||
#define USBC_BP_DEVCTL_LS_DEV 5
|
||||
|
||||
#define USBC_BP_DEVCTL_VBUS 3
|
||||
#define USBC_BP_DEVCTL_HOST_MODE 2
|
||||
#define USBC_BP_DEVCTL_HOST_REQ 1
|
||||
#define USBC_BP_DEVCTL_SESSION 0
|
||||
|
||||
/* Tx EP FIFO size control */
|
||||
#define USBC_BP_TXFIFOSZ_DPB 4
|
||||
#define USBC_BP_TXFIFOSZ_SZ 0
|
||||
|
||||
/* Rx EP FIFO size control */
|
||||
#define USBC_BP_RXFIFOSZ_DPB 4
|
||||
#define USBC_BP_RXFIFOSZ_SZ 0
|
||||
|
||||
/* vendor0 */
|
||||
#define USBC_BP_VEND0_DRQ_SEL 1
|
||||
#define USBC_BP_VEND0_BUS_SEL 0
|
||||
|
||||
/* hub address */
|
||||
#define USBC_BP_HADDR_MULTI_TT 7
|
||||
|
||||
/* Interface Status and Control */
|
||||
#define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
|
||||
#define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
|
||||
#define USBC_BP_ISCR_EXT_ID_STATUS 28
|
||||
#define USBC_BP_ISCR_EXT_DM_STATUS 27
|
||||
#define USBC_BP_ISCR_EXT_DP_STATUS 26
|
||||
#define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
|
||||
#define USBC_BP_ISCR_MERGED_ID_STATUS 24
|
||||
|
||||
#define USBC_BP_ISCR_ID_PULLUP_EN 17
|
||||
#define USBC_BP_ISCR_DPDM_PULLUP_EN 16
|
||||
#define USBC_BP_ISCR_FORCE_ID 14
|
||||
#define USBC_BP_ISCR_FORCE_VBUS_VALID 12
|
||||
#define USBC_BP_ISCR_VBUS_VALID_SRC 10
|
||||
|
||||
#define USBC_BP_ISCR_HOSC_EN 7
|
||||
#define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
|
||||
#define USBC_BP_ISCR_ID_CHANGE_DETECT 5
|
||||
#define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
|
||||
#define USBC_BP_ISCR_IRQ_ENABLE 3
|
||||
#define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
|
||||
#define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
|
||||
#define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
|
||||
|
||||
|
||||
#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
|
||||
#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
|
||||
#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
|
||||
#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
|
||||
//-----------------------------------------------------------------------
|
||||
// <20>Զ<EFBFBD><D4B6><EFBFBD>
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
/* usb<73><62>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD> */
|
||||
#define USBC_MAX_CTL_NUM 1
|
||||
#define USBC_MAX_EP_NUM 3 //ep0~2, ep<65>ĸ<EFBFBD><C4B8><EFBFBD>
|
||||
#define USBC_MAX_FIFO_SIZE (2 * 1024)
|
||||
|
||||
/* usb OTG mode */
|
||||
#define USBC_OTG_HOST 0
|
||||
#define USBC_OTG_DEVICE 1
|
||||
|
||||
/* usb device type */
|
||||
#define USBC_DEVICE_HSDEV 0
|
||||
#define USBC_DEVICE_FSDEV 1
|
||||
#define USBC_DEVICE_LSDEV 2
|
||||
|
||||
/* usb transfer type */
|
||||
#define USBC_TS_TYPE_IDLE 0
|
||||
#define USBC_TS_TYPE_CTRL 1
|
||||
#define USBC_TS_TYPE_ISO 2
|
||||
#define USBC_TS_TYPE_INT 3
|
||||
#define USBC_TS_TYPE_BULK 4
|
||||
|
||||
/* usb transfer mode */
|
||||
#define USBC_TS_MODE_UNKOWN 0
|
||||
#define USBC_TS_MODE_LS 1
|
||||
#define USBC_TS_MODE_FS 2
|
||||
#define USBC_TS_MODE_HS 3
|
||||
|
||||
/* usb Vbus status */
|
||||
#define USBC_VBUS_STATUS_BELOW_SESSIONEND 0
|
||||
#define USBC_VBUS_STATUS_ABOVE_SESSIONEND_BELOW_AVALID 1
|
||||
#define USBC_VBUS_STATUS_ABOVE_AVALID_BELOW_VBUSVALID 2
|
||||
#define USBC_VBUS_STATUS_ABOVE_VBUSVALID 3
|
||||
|
||||
/* usb io type */
|
||||
#define USBC_IO_TYPE_PIO 0
|
||||
#define USBC_IO_TYPE_DMA 1
|
||||
|
||||
/* usb ep type */
|
||||
#define USBC_EP_TYPE_IDLE 0
|
||||
#define USBC_EP_TYPE_EP0 1
|
||||
#define USBC_EP_TYPE_TX 2
|
||||
#define USBC_EP_TYPE_RX 3
|
||||
|
||||
/* usb id type */
|
||||
#define USBC_ID_TYPE_DISABLE 0
|
||||
#define USBC_ID_TYPE_HOST 1
|
||||
#define USBC_ID_TYPE_DEVICE 2
|
||||
|
||||
/* usb vbus valid type */
|
||||
#define USBC_VBUS_TYPE_DISABLE 0
|
||||
#define USBC_VBUS_TYPE_LOW 1
|
||||
#define USBC_VBUS_TYPE_HIGH 2
|
||||
|
||||
/* usb a valid source */
|
||||
#define USBC_A_VALID_SOURCE_UTMI_AVALID 0
|
||||
#define USBC_A_VALID_SOURCE_UTMI_VBUS 1
|
||||
|
||||
/* usb device switch */
|
||||
#define USBC_DEVICE_SWITCH_OFF 0
|
||||
#define USBC_DEVICE_SWITCH_ON 1
|
||||
|
||||
/* usb fifo config mode */
|
||||
#define USBC_FIFO_MODE_4K 0
|
||||
#define USBC_FIFO_MODE_8K 1
|
||||
|
||||
/*
|
||||
**************************************************
|
||||
* usb interrupt mask
|
||||
*
|
||||
**************************************************
|
||||
*/
|
||||
|
||||
/* interrupt flags for ep0 and the Tx ep1~4 */
|
||||
#define USBC_INTTx_FLAG_EP5 (1 << USBC_BP_INTTx_FLAG_EP5)
|
||||
#define USBC_INTTx_FLAG_EP4 (1 << USBC_BP_INTTx_FLAG_EP4)
|
||||
#define USBC_INTTx_FLAG_EP3 (1 << USBC_BP_INTTx_FLAG_EP3)
|
||||
#define USBC_INTTx_FLAG_EP2 (1 << USBC_BP_INTTx_FLAG_EP2)
|
||||
#define USBC_INTTx_FLAG_EP1 (1 << USBC_BP_INTTx_FLAG_EP1)
|
||||
#define USBC_INTTx_FLAG_EP0 (1 << USBC_BP_INTTx_FLAG_EP0)
|
||||
|
||||
/* interrupt flags for Rx ep1~4 */
|
||||
#define USBC_INTRx_FLAG_EP5 (1 << USBC_BP_INTRx_FLAG_EP5)
|
||||
#define USBC_INTRx_FLAG_EP4 (1 << USBC_BP_INTRx_FLAG_EP4)
|
||||
#define USBC_INTRx_FLAG_EP3 (1 << USBC_BP_INTRx_FLAG_EP3)
|
||||
#define USBC_INTRx_FLAG_EP2 (1 << USBC_BP_INTRx_FLAG_EP2)
|
||||
#define USBC_INTRx_FLAG_EP1 (1 << USBC_BP_INTRx_FLAG_EP1)
|
||||
|
||||
/* USB interrupt */
|
||||
#define USBC_INTUSB_VBUS_ERROR (1 << USBC_BP_INTUSB_VBUS_ERROR)
|
||||
#define USBC_INTUSB_SESSION_REQ (1 << USBC_BP_INTUSB_SESSION_REQ)
|
||||
#define USBC_INTUSB_DISCONNECT (1 << USBC_BP_INTUSB_DISCONNECT)
|
||||
#define USBC_INTUSB_CONNECT (1 << USBC_BP_INTUSB_CONNECT)
|
||||
#define USBC_INTUSB_SOF (1 << USBC_BP_INTUSB_SOF)
|
||||
#define USBC_INTUSB_RESET (1 << USBC_BP_INTUSB_RESET)
|
||||
#define USBC_INTUSB_RESUME (1 << USBC_BP_INTUSB_RESUME)
|
||||
#define USBC_INTUSB_SUSPEND (1 << USBC_BP_INTUSB_SUSPEND)
|
||||
|
||||
#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
|
||||
#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
|
||||
#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
|
||||
#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
|
||||
#define USB_CSRL0_REQPKT 0x00000020 // Request Packet
|
||||
#define USB_CSRL0_STALL 0x00000020 // Send Stall
|
||||
#define USB_CSRL0_SETEND 0x00000010 // Setup End
|
||||
#define USB_CSRL0_ERROR 0x00000010 // Error
|
||||
#define USB_CSRL0_DATAEND 0x00000008 // Data End
|
||||
#define USB_CSRL0_SETUP 0x00000008 // Setup Packet
|
||||
#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
|
||||
#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
|
||||
#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
|
||||
|
||||
#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
|
||||
#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
|
||||
|
||||
#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
|
||||
#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
|
||||
|
||||
#endif
|
||||
|
|
@ -145,6 +145,9 @@
|
|||
#define OPT_MCU_FT90X 2000 ///< BridgeTek FT90x
|
||||
#define OPT_MCU_FT93X 2001 ///< BridgeTek FT93x
|
||||
|
||||
// Allwinner
|
||||
#define OPT_MCU_F1C100S 2100 ///< Allwinner F1C100s family
|
||||
|
||||
// Helper to check if configured MCU is one of listed
|
||||
// Apply _TU_CHECK_MCU with || as separator to list of input
|
||||
#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m)
|
||||
|
|
@ -160,6 +163,7 @@
|
|||
#define OPT_OS_CUSTOM 4 ///< Custom OS is implemented by application
|
||||
#define OPT_OS_PICO 5 ///< Raspberry Pi Pico SDK
|
||||
#define OPT_OS_RTTHREAD 6 ///< RT-Thread
|
||||
#define OPT_OS_RTX4 7 ///< Keil RTX 4
|
||||
|
||||
// Allow to use command line to change the config name/location
|
||||
#ifdef CFG_TUSB_CONFIG_FILE
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
#!/usr/bin/env python3
|
||||
import sys
|
||||
import struct
|
||||
|
||||
def align(num, alignment):
|
||||
if num % alignment != 0:
|
||||
num += (alignment - num % alignment)
|
||||
return num
|
||||
|
||||
|
||||
def process_file(input, output):
|
||||
with open(input, 'rb') as fin:
|
||||
content = bytearray(fin.read())
|
||||
|
||||
align_value = 512
|
||||
padded_length = align(len(content), align_value)
|
||||
# pad file to actual length
|
||||
content += b'\x00' * (padded_length - len(content))
|
||||
|
||||
struct_format = '<L8sLL'
|
||||
(instruction, magic, checksum, length) = struct.unpack_from(struct_format, content)
|
||||
|
||||
if magic != b'eGON.BT0':
|
||||
print("Magic is invalid:", magic)
|
||||
return 2
|
||||
|
||||
checksum = 0x5F0A6C39
|
||||
length = align(length, align_value)
|
||||
|
||||
struct.pack_into(struct_format, content, 0, instruction, magic, checksum, length)
|
||||
|
||||
checksum = 0
|
||||
for i in range(0, length, 4):
|
||||
(n, ) = struct.unpack_from('<L', content, i)
|
||||
checksum += n
|
||||
checksum %= 4294967296
|
||||
|
||||
struct.pack_into(struct_format, content, 0, instruction, magic, checksum, length)
|
||||
|
||||
with open(output, 'wb') as fout:
|
||||
fout.write(content)
|
||||
return 0
|
||||
|
||||
if __name__ == "__main__":
|
||||
if len(sys.argv) != 3:
|
||||
print("Usage: mksunxi.py input.bin output.bin")
|
||||
exit(1)
|
||||
exit(process_file(sys.argv[1], sys.argv[2]))
|
||||
Loading…
Reference in New Issue